Merge tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[linux-3.10.git] / arch / arm / mach-shmobile / setup-sh7372.c
1 /*
2  * sh7372 processor support
3  *
4  * Copyright (C) 2010  Magnus Damm
5  * Copyright (C) 2008  Yoshihiro Shimoda
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19  */
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/platform_device.h>
25 #include <linux/uio_driver.h>
26 #include <linux/delay.h>
27 #include <linux/input.h>
28 #include <linux/io.h>
29 #include <linux/serial_sci.h>
30 #include <linux/sh_dma.h>
31 #include <linux/sh_intc.h>
32 #include <linux/sh_timer.h>
33 #include <linux/pm_domain.h>
34 #include <mach/hardware.h>
35 #include <mach/sh7372.h>
36 #include <mach/common.h>
37 #include <asm/mach/map.h>
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
41
42 static struct map_desc sh7372_io_desc[] __initdata = {
43         /* create a 1:1 entity map for 0xe6xxxxxx
44          * used by CPGA, INTC and PFC.
45          */
46         {
47                 .virtual        = 0xe6000000,
48                 .pfn            = __phys_to_pfn(0xe6000000),
49                 .length         = 256 << 20,
50                 .type           = MT_DEVICE_NONSHARED
51         },
52 };
53
54 void __init sh7372_map_io(void)
55 {
56         iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
57 }
58
59 /* SCIFA0 */
60 static struct plat_sci_port scif0_platform_data = {
61         .mapbase        = 0xe6c40000,
62         .flags          = UPF_BOOT_AUTOCONF,
63         .scscr          = SCSCR_RE | SCSCR_TE,
64         .scbrr_algo_id  = SCBRR_ALGO_4,
65         .type           = PORT_SCIFA,
66         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
67                             evt2irq(0x0c00), evt2irq(0x0c00) },
68 };
69
70 static struct platform_device scif0_device = {
71         .name           = "sh-sci",
72         .id             = 0,
73         .dev            = {
74                 .platform_data  = &scif0_platform_data,
75         },
76 };
77
78 /* SCIFA1 */
79 static struct plat_sci_port scif1_platform_data = {
80         .mapbase        = 0xe6c50000,
81         .flags          = UPF_BOOT_AUTOCONF,
82         .scscr          = SCSCR_RE | SCSCR_TE,
83         .scbrr_algo_id  = SCBRR_ALGO_4,
84         .type           = PORT_SCIFA,
85         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
86                             evt2irq(0x0c20), evt2irq(0x0c20) },
87 };
88
89 static struct platform_device scif1_device = {
90         .name           = "sh-sci",
91         .id             = 1,
92         .dev            = {
93                 .platform_data  = &scif1_platform_data,
94         },
95 };
96
97 /* SCIFA2 */
98 static struct plat_sci_port scif2_platform_data = {
99         .mapbase        = 0xe6c60000,
100         .flags          = UPF_BOOT_AUTOCONF,
101         .scscr          = SCSCR_RE | SCSCR_TE,
102         .scbrr_algo_id  = SCBRR_ALGO_4,
103         .type           = PORT_SCIFA,
104         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
105                             evt2irq(0x0c40), evt2irq(0x0c40) },
106 };
107
108 static struct platform_device scif2_device = {
109         .name           = "sh-sci",
110         .id             = 2,
111         .dev            = {
112                 .platform_data  = &scif2_platform_data,
113         },
114 };
115
116 /* SCIFA3 */
117 static struct plat_sci_port scif3_platform_data = {
118         .mapbase        = 0xe6c70000,
119         .flags          = UPF_BOOT_AUTOCONF,
120         .scscr          = SCSCR_RE | SCSCR_TE,
121         .scbrr_algo_id  = SCBRR_ALGO_4,
122         .type           = PORT_SCIFA,
123         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
124                             evt2irq(0x0c60), evt2irq(0x0c60) },
125 };
126
127 static struct platform_device scif3_device = {
128         .name           = "sh-sci",
129         .id             = 3,
130         .dev            = {
131                 .platform_data  = &scif3_platform_data,
132         },
133 };
134
135 /* SCIFA4 */
136 static struct plat_sci_port scif4_platform_data = {
137         .mapbase        = 0xe6c80000,
138         .flags          = UPF_BOOT_AUTOCONF,
139         .scscr          = SCSCR_RE | SCSCR_TE,
140         .scbrr_algo_id  = SCBRR_ALGO_4,
141         .type           = PORT_SCIFA,
142         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
143                             evt2irq(0x0d20), evt2irq(0x0d20) },
144 };
145
146 static struct platform_device scif4_device = {
147         .name           = "sh-sci",
148         .id             = 4,
149         .dev            = {
150                 .platform_data  = &scif4_platform_data,
151         },
152 };
153
154 /* SCIFA5 */
155 static struct plat_sci_port scif5_platform_data = {
156         .mapbase        = 0xe6cb0000,
157         .flags          = UPF_BOOT_AUTOCONF,
158         .scscr          = SCSCR_RE | SCSCR_TE,
159         .scbrr_algo_id  = SCBRR_ALGO_4,
160         .type           = PORT_SCIFA,
161         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
162                             evt2irq(0x0d40), evt2irq(0x0d40) },
163 };
164
165 static struct platform_device scif5_device = {
166         .name           = "sh-sci",
167         .id             = 5,
168         .dev            = {
169                 .platform_data  = &scif5_platform_data,
170         },
171 };
172
173 /* SCIFB */
174 static struct plat_sci_port scif6_platform_data = {
175         .mapbase        = 0xe6c30000,
176         .flags          = UPF_BOOT_AUTOCONF,
177         .scscr          = SCSCR_RE | SCSCR_TE,
178         .scbrr_algo_id  = SCBRR_ALGO_4,
179         .type           = PORT_SCIFB,
180         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
181                             evt2irq(0x0d60), evt2irq(0x0d60) },
182 };
183
184 static struct platform_device scif6_device = {
185         .name           = "sh-sci",
186         .id             = 6,
187         .dev            = {
188                 .platform_data  = &scif6_platform_data,
189         },
190 };
191
192 /* CMT */
193 static struct sh_timer_config cmt2_platform_data = {
194         .name = "CMT2",
195         .channel_offset = 0x40,
196         .timer_bit = 5,
197         .clockevent_rating = 125,
198         .clocksource_rating = 125,
199 };
200
201 static struct resource cmt2_resources[] = {
202         [0] = {
203                 .name   = "CMT2",
204                 .start  = 0xe6130040,
205                 .end    = 0xe613004b,
206                 .flags  = IORESOURCE_MEM,
207         },
208         [1] = {
209                 .start  = evt2irq(0x0b80), /* CMT2 */
210                 .flags  = IORESOURCE_IRQ,
211         },
212 };
213
214 static struct platform_device cmt2_device = {
215         .name           = "sh_cmt",
216         .id             = 2,
217         .dev = {
218                 .platform_data  = &cmt2_platform_data,
219         },
220         .resource       = cmt2_resources,
221         .num_resources  = ARRAY_SIZE(cmt2_resources),
222 };
223
224 /* TMU */
225 static struct sh_timer_config tmu00_platform_data = {
226         .name = "TMU00",
227         .channel_offset = 0x4,
228         .timer_bit = 0,
229         .clockevent_rating = 200,
230 };
231
232 static struct resource tmu00_resources[] = {
233         [0] = {
234                 .name   = "TMU00",
235                 .start  = 0xfff60008,
236                 .end    = 0xfff60013,
237                 .flags  = IORESOURCE_MEM,
238         },
239         [1] = {
240                 .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
241                 .flags  = IORESOURCE_IRQ,
242         },
243 };
244
245 static struct platform_device tmu00_device = {
246         .name           = "sh_tmu",
247         .id             = 0,
248         .dev = {
249                 .platform_data  = &tmu00_platform_data,
250         },
251         .resource       = tmu00_resources,
252         .num_resources  = ARRAY_SIZE(tmu00_resources),
253 };
254
255 static struct sh_timer_config tmu01_platform_data = {
256         .name = "TMU01",
257         .channel_offset = 0x10,
258         .timer_bit = 1,
259         .clocksource_rating = 200,
260 };
261
262 static struct resource tmu01_resources[] = {
263         [0] = {
264                 .name   = "TMU01",
265                 .start  = 0xfff60014,
266                 .end    = 0xfff6001f,
267                 .flags  = IORESOURCE_MEM,
268         },
269         [1] = {
270                 .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
271                 .flags  = IORESOURCE_IRQ,
272         },
273 };
274
275 static struct platform_device tmu01_device = {
276         .name           = "sh_tmu",
277         .id             = 1,
278         .dev = {
279                 .platform_data  = &tmu01_platform_data,
280         },
281         .resource       = tmu01_resources,
282         .num_resources  = ARRAY_SIZE(tmu01_resources),
283 };
284
285 /* I2C */
286 static struct resource iic0_resources[] = {
287         [0] = {
288                 .name   = "IIC0",
289                 .start  = 0xFFF20000,
290                 .end    = 0xFFF20425 - 1,
291                 .flags  = IORESOURCE_MEM,
292         },
293         [1] = {
294                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
295                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
296                 .flags  = IORESOURCE_IRQ,
297         },
298 };
299
300 static struct platform_device iic0_device = {
301         .name           = "i2c-sh_mobile",
302         .id             = 0, /* "i2c0" clock */
303         .num_resources  = ARRAY_SIZE(iic0_resources),
304         .resource       = iic0_resources,
305 };
306
307 static struct resource iic1_resources[] = {
308         [0] = {
309                 .name   = "IIC1",
310                 .start  = 0xE6C20000,
311                 .end    = 0xE6C20425 - 1,
312                 .flags  = IORESOURCE_MEM,
313         },
314         [1] = {
315                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
316                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
317                 .flags  = IORESOURCE_IRQ,
318         },
319 };
320
321 static struct platform_device iic1_device = {
322         .name           = "i2c-sh_mobile",
323         .id             = 1, /* "i2c1" clock */
324         .num_resources  = ARRAY_SIZE(iic1_resources),
325         .resource       = iic1_resources,
326 };
327
328 /* DMA */
329 /* Transmit sizes and respective CHCR register values */
330 enum {
331         XMIT_SZ_8BIT            = 0,
332         XMIT_SZ_16BIT           = 1,
333         XMIT_SZ_32BIT           = 2,
334         XMIT_SZ_64BIT           = 7,
335         XMIT_SZ_128BIT          = 3,
336         XMIT_SZ_256BIT          = 4,
337         XMIT_SZ_512BIT          = 5,
338 };
339
340 /* log2(size / 8) - used to calculate number of transfers */
341 #define TS_SHIFT {                      \
342         [XMIT_SZ_8BIT]          = 0,    \
343         [XMIT_SZ_16BIT]         = 1,    \
344         [XMIT_SZ_32BIT]         = 2,    \
345         [XMIT_SZ_64BIT]         = 3,    \
346         [XMIT_SZ_128BIT]        = 4,    \
347         [XMIT_SZ_256BIT]        = 5,    \
348         [XMIT_SZ_512BIT]        = 6,    \
349 }
350
351 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
352                          (((i) & 0xc) << (20 - 2)))
353
354 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
355         {
356                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
357                 .addr           = 0xe6c40020,
358                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
359                 .mid_rid        = 0x21,
360         }, {
361                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
362                 .addr           = 0xe6c40024,
363                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
364                 .mid_rid        = 0x22,
365         }, {
366                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
367                 .addr           = 0xe6c50020,
368                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
369                 .mid_rid        = 0x25,
370         }, {
371                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
372                 .addr           = 0xe6c50024,
373                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
374                 .mid_rid        = 0x26,
375         }, {
376                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
377                 .addr           = 0xe6c60020,
378                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
379                 .mid_rid        = 0x29,
380         }, {
381                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
382                 .addr           = 0xe6c60024,
383                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
384                 .mid_rid        = 0x2a,
385         }, {
386                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
387                 .addr           = 0xe6c70020,
388                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
389                 .mid_rid        = 0x2d,
390         }, {
391                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
392                 .addr           = 0xe6c70024,
393                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
394                 .mid_rid        = 0x2e,
395         }, {
396                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
397                 .addr           = 0xe6c80020,
398                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
399                 .mid_rid        = 0x39,
400         }, {
401                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
402                 .addr           = 0xe6c80024,
403                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
404                 .mid_rid        = 0x3a,
405         }, {
406                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
407                 .addr           = 0xe6cb0020,
408                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
409                 .mid_rid        = 0x35,
410         }, {
411                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
412                 .addr           = 0xe6cb0024,
413                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
414                 .mid_rid        = 0x36,
415         }, {
416                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
417                 .addr           = 0xe6c30040,
418                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
419                 .mid_rid        = 0x3d,
420         }, {
421                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
422                 .addr           = 0xe6c30060,
423                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
424                 .mid_rid        = 0x3e,
425         }, {
426                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
427                 .addr           = 0xe6850030,
428                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
429                 .mid_rid        = 0xc1,
430         }, {
431                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
432                 .addr           = 0xe6850030,
433                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
434                 .mid_rid        = 0xc2,
435         }, {
436                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
437                 .addr           = 0xe6860030,
438                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
439                 .mid_rid        = 0xc9,
440         }, {
441                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
442                 .addr           = 0xe6860030,
443                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
444                 .mid_rid        = 0xca,
445         }, {
446                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
447                 .addr           = 0xe6870030,
448                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
449                 .mid_rid        = 0xcd,
450         }, {
451                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
452                 .addr           = 0xe6870030,
453                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
454                 .mid_rid        = 0xce,
455         }, {
456                 .slave_id       = SHDMA_SLAVE_MMCIF_TX,
457                 .addr           = 0xe6bd0034,
458                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
459                 .mid_rid        = 0xd1,
460         }, {
461                 .slave_id       = SHDMA_SLAVE_MMCIF_RX,
462                 .addr           = 0xe6bd0034,
463                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
464                 .mid_rid        = 0xd2,
465         },
466 };
467
468 #define SH7372_CHCLR 0x220
469
470 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
471         {
472                 .offset = 0,
473                 .dmars = 0,
474                 .dmars_bit = 0,
475                 .chclr_offset = SH7372_CHCLR + 0,
476         }, {
477                 .offset = 0x10,
478                 .dmars = 0,
479                 .dmars_bit = 8,
480                 .chclr_offset = SH7372_CHCLR + 0x10,
481         }, {
482                 .offset = 0x20,
483                 .dmars = 4,
484                 .dmars_bit = 0,
485                 .chclr_offset = SH7372_CHCLR + 0x20,
486         }, {
487                 .offset = 0x30,
488                 .dmars = 4,
489                 .dmars_bit = 8,
490                 .chclr_offset = SH7372_CHCLR + 0x30,
491         }, {
492                 .offset = 0x50,
493                 .dmars = 8,
494                 .dmars_bit = 0,
495                 .chclr_offset = SH7372_CHCLR + 0x50,
496         }, {
497                 .offset = 0x60,
498                 .dmars = 8,
499                 .dmars_bit = 8,
500                 .chclr_offset = SH7372_CHCLR + 0x60,
501         }
502 };
503
504 static const unsigned int ts_shift[] = TS_SHIFT;
505
506 static struct sh_dmae_pdata dma_platform_data = {
507         .slave          = sh7372_dmae_slaves,
508         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
509         .channel        = sh7372_dmae_channels,
510         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
511         .ts_low_shift   = 3,
512         .ts_low_mask    = 0x18,
513         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
514         .ts_high_mask   = 0x00300000,
515         .ts_shift       = ts_shift,
516         .ts_shift_num   = ARRAY_SIZE(ts_shift),
517         .dmaor_init     = DMAOR_DME,
518         .chclr_present  = 1,
519 };
520
521 /* Resource order important! */
522 static struct resource sh7372_dmae0_resources[] = {
523         {
524                 /* Channel registers and DMAOR */
525                 .start  = 0xfe008020,
526                 .end    = 0xfe00828f,
527                 .flags  = IORESOURCE_MEM,
528         },
529         {
530                 /* DMARSx */
531                 .start  = 0xfe009000,
532                 .end    = 0xfe00900b,
533                 .flags  = IORESOURCE_MEM,
534         },
535         {
536                 .name   = "error_irq",
537                 .start  = evt2irq(0x20c0),
538                 .end    = evt2irq(0x20c0),
539                 .flags  = IORESOURCE_IRQ,
540         },
541         {
542                 /* IRQ for channels 0-5 */
543                 .start  = evt2irq(0x2000),
544                 .end    = evt2irq(0x20a0),
545                 .flags  = IORESOURCE_IRQ,
546         },
547 };
548
549 /* Resource order important! */
550 static struct resource sh7372_dmae1_resources[] = {
551         {
552                 /* Channel registers and DMAOR */
553                 .start  = 0xfe018020,
554                 .end    = 0xfe01828f,
555                 .flags  = IORESOURCE_MEM,
556         },
557         {
558                 /* DMARSx */
559                 .start  = 0xfe019000,
560                 .end    = 0xfe01900b,
561                 .flags  = IORESOURCE_MEM,
562         },
563         {
564                 .name   = "error_irq",
565                 .start  = evt2irq(0x21c0),
566                 .end    = evt2irq(0x21c0),
567                 .flags  = IORESOURCE_IRQ,
568         },
569         {
570                 /* IRQ for channels 0-5 */
571                 .start  = evt2irq(0x2100),
572                 .end    = evt2irq(0x21a0),
573                 .flags  = IORESOURCE_IRQ,
574         },
575 };
576
577 /* Resource order important! */
578 static struct resource sh7372_dmae2_resources[] = {
579         {
580                 /* Channel registers and DMAOR */
581                 .start  = 0xfe028020,
582                 .end    = 0xfe02828f,
583                 .flags  = IORESOURCE_MEM,
584         },
585         {
586                 /* DMARSx */
587                 .start  = 0xfe029000,
588                 .end    = 0xfe02900b,
589                 .flags  = IORESOURCE_MEM,
590         },
591         {
592                 .name   = "error_irq",
593                 .start  = evt2irq(0x22c0),
594                 .end    = evt2irq(0x22c0),
595                 .flags  = IORESOURCE_IRQ,
596         },
597         {
598                 /* IRQ for channels 0-5 */
599                 .start  = evt2irq(0x2200),
600                 .end    = evt2irq(0x22a0),
601                 .flags  = IORESOURCE_IRQ,
602         },
603 };
604
605 static struct platform_device dma0_device = {
606         .name           = "sh-dma-engine",
607         .id             = 0,
608         .resource       = sh7372_dmae0_resources,
609         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
610         .dev            = {
611                 .platform_data  = &dma_platform_data,
612         },
613 };
614
615 static struct platform_device dma1_device = {
616         .name           = "sh-dma-engine",
617         .id             = 1,
618         .resource       = sh7372_dmae1_resources,
619         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
620         .dev            = {
621                 .platform_data  = &dma_platform_data,
622         },
623 };
624
625 static struct platform_device dma2_device = {
626         .name           = "sh-dma-engine",
627         .id             = 2,
628         .resource       = sh7372_dmae2_resources,
629         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
630         .dev            = {
631                 .platform_data  = &dma_platform_data,
632         },
633 };
634
635 /*
636  * USB-DMAC
637  */
638
639 unsigned int usbts_shift[] = {3, 4, 5};
640
641 enum {
642         XMIT_SZ_8BYTE           = 0,
643         XMIT_SZ_16BYTE          = 1,
644         XMIT_SZ_32BYTE          = 2,
645 };
646
647 #define USBTS_INDEX2VAL(i) (((i) & 3) << 6)
648
649 static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
650         {
651                 .offset = 0,
652         }, {
653                 .offset = 0x20,
654         },
655 };
656
657 /* USB DMAC0 */
658 static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
659         {
660                 .slave_id       = SHDMA_SLAVE_USB0_TX,
661                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
662         }, {
663                 .slave_id       = SHDMA_SLAVE_USB0_RX,
664                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
665         },
666 };
667
668 static struct sh_dmae_pdata usb_dma0_platform_data = {
669         .slave          = sh7372_usb_dmae0_slaves,
670         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
671         .channel        = sh7372_usb_dmae_channels,
672         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
673         .ts_low_shift   = 6,
674         .ts_low_mask    = 0xc0,
675         .ts_high_shift  = 0,
676         .ts_high_mask   = 0,
677         .ts_shift       = usbts_shift,
678         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
679         .dmaor_init     = DMAOR_DME,
680         .chcr_offset    = 0x14,
681         .chcr_ie_bit    = 1 << 5,
682         .dmaor_is_32bit = 1,
683         .needs_tend_set = 1,
684         .no_dmars       = 1,
685         .slave_only     = 1,
686 };
687
688 static struct resource sh7372_usb_dmae0_resources[] = {
689         {
690                 /* Channel registers and DMAOR */
691                 .start  = 0xe68a0020,
692                 .end    = 0xe68a0064 - 1,
693                 .flags  = IORESOURCE_MEM,
694         },
695         {
696                 /* VCR/SWR/DMICR */
697                 .start  = 0xe68a0000,
698                 .end    = 0xe68a0014 - 1,
699                 .flags  = IORESOURCE_MEM,
700         },
701         {
702                 /* IRQ for channels */
703                 .start  = evt2irq(0x0a00),
704                 .end    = evt2irq(0x0a00),
705                 .flags  = IORESOURCE_IRQ,
706         },
707 };
708
709 static struct platform_device usb_dma0_device = {
710         .name           = "sh-dma-engine",
711         .id             = 3,
712         .resource       = sh7372_usb_dmae0_resources,
713         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae0_resources),
714         .dev            = {
715                 .platform_data  = &usb_dma0_platform_data,
716         },
717 };
718
719 /* USB DMAC1 */
720 static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
721         {
722                 .slave_id       = SHDMA_SLAVE_USB1_TX,
723                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
724         }, {
725                 .slave_id       = SHDMA_SLAVE_USB1_RX,
726                 .chcr           = USBTS_INDEX2VAL(XMIT_SZ_8BYTE),
727         },
728 };
729
730 static struct sh_dmae_pdata usb_dma1_platform_data = {
731         .slave          = sh7372_usb_dmae1_slaves,
732         .slave_num      = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
733         .channel        = sh7372_usb_dmae_channels,
734         .channel_num    = ARRAY_SIZE(sh7372_usb_dmae_channels),
735         .ts_low_shift   = 6,
736         .ts_low_mask    = 0xc0,
737         .ts_high_shift  = 0,
738         .ts_high_mask   = 0,
739         .ts_shift       = usbts_shift,
740         .ts_shift_num   = ARRAY_SIZE(usbts_shift),
741         .dmaor_init     = DMAOR_DME,
742         .chcr_offset    = 0x14,
743         .chcr_ie_bit    = 1 << 5,
744         .dmaor_is_32bit = 1,
745         .needs_tend_set = 1,
746         .no_dmars       = 1,
747         .slave_only     = 1,
748 };
749
750 static struct resource sh7372_usb_dmae1_resources[] = {
751         {
752                 /* Channel registers and DMAOR */
753                 .start  = 0xe68c0020,
754                 .end    = 0xe68c0064 - 1,
755                 .flags  = IORESOURCE_MEM,
756         },
757         {
758                 /* VCR/SWR/DMICR */
759                 .start  = 0xe68c0000,
760                 .end    = 0xe68c0014 - 1,
761                 .flags  = IORESOURCE_MEM,
762         },
763         {
764                 /* IRQ for channels */
765                 .start  = evt2irq(0x1d00),
766                 .end    = evt2irq(0x1d00),
767                 .flags  = IORESOURCE_IRQ,
768         },
769 };
770
771 static struct platform_device usb_dma1_device = {
772         .name           = "sh-dma-engine",
773         .id             = 4,
774         .resource       = sh7372_usb_dmae1_resources,
775         .num_resources  = ARRAY_SIZE(sh7372_usb_dmae1_resources),
776         .dev            = {
777                 .platform_data  = &usb_dma1_platform_data,
778         },
779 };
780
781 /* VPU */
782 static struct uio_info vpu_platform_data = {
783         .name = "VPU5HG",
784         .version = "0",
785         .irq = intcs_evt2irq(0x980),
786 };
787
788 static struct resource vpu_resources[] = {
789         [0] = {
790                 .name   = "VPU",
791                 .start  = 0xfe900000,
792                 .end    = 0xfe900157,
793                 .flags  = IORESOURCE_MEM,
794         },
795 };
796
797 static struct platform_device vpu_device = {
798         .name           = "uio_pdrv_genirq",
799         .id             = 0,
800         .dev = {
801                 .platform_data  = &vpu_platform_data,
802         },
803         .resource       = vpu_resources,
804         .num_resources  = ARRAY_SIZE(vpu_resources),
805 };
806
807 /* VEU0 */
808 static struct uio_info veu0_platform_data = {
809         .name = "VEU0",
810         .version = "0",
811         .irq = intcs_evt2irq(0x700),
812 };
813
814 static struct resource veu0_resources[] = {
815         [0] = {
816                 .name   = "VEU0",
817                 .start  = 0xfe920000,
818                 .end    = 0xfe9200cb,
819                 .flags  = IORESOURCE_MEM,
820         },
821 };
822
823 static struct platform_device veu0_device = {
824         .name           = "uio_pdrv_genirq",
825         .id             = 1,
826         .dev = {
827                 .platform_data  = &veu0_platform_data,
828         },
829         .resource       = veu0_resources,
830         .num_resources  = ARRAY_SIZE(veu0_resources),
831 };
832
833 /* VEU1 */
834 static struct uio_info veu1_platform_data = {
835         .name = "VEU1",
836         .version = "0",
837         .irq = intcs_evt2irq(0x720),
838 };
839
840 static struct resource veu1_resources[] = {
841         [0] = {
842                 .name   = "VEU1",
843                 .start  = 0xfe924000,
844                 .end    = 0xfe9240cb,
845                 .flags  = IORESOURCE_MEM,
846         },
847 };
848
849 static struct platform_device veu1_device = {
850         .name           = "uio_pdrv_genirq",
851         .id             = 2,
852         .dev = {
853                 .platform_data  = &veu1_platform_data,
854         },
855         .resource       = veu1_resources,
856         .num_resources  = ARRAY_SIZE(veu1_resources),
857 };
858
859 /* VEU2 */
860 static struct uio_info veu2_platform_data = {
861         .name = "VEU2",
862         .version = "0",
863         .irq = intcs_evt2irq(0x740),
864 };
865
866 static struct resource veu2_resources[] = {
867         [0] = {
868                 .name   = "VEU2",
869                 .start  = 0xfe928000,
870                 .end    = 0xfe928307,
871                 .flags  = IORESOURCE_MEM,
872         },
873 };
874
875 static struct platform_device veu2_device = {
876         .name           = "uio_pdrv_genirq",
877         .id             = 3,
878         .dev = {
879                 .platform_data  = &veu2_platform_data,
880         },
881         .resource       = veu2_resources,
882         .num_resources  = ARRAY_SIZE(veu2_resources),
883 };
884
885 /* VEU3 */
886 static struct uio_info veu3_platform_data = {
887         .name = "VEU3",
888         .version = "0",
889         .irq = intcs_evt2irq(0x760),
890 };
891
892 static struct resource veu3_resources[] = {
893         [0] = {
894                 .name   = "VEU3",
895                 .start  = 0xfe92c000,
896                 .end    = 0xfe92c307,
897                 .flags  = IORESOURCE_MEM,
898         },
899 };
900
901 static struct platform_device veu3_device = {
902         .name           = "uio_pdrv_genirq",
903         .id             = 4,
904         .dev = {
905                 .platform_data  = &veu3_platform_data,
906         },
907         .resource       = veu3_resources,
908         .num_resources  = ARRAY_SIZE(veu3_resources),
909 };
910
911 /* JPU */
912 static struct uio_info jpu_platform_data = {
913         .name = "JPU",
914         .version = "0",
915         .irq = intcs_evt2irq(0x560),
916 };
917
918 static struct resource jpu_resources[] = {
919         [0] = {
920                 .name   = "JPU",
921                 .start  = 0xfe980000,
922                 .end    = 0xfe9902d3,
923                 .flags  = IORESOURCE_MEM,
924         },
925 };
926
927 static struct platform_device jpu_device = {
928         .name           = "uio_pdrv_genirq",
929         .id             = 5,
930         .dev = {
931                 .platform_data  = &jpu_platform_data,
932         },
933         .resource       = jpu_resources,
934         .num_resources  = ARRAY_SIZE(jpu_resources),
935 };
936
937 /* SPU2DSP0 */
938 static struct uio_info spu0_platform_data = {
939         .name = "SPU2DSP0",
940         .version = "0",
941         .irq = evt2irq(0x1800),
942 };
943
944 static struct resource spu0_resources[] = {
945         [0] = {
946                 .name   = "SPU2DSP0",
947                 .start  = 0xfe200000,
948                 .end    = 0xfe2fffff,
949                 .flags  = IORESOURCE_MEM,
950         },
951 };
952
953 static struct platform_device spu0_device = {
954         .name           = "uio_pdrv_genirq",
955         .id             = 6,
956         .dev = {
957                 .platform_data  = &spu0_platform_data,
958         },
959         .resource       = spu0_resources,
960         .num_resources  = ARRAY_SIZE(spu0_resources),
961 };
962
963 /* SPU2DSP1 */
964 static struct uio_info spu1_platform_data = {
965         .name = "SPU2DSP1",
966         .version = "0",
967         .irq = evt2irq(0x1820),
968 };
969
970 static struct resource spu1_resources[] = {
971         [0] = {
972                 .name   = "SPU2DSP1",
973                 .start  = 0xfe300000,
974                 .end    = 0xfe3fffff,
975                 .flags  = IORESOURCE_MEM,
976         },
977 };
978
979 static struct platform_device spu1_device = {
980         .name           = "uio_pdrv_genirq",
981         .id             = 7,
982         .dev = {
983                 .platform_data  = &spu1_platform_data,
984         },
985         .resource       = spu1_resources,
986         .num_resources  = ARRAY_SIZE(spu1_resources),
987 };
988
989 static struct platform_device *sh7372_early_devices[] __initdata = {
990         &scif0_device,
991         &scif1_device,
992         &scif2_device,
993         &scif3_device,
994         &scif4_device,
995         &scif5_device,
996         &scif6_device,
997         &cmt2_device,
998         &tmu00_device,
999         &tmu01_device,
1000 };
1001
1002 static struct platform_device *sh7372_late_devices[] __initdata = {
1003         &iic0_device,
1004         &iic1_device,
1005         &dma0_device,
1006         &dma1_device,
1007         &dma2_device,
1008         &usb_dma0_device,
1009         &usb_dma1_device,
1010         &vpu_device,
1011         &veu0_device,
1012         &veu1_device,
1013         &veu2_device,
1014         &veu3_device,
1015         &jpu_device,
1016         &spu0_device,
1017         &spu1_device,
1018 };
1019
1020 void __init sh7372_add_standard_devices(void)
1021 {
1022         sh7372_init_pm_domain(&sh7372_a4lc);
1023         sh7372_init_pm_domain(&sh7372_a4mp);
1024         sh7372_init_pm_domain(&sh7372_d4);
1025         sh7372_init_pm_domain(&sh7372_a4r);
1026         sh7372_init_pm_domain(&sh7372_a3rv);
1027         sh7372_init_pm_domain(&sh7372_a3ri);
1028         sh7372_init_pm_domain(&sh7372_a4s);
1029         sh7372_init_pm_domain(&sh7372_a3sp);
1030         sh7372_init_pm_domain(&sh7372_a3sg);
1031
1032         sh7372_pm_add_subdomain(&sh7372_a4lc, &sh7372_a3rv);
1033         sh7372_pm_add_subdomain(&sh7372_a4r, &sh7372_a4lc);
1034
1035         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sg);
1036         sh7372_pm_add_subdomain(&sh7372_a4s, &sh7372_a3sp);
1037
1038         platform_add_devices(sh7372_early_devices,
1039                             ARRAY_SIZE(sh7372_early_devices));
1040
1041         platform_add_devices(sh7372_late_devices,
1042                             ARRAY_SIZE(sh7372_late_devices));
1043
1044         sh7372_add_device_to_domain(&sh7372_a3rv, &vpu_device);
1045         sh7372_add_device_to_domain(&sh7372_a4mp, &spu0_device);
1046         sh7372_add_device_to_domain(&sh7372_a4mp, &spu1_device);
1047         sh7372_add_device_to_domain(&sh7372_a3sp, &scif0_device);
1048         sh7372_add_device_to_domain(&sh7372_a3sp, &scif1_device);
1049         sh7372_add_device_to_domain(&sh7372_a3sp, &scif2_device);
1050         sh7372_add_device_to_domain(&sh7372_a3sp, &scif3_device);
1051         sh7372_add_device_to_domain(&sh7372_a3sp, &scif4_device);
1052         sh7372_add_device_to_domain(&sh7372_a3sp, &scif5_device);
1053         sh7372_add_device_to_domain(&sh7372_a3sp, &scif6_device);
1054         sh7372_add_device_to_domain(&sh7372_a3sp, &iic1_device);
1055         sh7372_add_device_to_domain(&sh7372_a3sp, &dma0_device);
1056         sh7372_add_device_to_domain(&sh7372_a3sp, &dma1_device);
1057         sh7372_add_device_to_domain(&sh7372_a3sp, &dma2_device);
1058         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma0_device);
1059         sh7372_add_device_to_domain(&sh7372_a3sp, &usb_dma1_device);
1060         sh7372_add_device_to_domain(&sh7372_a4r, &iic0_device);
1061         sh7372_add_device_to_domain(&sh7372_a4r, &veu0_device);
1062         sh7372_add_device_to_domain(&sh7372_a4r, &veu1_device);
1063         sh7372_add_device_to_domain(&sh7372_a4r, &veu2_device);
1064         sh7372_add_device_to_domain(&sh7372_a4r, &veu3_device);
1065         sh7372_add_device_to_domain(&sh7372_a4r, &jpu_device);
1066         sh7372_add_device_to_domain(&sh7372_a4r, &tmu00_device);
1067         sh7372_add_device_to_domain(&sh7372_a4r, &tmu01_device);
1068 }
1069
1070 static void __init sh7372_earlytimer_init(void)
1071 {
1072         sh7372_clock_init();
1073         shmobile_earlytimer_init();
1074 }
1075
1076 void __init sh7372_add_early_devices(void)
1077 {
1078         early_platform_add_devices(sh7372_early_devices,
1079                                    ARRAY_SIZE(sh7372_early_devices));
1080
1081         /* setup early console here as well */
1082         shmobile_setup_console();
1083
1084         /* override timer setup with soc-specific code */
1085         shmobile_timer.init = sh7372_earlytimer_init;
1086 }