arm: tegra: fuse: replace globals with functions
[linux-3.10.git] / arch / arm / mach-shmobile / setup-r8a7790.c
1 /*
2  * r8a7790 processor support
3  *
4  * Copyright (C) 2013  Renesas Solutions Corp.
5  * Copyright (C) 2013  Magnus Damm
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19  */
20
21 #include <linux/irq.h>
22 #include <linux/irqchip.h>
23 #include <linux/kernel.h>
24 #include <linux/of_platform.h>
25 #include <linux/serial_sci.h>
26 #include <linux/platform_data/irq-renesas-irqc.h>
27 #include <mach/common.h>
28 #include <mach/irqs.h>
29 #include <mach/r8a7790.h>
30 #include <asm/mach/arch.h>
31
32 static const struct resource pfc_resources[] = {
33         DEFINE_RES_MEM(0xe6060000, 0x250),
34         DEFINE_RES_MEM(0xe6050000, 0x5050),
35 };
36
37 void __init r8a7790_pinmux_init(void)
38 {
39         platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
40                                         ARRAY_SIZE(pfc_resources));
41 }
42
43 #define SCIF_COMMON(scif_type, baseaddr, irq)                   \
44         .type           = scif_type,                            \
45         .mapbase        = baseaddr,                             \
46         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
47         .irqs           = SCIx_IRQ_MUXED(irq)
48
49 #define SCIFA_DATA(index, baseaddr, irq)                \
50 [index] = {                                             \
51         SCIF_COMMON(PORT_SCIFA, baseaddr, irq),         \
52         .scbrr_algo_id  = SCBRR_ALGO_4,                 \
53         .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,      \
54 }
55
56 #define SCIFB_DATA(index, baseaddr, irq)        \
57 [index] = {                                     \
58         SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
59         .scbrr_algo_id  = SCBRR_ALGO_4,         \
60         .scscr = SCSCR_RE | SCSCR_TE,           \
61 }
62
63 #define SCIF_DATA(index, baseaddr, irq)         \
64 [index] = {                                             \
65         SCIF_COMMON(PORT_SCIF, baseaddr, irq),          \
66         .scbrr_algo_id  = SCBRR_ALGO_2,                 \
67         .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,      \
68 }
69
70 enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
71
72 static const struct plat_sci_port scif[] = {
73         SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
74         SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
75         SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
76         SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
77         SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
78         SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
79         SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
80         SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
81 };
82
83 static inline void r8a7790_register_scif(int idx)
84 {
85         platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
86                                       sizeof(struct plat_sci_port));
87 }
88
89 static struct renesas_irqc_config irqc0_data = {
90         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
91 };
92
93 static struct resource irqc0_resources[] = {
94         DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
95         DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
96         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
97         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
98         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
99 };
100
101 #define r8a7790_register_irqc(idx)                                      \
102         platform_device_register_resndata(&platform_bus, "renesas_irqc", \
103                                           idx, irqc##idx##_resources,   \
104                                           ARRAY_SIZE(irqc##idx##_resources), \
105                                           &irqc##idx##_data,            \
106                                           sizeof(struct renesas_irqc_config))
107
108 void __init r8a7790_add_standard_devices(void)
109 {
110         r8a7790_register_scif(SCIFA0);
111         r8a7790_register_scif(SCIFA1);
112         r8a7790_register_scif(SCIFB0);
113         r8a7790_register_scif(SCIFB1);
114         r8a7790_register_scif(SCIFB2);
115         r8a7790_register_scif(SCIFA2);
116         r8a7790_register_scif(SCIF0);
117         r8a7790_register_scif(SCIF1);
118         r8a7790_register_irqc(0);
119 }
120
121 void __init r8a7790_timer_init(void)
122 {
123         void __iomem *cntcr;
124
125         /* make sure arch timer is started by setting bit 0 of CNTCT */
126         cntcr = ioremap(0xe6080000, PAGE_SIZE);
127         iowrite32(1, cntcr);
128         iounmap(cntcr);
129
130         shmobile_timer_init();
131 }
132
133 #ifdef CONFIG_USE_OF
134 void __init r8a7790_add_standard_devices_dt(void)
135 {
136         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
137 }
138
139 static const char *r8a7790_boards_compat_dt[] __initdata = {
140         "renesas,r8a7790",
141         NULL,
142 };
143
144 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
145         .init_irq       = irqchip_init,
146         .init_machine   = r8a7790_add_standard_devices_dt,
147         .init_time      = r8a7790_timer_init,
148         .dt_compat      = r8a7790_boards_compat_dt,
149 MACHINE_END
150 #endif /* CONFIG_USE_OF */