Merge tag 'cleanup-initcall' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...
[linux-3.10.git] / arch / arm / mach-shmobile / board-bonito.c
1 /*
2  * bonito board support
3  *
4  * Copyright (C) 2011 Renesas Solutions Corp.
5  * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19  *
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/i2c.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/platform_device.h>
28 #include <linux/gpio.h>
29 #include <linux/smsc911x.h>
30 #include <linux/videodev2.h>
31 #include <mach/common.h>
32 #include <asm/mach-types.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/map.h>
35 #include <asm/mach/time.h>
36 #include <asm/hardware/cache-l2x0.h>
37 #include <mach/r8a7740.h>
38 #include <mach/irqs.h>
39 #include <video/sh_mobile_lcdc.h>
40
41 /*
42  * CS   Address         device                  note
43  *----------------------------------------------------------------
44  * 0    0x0000_0000     NOR Flash (64MB)        SW12 : bit3 = OFF
45  * 2    0x0800_0000     ExtNOR (64MB)           SW12 : bit3 = OFF
46  * 4                    -
47  * 5A                   -
48  * 5B   0x1600_0000     SRAM (8MB)
49  * 6    0x1800_0000     FPGA (64K)
50  *      0x1801_0000     Ether (4KB)
51  *      0x1801_1000     USB (4KB)
52  */
53
54 /*
55  * SW12
56  *
57  *      bit1                    bit2                    bit3
58  *----------------------------------------------------------------------------
59  * ON   NOR WriteProtect        NAND WriteProtect       CS0 ExtNOR / CS2 NOR
60  * OFF  NOR Not WriteProtect    NAND Not WriteProtect   CS0 NOR    / CS2 ExtNOR
61  */
62
63 /*
64  * SCIFA5 (CN42)
65  *
66  * S38.3 = ON
67  * S39.6 = ON
68  * S43.1 = ON
69  */
70
71 /*
72  * LCDC0 (CN3/CN4/CN7)
73  *
74  * S38.1 = OFF
75  * S38.2 = OFF
76  */
77
78 /*
79  * FPGA
80  */
81 #define IRQSR0          0x0020
82 #define IRQSR1          0x0022
83 #define IRQMR0          0x0030
84 #define IRQMR1          0x0032
85 #define BUSSWMR1        0x0070
86 #define BUSSWMR2        0x0072
87 #define BUSSWMR3        0x0074
88 #define BUSSWMR4        0x0076
89
90 #define LCDCR           0x10B4
91 #define DEVRSTCR1       0x10D0
92 #define DEVRSTCR2       0x10D2
93 #define A1MDSR          0x10E0
94 #define BVERR           0x1100
95
96 /* FPGA IRQ */
97 #define FPGA_IRQ_BASE           (512)
98 #define FPGA_IRQ0               (FPGA_IRQ_BASE)
99 #define FPGA_IRQ1               (FPGA_IRQ_BASE + 16)
100 #define FPGA_ETH_IRQ            (FPGA_IRQ0 + 15)
101 static u16 bonito_fpga_read(u32 offset)
102 {
103         return __raw_readw(0xf0003000 + offset);
104 }
105
106 static void bonito_fpga_write(u32 offset, u16 val)
107 {
108         __raw_writew(val, 0xf0003000 + offset);
109 }
110
111 static void bonito_fpga_irq_disable(struct irq_data *data)
112 {
113         unsigned int irq = data->irq;
114         u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
115         int shift = irq % 16;
116
117         bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
118 }
119
120 static void bonito_fpga_irq_enable(struct irq_data *data)
121 {
122         unsigned int irq = data->irq;
123         u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
124         int shift = irq % 16;
125
126         bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
127 }
128
129 static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
130         .name           = "bonito FPGA",
131         .irq_mask       = bonito_fpga_irq_disable,
132         .irq_unmask     = bonito_fpga_irq_enable,
133 };
134
135 static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
136 {
137         u32 val =  bonito_fpga_read(IRQSR1) << 16 |
138                    bonito_fpga_read(IRQSR0);
139         u32 mask = bonito_fpga_read(IRQMR1) << 16 |
140                    bonito_fpga_read(IRQMR0);
141
142         int i;
143
144         val &= ~mask;
145
146         for (i = 0; i < 32; i++) {
147                 if (!(val & (1 << i)))
148                         continue;
149
150                 generic_handle_irq(FPGA_IRQ_BASE + i);
151         }
152 }
153
154 static void bonito_fpga_init(void)
155 {
156         int i;
157
158         bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
159         bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
160
161         /* Device reset */
162         bonito_fpga_write(DEVRSTCR1,
163                    (1 << 2));   /* Eth */
164
165         /* FPGA irq require special handling */
166         for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
167                 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
168                                               handle_level_irq, "level");
169                 set_irq_flags(i, IRQF_VALID); /* yuck */
170         }
171
172         irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
173         irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
174 }
175
176 /*
177 * PMIC settings
178 *
179 * FIXME
180 *
181 * bonito board needs some settings by pmic which use i2c access.
182 * pmic settings use device_initcall() here for use it.
183 */
184 static __u8 *pmic_settings = NULL;
185 static __u8 pmic_do_2A[] = {
186         0x1C, 0x09,
187         0x1A, 0x80,
188         0xff, 0xff,
189 };
190
191 static int __init pmic_init(void)
192 {
193         struct i2c_adapter *a = i2c_get_adapter(0);
194         struct i2c_msg msg;
195         __u8 buf[2];
196         int i, ret;
197
198         if (!pmic_settings)
199                 return 0;
200         if (!a)
201                 return 0;
202
203         msg.addr        = 0x46;
204         msg.buf         = buf;
205         msg.len         = 2;
206         msg.flags       = 0;
207
208         for (i = 0; ; i += 2) {
209                 buf[0] = pmic_settings[i + 0];
210                 buf[1] = pmic_settings[i + 1];
211
212                 if ((0xff == buf[0]) && (0xff == buf[1]))
213                         break;
214
215                 ret = i2c_transfer(a, &msg, 1);
216                 if (ret < 0) {
217                         pr_err("i2c transfer fail\n");
218                         break;
219                 }
220         }
221
222         return 0;
223 }
224 device_initcall(pmic_init);
225
226 /*
227  * LCDC0
228  */
229 static const struct fb_videomode lcdc0_mode = {
230         .name           = "WVGA Panel",
231         .xres           = 800,
232         .yres           = 480,
233         .left_margin    = 88,
234         .right_margin   = 40,
235         .hsync_len      = 128,
236         .upper_margin   = 20,
237         .lower_margin   = 5,
238         .vsync_len      = 5,
239         .sync           = 0,
240 };
241
242 static struct sh_mobile_lcdc_info lcdc0_info = {
243         .clock_source   = LCDC_CLK_BUS,
244         .ch[0] = {
245                 .chan                   = LCDC_CHAN_MAINLCD,
246                 .fourcc = V4L2_PIX_FMT_RGB565,
247                 .interface_type         = RGB24,
248                 .clock_divider          = 5,
249                 .flags                  = 0,
250                 .lcd_modes              = &lcdc0_mode,
251                 .num_modes              = 1,
252                 .panel_cfg = {
253                         .width  = 152,
254                         .height = 91,
255                 },
256         },
257 };
258
259 static struct resource lcdc0_resources[] = {
260         [0] = {
261                 .name   = "LCDC0",
262                 .start  = 0xfe940000,
263                 .end    = 0xfe943fff,
264                 .flags  = IORESOURCE_MEM,
265         },
266         [1] = {
267                 .start  = intcs_evt2irq(0x0580),
268                 .flags  = IORESOURCE_IRQ,
269         },
270 };
271
272 static struct platform_device lcdc0_device = {
273         .name           = "sh_mobile_lcdc_fb",
274         .id             = 0,
275         .resource       = lcdc0_resources,
276         .num_resources  = ARRAY_SIZE(lcdc0_resources),
277         .dev    = {
278                 .platform_data  = &lcdc0_info,
279                 .coherent_dma_mask = ~0,
280         },
281 };
282
283 /*
284  * SMSC 9221
285  */
286 static struct resource smsc_resources[] = {
287         [0] = {
288                 .start          = 0x18010000,
289                 .end            = 0x18011000 - 1,
290                 .flags          = IORESOURCE_MEM,
291         },
292         [1] = {
293                 .start          = FPGA_ETH_IRQ,
294                 .flags          = IORESOURCE_IRQ,
295         },
296 };
297
298 static struct smsc911x_platform_config smsc_platdata = {
299         .flags          = SMSC911X_USE_16BIT,
300         .phy_interface  = PHY_INTERFACE_MODE_MII,
301         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
302         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
303 };
304
305 static struct platform_device smsc_device = {
306         .name           = "smsc911x",
307         .dev  = {
308                 .platform_data = &smsc_platdata,
309         },
310         .resource       = smsc_resources,
311         .num_resources  = ARRAY_SIZE(smsc_resources),
312 };
313
314 /*
315  * core board devices
316  */
317 static struct platform_device *bonito_core_devices[] __initdata = {
318 };
319
320 /*
321  * base board devices
322  */
323 static struct platform_device *bonito_base_devices[] __initdata = {
324         &lcdc0_device,
325         &smsc_device,
326 };
327
328 /*
329  * map I/O
330  */
331 static struct map_desc bonito_io_desc[] __initdata = {
332         /*
333          * for FPGA (0x1800000-0x19ffffff)
334          * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
335          */
336         {
337                 .virtual        = 0xf0003000,
338                 .pfn            = __phys_to_pfn(0x18000000),
339                 .length         = PAGE_SIZE * 2,
340                 .type           = MT_DEVICE_NONSHARED
341         }
342 };
343
344 static void __init bonito_map_io(void)
345 {
346         r8a7740_map_io();
347         iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
348 }
349
350 /*
351  * board init
352  */
353 #define BIT_ON(sw, bit)         (sw & (1 << bit))
354 #define BIT_OFF(sw, bit)        (!(sw & (1 << bit)))
355
356 #define VCCQ1CR         0xE6058140
357 #define VCCQ1LCDCR      0xE6058186
358
359 static void __init bonito_init(void)
360 {
361         u16 val;
362
363         r8a7740_pinmux_init();
364         bonito_fpga_init();
365
366         pmic_settings = pmic_do_2A;
367
368         /*
369          * core board settings
370          */
371
372 #ifdef CONFIG_CACHE_L2X0
373         /* Early BRESP enable, Shared attribute override enable, 32K*8way */
374         l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
375 #endif
376
377         r8a7740_add_standard_devices();
378
379         platform_add_devices(bonito_core_devices,
380                              ARRAY_SIZE(bonito_core_devices));
381
382         /*
383          * base board settings
384          */
385         gpio_request(GPIO_PORT176, NULL);
386         gpio_direction_input(GPIO_PORT176);
387         if (!gpio_get_value(GPIO_PORT176)) {
388                 u16 bsw2;
389                 u16 bsw3;
390                 u16 bsw4;
391
392                 /*
393                  * FPGA
394                  */
395                 gpio_request(GPIO_FN_CS5B,              NULL);
396                 gpio_request(GPIO_FN_CS6A,              NULL);
397                 gpio_request(GPIO_FN_CS5A_PORT105,      NULL);
398                 gpio_request(GPIO_FN_IRQ10,             NULL);
399
400                 val = bonito_fpga_read(BVERR);
401                 pr_info("bonito version: cpu %02x, base %02x\n",
402                         ((val >> 8) & 0xFF),
403                         ((val >> 0) & 0xFF));
404
405                 bsw2 = bonito_fpga_read(BUSSWMR2);
406                 bsw3 = bonito_fpga_read(BUSSWMR3);
407                 bsw4 = bonito_fpga_read(BUSSWMR4);
408
409                 /*
410                  * SCIFA5 (CN42)
411                  */
412                 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
413                     BIT_OFF(bsw3, 9) && /* S39.6 = ON */
414                     BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
415                         gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
416                         gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
417                 }
418
419                 /*
420                  * LCDC0 (CN3)
421                  */
422                 if (BIT_ON(bsw2, 3) &&  /* S38.1 = OFF */
423                     BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
424                         gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
425                         gpio_request(GPIO_FN_LCD0_D0,           NULL);
426                         gpio_request(GPIO_FN_LCD0_D1,           NULL);
427                         gpio_request(GPIO_FN_LCD0_D2,           NULL);
428                         gpio_request(GPIO_FN_LCD0_D3,           NULL);
429                         gpio_request(GPIO_FN_LCD0_D4,           NULL);
430                         gpio_request(GPIO_FN_LCD0_D5,           NULL);
431                         gpio_request(GPIO_FN_LCD0_D6,           NULL);
432                         gpio_request(GPIO_FN_LCD0_D7,           NULL);
433                         gpio_request(GPIO_FN_LCD0_D8,           NULL);
434                         gpio_request(GPIO_FN_LCD0_D9,           NULL);
435                         gpio_request(GPIO_FN_LCD0_D10,          NULL);
436                         gpio_request(GPIO_FN_LCD0_D11,          NULL);
437                         gpio_request(GPIO_FN_LCD0_D12,          NULL);
438                         gpio_request(GPIO_FN_LCD0_D13,          NULL);
439                         gpio_request(GPIO_FN_LCD0_D14,          NULL);
440                         gpio_request(GPIO_FN_LCD0_D15,          NULL);
441                         gpio_request(GPIO_FN_LCD0_D16,          NULL);
442                         gpio_request(GPIO_FN_LCD0_D17,          NULL);
443                         gpio_request(GPIO_FN_LCD0_D18_PORT163,  NULL);
444                         gpio_request(GPIO_FN_LCD0_D19_PORT162,  NULL);
445                         gpio_request(GPIO_FN_LCD0_D20_PORT161,  NULL);
446                         gpio_request(GPIO_FN_LCD0_D21_PORT158,  NULL);
447                         gpio_request(GPIO_FN_LCD0_D22_PORT160,  NULL);
448                         gpio_request(GPIO_FN_LCD0_D23_PORT159,  NULL);
449                         gpio_request(GPIO_FN_LCD0_DCK,          NULL);
450                         gpio_request(GPIO_FN_LCD0_VSYN,         NULL);
451                         gpio_request(GPIO_FN_LCD0_HSYN,         NULL);
452                         gpio_request(GPIO_FN_LCD0_DISP,         NULL);
453                         gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
454
455                         gpio_request(GPIO_PORT61, NULL); /* LCDDON */
456                         gpio_direction_output(GPIO_PORT61, 1);
457
458                         /* backlight on */
459                         bonito_fpga_write(LCDCR, 1);
460
461                         /*  drivability Max */
462                         __raw_writew(0x00FF , VCCQ1LCDCR);
463                         __raw_writew(0xFFFF , VCCQ1CR);
464                 }
465
466                 platform_add_devices(bonito_base_devices,
467                                      ARRAY_SIZE(bonito_base_devices));
468         }
469 }
470
471 static void __init bonito_earlytimer_init(void)
472 {
473         u16 val;
474         u8 md_ck = 0;
475
476         /* read MD_CK value */
477         val = bonito_fpga_read(A1MDSR);
478         if (val & (1 << 10))
479                 md_ck |= MD_CK2;
480         if (val & (1 << 9))
481                 md_ck |= MD_CK1;
482         if (val & (1 << 8))
483                 md_ck |= MD_CK0;
484
485         r8a7740_clock_init(md_ck);
486         shmobile_earlytimer_init();
487 }
488
489 static void __init bonito_add_early_devices(void)
490 {
491         r8a7740_add_early_devices();
492
493         /* override timer setup with board-specific code */
494         shmobile_timer.init = bonito_earlytimer_init;
495 }
496
497 MACHINE_START(BONITO, "bonito")
498         .map_io         = bonito_map_io,
499         .init_early     = bonito_add_early_devices,
500         .init_irq       = r8a7740_init_irq,
501         .handle_irq     = shmobile_handle_irq_intc,
502         .init_machine   = bonito_init,
503         .init_late      = shmobile_init_late,
504         .timer          = &shmobile_timer,
505 MACHINE_END