ARM: __io abuse cleanup
[linux-3.10.git] / arch / arm / mach-shmobile / board-bonito.c
1 /*
2  * bonito board support
3  *
4  * Copyright (C) 2011 Renesas Solutions Corp.
5  * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19  *
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/i2c.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/platform_device.h>
28 #include <linux/gpio.h>
29 #include <linux/smsc911x.h>
30 #include <mach/common.h>
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/map.h>
34 #include <asm/mach/time.h>
35 #include <asm/hardware/cache-l2x0.h>
36 #include <mach/r8a7740.h>
37 #include <video/sh_mobile_lcdc.h>
38
39 /*
40  * CS   Address         device                  note
41  *----------------------------------------------------------------
42  * 0    0x0000_0000     NOR Flash (64MB)        SW12 : bit3 = OFF
43  * 2    0x0800_0000     ExtNOR (64MB)           SW12 : bit3 = OFF
44  * 4                    -
45  * 5A                   -
46  * 5B   0x1600_0000     SRAM (8MB)
47  * 6    0x1800_0000     FPGA (64K)
48  *      0x1801_0000     Ether (4KB)
49  *      0x1801_1000     USB (4KB)
50  */
51
52 /*
53  * SW12
54  *
55  *      bit1                    bit2                    bit3
56  *----------------------------------------------------------------------------
57  * ON   NOR WriteProtect        NAND WriteProtect       CS0 ExtNOR / CS2 NOR
58  * OFF  NOR Not WriteProtect    NAND Not WriteProtect   CS0 NOR    / CS2 ExtNOR
59  */
60
61 /*
62  * SCIFA5 (CN42)
63  *
64  * S38.3 = ON
65  * S39.6 = ON
66  * S43.1 = ON
67  */
68
69 /*
70  * LCDC0 (CN3/CN4/CN7)
71  *
72  * S38.1 = OFF
73  * S38.2 = OFF
74  */
75
76 /*
77  * FPGA
78  */
79 #define IRQSR0          0x0020
80 #define IRQSR1          0x0022
81 #define IRQMR0          0x0030
82 #define IRQMR1          0x0032
83 #define BUSSWMR1        0x0070
84 #define BUSSWMR2        0x0072
85 #define BUSSWMR3        0x0074
86 #define BUSSWMR4        0x0076
87
88 #define LCDCR           0x10B4
89 #define DEVRSTCR1       0x10D0
90 #define DEVRSTCR2       0x10D2
91 #define A1MDSR          0x10E0
92 #define BVERR           0x1100
93
94 /* FPGA IRQ */
95 #define FPGA_IRQ_BASE           (512)
96 #define FPGA_IRQ0               (FPGA_IRQ_BASE)
97 #define FPGA_IRQ1               (FPGA_IRQ_BASE + 16)
98 #define FPGA_ETH_IRQ            (FPGA_IRQ0 + 15)
99 static u16 bonito_fpga_read(u32 offset)
100 {
101         return __raw_readw(0xf0003000 + offset);
102 }
103
104 static void bonito_fpga_write(u32 offset, u16 val)
105 {
106         __raw_writew(val, 0xf0003000 + offset);
107 }
108
109 static void bonito_fpga_irq_disable(struct irq_data *data)
110 {
111         unsigned int irq = data->irq;
112         u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
113         int shift = irq % 16;
114
115         bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
116 }
117
118 static void bonito_fpga_irq_enable(struct irq_data *data)
119 {
120         unsigned int irq = data->irq;
121         u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
122         int shift = irq % 16;
123
124         bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
125 }
126
127 static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
128         .name           = "bonito FPGA",
129         .irq_mask       = bonito_fpga_irq_disable,
130         .irq_unmask     = bonito_fpga_irq_enable,
131 };
132
133 static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
134 {
135         u32 val =  bonito_fpga_read(IRQSR1) << 16 |
136                    bonito_fpga_read(IRQSR0);
137         u32 mask = bonito_fpga_read(IRQMR1) << 16 |
138                    bonito_fpga_read(IRQMR0);
139
140         int i;
141
142         val &= ~mask;
143
144         for (i = 0; i < 32; i++) {
145                 if (!(val & (1 << i)))
146                         continue;
147
148                 generic_handle_irq(FPGA_IRQ_BASE + i);
149         }
150 }
151
152 static void bonito_fpga_init(void)
153 {
154         int i;
155
156         bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
157         bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
158
159         /* Device reset */
160         bonito_fpga_write(DEVRSTCR1,
161                    (1 << 2));   /* Eth */
162
163         /* FPGA irq require special handling */
164         for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
165                 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
166                                               handle_level_irq, "level");
167                 set_irq_flags(i, IRQF_VALID); /* yuck */
168         }
169
170         irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
171         irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
172 }
173
174 /*
175 * PMIC settings
176 *
177 * FIXME
178 *
179 * bonito board needs some settings by pmic which use i2c access.
180 * pmic settings use device_initcall() here for use it.
181 */
182 static __u8 *pmic_settings = NULL;
183 static __u8 pmic_do_2A[] = {
184         0x1C, 0x09,
185         0x1A, 0x80,
186         0xff, 0xff,
187 };
188
189 static int __init pmic_init(void)
190 {
191         struct i2c_adapter *a = i2c_get_adapter(0);
192         struct i2c_msg msg;
193         __u8 buf[2];
194         int i, ret;
195
196         if (!pmic_settings)
197                 return 0;
198         if (!a)
199                 return 0;
200
201         msg.addr        = 0x46;
202         msg.buf         = buf;
203         msg.len         = 2;
204         msg.flags       = 0;
205
206         for (i = 0; ; i += 2) {
207                 buf[0] = pmic_settings[i + 0];
208                 buf[1] = pmic_settings[i + 1];
209
210                 if ((0xff == buf[0]) && (0xff == buf[1]))
211                         break;
212
213                 ret = i2c_transfer(a, &msg, 1);
214                 if (ret < 0) {
215                         pr_err("i2c transfer fail\n");
216                         break;
217                 }
218         }
219
220         return 0;
221 }
222 device_initcall(pmic_init);
223
224 /*
225  * LCDC0
226  */
227 static const struct fb_videomode lcdc0_mode = {
228         .name           = "WVGA Panel",
229         .xres           = 800,
230         .yres           = 480,
231         .left_margin    = 88,
232         .right_margin   = 40,
233         .hsync_len      = 128,
234         .upper_margin   = 20,
235         .lower_margin   = 5,
236         .vsync_len      = 5,
237         .sync           = 0,
238 };
239
240 static struct sh_mobile_lcdc_info lcdc0_info = {
241         .clock_source   = LCDC_CLK_BUS,
242         .ch[0] = {
243                 .chan                   = LCDC_CHAN_MAINLCD,
244                 .bpp                    = 16,
245                 .interface_type         = RGB24,
246                 .clock_divider          = 5,
247                 .flags                  = 0,
248                 .lcd_cfg                = &lcdc0_mode,
249                 .num_cfg                = 1,
250                 .lcd_size_cfg = {
251                         .width  = 152,
252                         .height = 91,
253                 },
254         },
255 };
256
257 static struct resource lcdc0_resources[] = {
258         [0] = {
259                 .name   = "LCDC0",
260                 .start  = 0xfe940000,
261                 .end    = 0xfe943fff,
262                 .flags  = IORESOURCE_MEM,
263         },
264         [1] = {
265                 .start  = intcs_evt2irq(0x0580),
266                 .flags  = IORESOURCE_IRQ,
267         },
268 };
269
270 static struct platform_device lcdc0_device = {
271         .name           = "sh_mobile_lcdc_fb",
272         .id             = 0,
273         .resource       = lcdc0_resources,
274         .num_resources  = ARRAY_SIZE(lcdc0_resources),
275         .dev    = {
276                 .platform_data  = &lcdc0_info,
277                 .coherent_dma_mask = ~0,
278         },
279 };
280
281 /*
282  * SMSC 9221
283  */
284 static struct resource smsc_resources[] = {
285         [0] = {
286                 .start          = 0x18010000,
287                 .end            = 0x18011000 - 1,
288                 .flags          = IORESOURCE_MEM,
289         },
290         [1] = {
291                 .start          = FPGA_ETH_IRQ,
292                 .flags          = IORESOURCE_IRQ,
293         },
294 };
295
296 static struct smsc911x_platform_config smsc_platdata = {
297         .flags          = SMSC911X_USE_16BIT,
298         .phy_interface  = PHY_INTERFACE_MODE_MII,
299         .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
300         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
301 };
302
303 static struct platform_device smsc_device = {
304         .name           = "smsc911x",
305         .dev  = {
306                 .platform_data = &smsc_platdata,
307         },
308         .resource       = smsc_resources,
309         .num_resources  = ARRAY_SIZE(smsc_resources),
310 };
311
312 /*
313  * core board devices
314  */
315 static struct platform_device *bonito_core_devices[] __initdata = {
316 };
317
318 /*
319  * base board devices
320  */
321 static struct platform_device *bonito_base_devices[] __initdata = {
322         &lcdc0_device,
323         &smsc_device,
324 };
325
326 /*
327  * map I/O
328  */
329 static struct map_desc bonito_io_desc[] __initdata = {
330          /*
331           * for CPGA/INTC/PFC
332           * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
333           */
334         {
335                 .virtual        = 0xe6000000,
336                 .pfn            = __phys_to_pfn(0xe6000000),
337                 .length         = 160 << 20,
338                 .type           = MT_DEVICE_NONSHARED
339         },
340 #ifdef CONFIG_CACHE_L2X0
341         /*
342          * for l2x0_init()
343          * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
344          */
345         {
346                 .virtual        = 0xf0002000,
347                 .pfn            = __phys_to_pfn(0xf0100000),
348                 .length         = PAGE_SIZE,
349                 .type           = MT_DEVICE_NONSHARED
350         },
351 #endif
352         /*
353          * for FPGA (0x1800000-0x19ffffff)
354          * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
355          */
356         {
357                 .virtual        = 0xf0003000,
358                 .pfn            = __phys_to_pfn(0x18000000),
359                 .length         = PAGE_SIZE * 2,
360                 .type           = MT_DEVICE_NONSHARED
361         }
362 };
363
364 static void __init bonito_map_io(void)
365 {
366         iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
367
368         /* setup early devices and console here as well */
369         r8a7740_add_early_devices();
370         shmobile_setup_console();
371 }
372
373 /*
374  * board init
375  */
376 #define BIT_ON(sw, bit)         (sw & (1 << bit))
377 #define BIT_OFF(sw, bit)        (!(sw & (1 << bit)))
378
379 #define VCCQ1CR         0xE6058140
380 #define VCCQ1LCDCR      0xE6058186
381
382 static void __init bonito_init(void)
383 {
384         u16 val;
385
386         r8a7740_pinmux_init();
387         bonito_fpga_init();
388
389         pmic_settings = pmic_do_2A;
390
391         /*
392          * core board settings
393          */
394
395 #ifdef CONFIG_CACHE_L2X0
396         /* Early BRESP enable, Shared attribute override enable, 32K*8way */
397         l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
398 #endif
399
400         r8a7740_add_standard_devices();
401
402         platform_add_devices(bonito_core_devices,
403                              ARRAY_SIZE(bonito_core_devices));
404
405         /*
406          * base board settings
407          */
408         gpio_request(GPIO_PORT176, NULL);
409         gpio_direction_input(GPIO_PORT176);
410         if (!gpio_get_value(GPIO_PORT176)) {
411                 u16 bsw2;
412                 u16 bsw3;
413                 u16 bsw4;
414
415                 /*
416                  * FPGA
417                  */
418                 gpio_request(GPIO_FN_CS5B,              NULL);
419                 gpio_request(GPIO_FN_CS6A,              NULL);
420                 gpio_request(GPIO_FN_CS5A_PORT105,      NULL);
421                 gpio_request(GPIO_FN_IRQ10,             NULL);
422
423                 val = bonito_fpga_read(BVERR);
424                 pr_info("bonito version: cpu %02x, base %02x\n",
425                         ((val >> 8) & 0xFF),
426                         ((val >> 0) & 0xFF));
427
428                 bsw2 = bonito_fpga_read(BUSSWMR2);
429                 bsw3 = bonito_fpga_read(BUSSWMR3);
430                 bsw4 = bonito_fpga_read(BUSSWMR4);
431
432                 /*
433                  * SCIFA5 (CN42)
434                  */
435                 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
436                     BIT_OFF(bsw3, 9) && /* S39.6 = ON */
437                     BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
438                         gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
439                         gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
440                 }
441
442                 /*
443                  * LCDC0 (CN3)
444                  */
445                 if (BIT_ON(bsw2, 3) &&  /* S38.1 = OFF */
446                     BIT_ON(bsw2, 2)) {  /* S38.2 = OFF */
447                         gpio_request(GPIO_FN_LCDC0_SELECT,      NULL);
448                         gpio_request(GPIO_FN_LCD0_D0,           NULL);
449                         gpio_request(GPIO_FN_LCD0_D1,           NULL);
450                         gpio_request(GPIO_FN_LCD0_D2,           NULL);
451                         gpio_request(GPIO_FN_LCD0_D3,           NULL);
452                         gpio_request(GPIO_FN_LCD0_D4,           NULL);
453                         gpio_request(GPIO_FN_LCD0_D5,           NULL);
454                         gpio_request(GPIO_FN_LCD0_D6,           NULL);
455                         gpio_request(GPIO_FN_LCD0_D7,           NULL);
456                         gpio_request(GPIO_FN_LCD0_D8,           NULL);
457                         gpio_request(GPIO_FN_LCD0_D9,           NULL);
458                         gpio_request(GPIO_FN_LCD0_D10,          NULL);
459                         gpio_request(GPIO_FN_LCD0_D11,          NULL);
460                         gpio_request(GPIO_FN_LCD0_D12,          NULL);
461                         gpio_request(GPIO_FN_LCD0_D13,          NULL);
462                         gpio_request(GPIO_FN_LCD0_D14,          NULL);
463                         gpio_request(GPIO_FN_LCD0_D15,          NULL);
464                         gpio_request(GPIO_FN_LCD0_D16,          NULL);
465                         gpio_request(GPIO_FN_LCD0_D17,          NULL);
466                         gpio_request(GPIO_FN_LCD0_D18_PORT163,  NULL);
467                         gpio_request(GPIO_FN_LCD0_D19_PORT162,  NULL);
468                         gpio_request(GPIO_FN_LCD0_D20_PORT161,  NULL);
469                         gpio_request(GPIO_FN_LCD0_D21_PORT158,  NULL);
470                         gpio_request(GPIO_FN_LCD0_D22_PORT160,  NULL);
471                         gpio_request(GPIO_FN_LCD0_D23_PORT159,  NULL);
472                         gpio_request(GPIO_FN_LCD0_DCK,          NULL);
473                         gpio_request(GPIO_FN_LCD0_VSYN,         NULL);
474                         gpio_request(GPIO_FN_LCD0_HSYN,         NULL);
475                         gpio_request(GPIO_FN_LCD0_DISP,         NULL);
476                         gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
477
478                         gpio_request(GPIO_PORT61, NULL); /* LCDDON */
479                         gpio_direction_output(GPIO_PORT61, 1);
480
481                         /* backlight on */
482                         bonito_fpga_write(LCDCR, 1);
483
484                         /*  drivability Max */
485                         __raw_writew(0x00FF , VCCQ1LCDCR);
486                         __raw_writew(0xFFFF , VCCQ1CR);
487                 }
488
489                 platform_add_devices(bonito_base_devices,
490                                      ARRAY_SIZE(bonito_base_devices));
491         }
492 }
493
494 static void __init bonito_timer_init(void)
495 {
496         u16 val;
497         u8 md_ck = 0;
498
499         /* read MD_CK value */
500         val = bonito_fpga_read(A1MDSR);
501         if (val & (1 << 10))
502                 md_ck |= MD_CK2;
503         if (val & (1 << 9))
504                 md_ck |= MD_CK1;
505         if (val & (1 << 8))
506                 md_ck |= MD_CK0;
507
508         r8a7740_clock_init(md_ck);
509         shmobile_timer.init();
510 }
511
512 struct sys_timer bonito_timer = {
513         .init   = bonito_timer_init,
514 };
515
516 MACHINE_START(BONITO, "bonito")
517         .map_io         = bonito_map_io,
518         .init_irq       = r8a7740_init_irq,
519         .handle_irq     = shmobile_handle_irq_intc,
520         .init_machine   = bonito_init,
521         .timer          = &bonito_timer,
522 MACHINE_END