Merge branch 'samsung/dt' into samsung/cleanup
[linux-3.10.git] / arch / arm / mach-s5pc100 / clock.c
1 /* linux/arch/arm/mach-s5pc100/clock.c
2  *
3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4  *              http://www.samsung.com/
5  *
6  * S5PC100 - Clock support
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/err.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20
21 #include <mach/map.h>
22
23 #include <plat/cpu-freq.h>
24 #include <mach/regs-clock.h>
25 #include <plat/clock.h>
26 #include <plat/cpu.h>
27 #include <plat/pll.h>
28 #include <plat/s5p-clock.h>
29 #include <plat/clock-clksrc.h>
30
31 #include "common.h"
32
33 static struct clk s5p_clk_otgphy = {
34         .name           = "otg_phy",
35 };
36
37 static struct clk dummy_apb_pclk = {
38         .name           = "apb_pclk",
39         .id             = -1,
40 };
41
42 static struct clk *clk_src_mout_href_list[] = {
43         [0] = &s5p_clk_27m,
44         [1] = &clk_fin_hpll,
45 };
46
47 static struct clksrc_sources clk_src_mout_href = {
48         .sources        = clk_src_mout_href_list,
49         .nr_sources     = ARRAY_SIZE(clk_src_mout_href_list),
50 };
51
52 static struct clksrc_clk clk_mout_href = {
53         .clk = {
54                 .name           = "mout_href",
55         },
56         .sources        = &clk_src_mout_href,
57         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
58 };
59
60 static struct clk *clk_src_mout_48m_list[] = {
61         [0] = &clk_xusbxti,
62         [1] = &s5p_clk_otgphy,
63 };
64
65 static struct clksrc_sources clk_src_mout_48m = {
66         .sources        = clk_src_mout_48m_list,
67         .nr_sources     = ARRAY_SIZE(clk_src_mout_48m_list),
68 };
69
70 static struct clksrc_clk clk_mout_48m = {
71         .clk = {
72                 .name           = "mout_48m",
73         },
74         .sources        = &clk_src_mout_48m,
75         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
76 };
77
78 static struct clksrc_clk clk_mout_mpll = {
79         .clk = {
80                 .name           = "mout_mpll",
81         },
82         .sources        = &clk_src_mpll,
83         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
84 };
85
86
87 static struct clksrc_clk clk_mout_apll = {
88         .clk    = {
89                 .name           = "mout_apll",
90         },
91         .sources        = &clk_src_apll,
92         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
93 };
94
95 static struct clksrc_clk clk_mout_epll = {
96         .clk    = {
97                 .name           = "mout_epll",
98         },
99         .sources        = &clk_src_epll,
100         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
101 };
102
103 static struct clk *clk_src_mout_hpll_list[] = {
104         [0] = &s5p_clk_27m,
105 };
106
107 static struct clksrc_sources clk_src_mout_hpll = {
108         .sources        = clk_src_mout_hpll_list,
109         .nr_sources     = ARRAY_SIZE(clk_src_mout_hpll_list),
110 };
111
112 static struct clksrc_clk clk_mout_hpll = {
113         .clk    = {
114                 .name           = "mout_hpll",
115         },
116         .sources        = &clk_src_mout_hpll,
117         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
118 };
119
120 static struct clksrc_clk clk_div_apll = {
121         .clk    = {
122                 .name   = "div_apll",
123                 .parent = &clk_mout_apll.clk,
124         },
125         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
126 };
127
128 static struct clksrc_clk clk_div_arm = {
129         .clk    = {
130                 .name   = "div_arm",
131                 .parent = &clk_div_apll.clk,
132         },
133         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
134 };
135
136 static struct clksrc_clk clk_div_d0_bus = {
137         .clk    = {
138                 .name   = "div_d0_bus",
139                 .parent = &clk_div_arm.clk,
140         },
141         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
142 };
143
144 static struct clksrc_clk clk_div_pclkd0 = {
145         .clk    = {
146                 .name   = "div_pclkd0",
147                 .parent = &clk_div_d0_bus.clk,
148         },
149         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
150 };
151
152 static struct clksrc_clk clk_div_secss = {
153         .clk    = {
154                 .name   = "div_secss",
155                 .parent = &clk_div_d0_bus.clk,
156         },
157         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
158 };
159
160 static struct clksrc_clk clk_div_apll2 = {
161         .clk    = {
162                 .name   = "div_apll2",
163                 .parent = &clk_mout_apll.clk,
164         },
165         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
166 };
167
168 static struct clk *clk_src_mout_am_list[] = {
169         [0] = &clk_mout_mpll.clk,
170         [1] = &clk_div_apll2.clk,
171 };
172
173 struct clksrc_sources clk_src_mout_am = {
174         .sources        = clk_src_mout_am_list,
175         .nr_sources     = ARRAY_SIZE(clk_src_mout_am_list),
176 };
177
178 static struct clksrc_clk clk_mout_am = {
179         .clk    = {
180                 .name   = "mout_am",
181         },
182         .sources = &clk_src_mout_am,
183         .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
184 };
185
186 static struct clksrc_clk clk_div_d1_bus = {
187         .clk    = {
188                 .name   = "div_d1_bus",
189                 .parent = &clk_mout_am.clk,
190         },
191         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
192 };
193
194 static struct clksrc_clk clk_div_mpll2 = {
195         .clk    = {
196                 .name   = "div_mpll2",
197                 .parent = &clk_mout_am.clk,
198         },
199         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
200 };
201
202 static struct clksrc_clk clk_div_mpll = {
203         .clk    = {
204                 .name   = "div_mpll",
205                 .parent = &clk_mout_am.clk,
206         },
207         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
208 };
209
210 static struct clk *clk_src_mout_onenand_list[] = {
211         [0] = &clk_div_d0_bus.clk,
212         [1] = &clk_div_d1_bus.clk,
213 };
214
215 struct clksrc_sources clk_src_mout_onenand = {
216         .sources        = clk_src_mout_onenand_list,
217         .nr_sources     = ARRAY_SIZE(clk_src_mout_onenand_list),
218 };
219
220 static struct clksrc_clk clk_mout_onenand = {
221         .clk    = {
222                 .name   = "mout_onenand",
223         },
224         .sources = &clk_src_mout_onenand,
225         .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
226 };
227
228 static struct clksrc_clk clk_div_onenand = {
229         .clk    = {
230                 .name   = "div_onenand",
231                 .parent = &clk_mout_onenand.clk,
232         },
233         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
234 };
235
236 static struct clksrc_clk clk_div_pclkd1 = {
237         .clk    = {
238                 .name   = "div_pclkd1",
239                 .parent = &clk_div_d1_bus.clk,
240         },
241         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
242 };
243
244 static struct clksrc_clk clk_div_cam = {
245         .clk    = {
246                 .name   = "div_cam",
247                 .parent = &clk_div_mpll2.clk,
248         },
249         .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
250 };
251
252 static struct clksrc_clk clk_div_hdmi = {
253         .clk    = {
254                 .name   = "div_hdmi",
255                 .parent = &clk_mout_hpll.clk,
256         },
257         .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
258 };
259
260 static u32 epll_div[][4] = {
261         { 32750000,     131, 3, 4 },
262         { 32768000,     131, 3, 4 },
263         { 36000000,     72,  3, 3 },
264         { 45000000,     90,  3, 3 },
265         { 45158000,     90,  3, 3 },
266         { 45158400,     90,  3, 3 },
267         { 48000000,     96,  3, 3 },
268         { 49125000,     131, 4, 3 },
269         { 49152000,     131, 4, 3 },
270         { 60000000,     120, 3, 3 },
271         { 67737600,     226, 5, 3 },
272         { 67738000,     226, 5, 3 },
273         { 73800000,     246, 5, 3 },
274         { 73728000,     246, 5, 3 },
275         { 72000000,     144, 3, 3 },
276         { 84000000,     168, 3, 3 },
277         { 96000000,     96,  3, 2 },
278         { 144000000,    144, 3, 2 },
279         { 192000000,    96,  3, 1 }
280 };
281
282 static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
283 {
284         unsigned int epll_con;
285         unsigned int i;
286
287         if (clk->rate == rate)  /* Return if nothing changed */
288                 return 0;
289
290         epll_con = __raw_readl(S5P_EPLL_CON);
291
292         epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
293
294         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
295                 if (epll_div[i][0] == rate) {
296                         epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
297                                     (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
298                                     (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
299                         break;
300                 }
301         }
302
303         if (i == ARRAY_SIZE(epll_div)) {
304                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
305                 return -EINVAL;
306         }
307
308         __raw_writel(epll_con, S5P_EPLL_CON);
309
310         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
311                         clk->rate, rate);
312
313         clk->rate = rate;
314
315         return 0;
316 }
317
318 static struct clk_ops s5pc100_epll_ops = {
319         .get_rate = s5p_epll_get_rate,
320         .set_rate = s5pc100_epll_set_rate,
321 };
322
323 static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
324 {
325         return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
326 }
327
328 static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
329 {
330         return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
331 }
332
333 static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
334 {
335         return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
336 }
337
338 static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
339 {
340         return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
341 }
342
343 static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
344 {
345         return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
346 }
347
348 static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
349 {
350         return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
351 }
352
353 static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
354 {
355         return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
356 }
357
358 static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
359 {
360         return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
361 }
362
363 static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
364 {
365         return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
366 }
367
368 static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
369 {
370         return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
371 }
372
373 static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
374 {
375         return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
376 }
377
378 /*
379  * The following clocks will be disabled during clock initialization. It is
380  * recommended to keep the following clocks disabled until the driver requests
381  * for enabling the clock.
382  */
383 static struct clk init_clocks_off[] = {
384         {
385                 .name           = "cssys",
386                 .parent         = &clk_div_d0_bus.clk,
387                 .enable         = s5pc100_d0_0_ctrl,
388                 .ctrlbit        = (1 << 6),
389         }, {
390                 .name           = "secss",
391                 .parent         = &clk_div_d0_bus.clk,
392                 .enable         = s5pc100_d0_0_ctrl,
393                 .ctrlbit        = (1 << 5),
394         }, {
395                 .name           = "g2d",
396                 .parent         = &clk_div_d0_bus.clk,
397                 .enable         = s5pc100_d0_0_ctrl,
398                 .ctrlbit        = (1 << 4),
399         }, {
400                 .name           = "mdma",
401                 .parent         = &clk_div_d0_bus.clk,
402                 .enable         = s5pc100_d0_0_ctrl,
403                 .ctrlbit        = (1 << 3),
404         }, {
405                 .name           = "cfcon",
406                 .parent         = &clk_div_d0_bus.clk,
407                 .enable         = s5pc100_d0_0_ctrl,
408                 .ctrlbit        = (1 << 2),
409         }, {
410                 .name           = "nfcon",
411                 .parent         = &clk_div_d0_bus.clk,
412                 .enable         = s5pc100_d0_1_ctrl,
413                 .ctrlbit        = (1 << 3),
414         }, {
415                 .name           = "onenandc",
416                 .parent         = &clk_div_d0_bus.clk,
417                 .enable         = s5pc100_d0_1_ctrl,
418                 .ctrlbit        = (1 << 2),
419         }, {
420                 .name           = "sdm",
421                 .parent         = &clk_div_d0_bus.clk,
422                 .enable         = s5pc100_d0_2_ctrl,
423                 .ctrlbit        = (1 << 2),
424         }, {
425                 .name           = "seckey",
426                 .parent         = &clk_div_d0_bus.clk,
427                 .enable         = s5pc100_d0_2_ctrl,
428                 .ctrlbit        = (1 << 1),
429         }, {
430                 .name           = "modemif",
431                 .parent         = &clk_div_d1_bus.clk,
432                 .enable         = s5pc100_d1_0_ctrl,
433                 .ctrlbit        = (1 << 4),
434         }, {
435                 .name           = "otg",
436                 .parent         = &clk_div_d1_bus.clk,
437                 .enable         = s5pc100_d1_0_ctrl,
438                 .ctrlbit        = (1 << 3),
439         }, {
440                 .name           = "usbhost",
441                 .parent         = &clk_div_d1_bus.clk,
442                 .enable         = s5pc100_d1_0_ctrl,
443                 .ctrlbit        = (1 << 2),
444         }, {
445                 .name           = "dma",
446                 .devname        = "dma-pl330.1",
447                 .parent         = &clk_div_d1_bus.clk,
448                 .enable         = s5pc100_d1_0_ctrl,
449                 .ctrlbit        = (1 << 1),
450         }, {
451                 .name           = "dma",
452                 .devname        = "dma-pl330.0",
453                 .parent         = &clk_div_d1_bus.clk,
454                 .enable         = s5pc100_d1_0_ctrl,
455                 .ctrlbit        = (1 << 0),
456         }, {
457                 .name           = "lcd",
458                 .parent         = &clk_div_d1_bus.clk,
459                 .enable         = s5pc100_d1_1_ctrl,
460                 .ctrlbit        = (1 << 0),
461         }, {
462                 .name           = "rotator",
463                 .parent         = &clk_div_d1_bus.clk,
464                 .enable         = s5pc100_d1_1_ctrl,
465                 .ctrlbit        = (1 << 1),
466         }, {
467                 .name           = "fimc",
468                 .devname        = "s5p-fimc.0",
469                 .parent         = &clk_div_d1_bus.clk,
470                 .enable         = s5pc100_d1_1_ctrl,
471                 .ctrlbit        = (1 << 2),
472         }, {
473                 .name           = "fimc",
474                 .devname        = "s5p-fimc.1",
475                 .parent         = &clk_div_d1_bus.clk,
476                 .enable         = s5pc100_d1_1_ctrl,
477                 .ctrlbit        = (1 << 3),
478         }, {
479                 .name           = "fimc",
480                 .devname        = "s5p-fimc.2",
481                 .enable         = s5pc100_d1_1_ctrl,
482                 .ctrlbit        = (1 << 4),
483         }, {
484                 .name           = "jpeg",
485                 .parent         = &clk_div_d1_bus.clk,
486                 .enable         = s5pc100_d1_1_ctrl,
487                 .ctrlbit        = (1 << 5),
488         }, {
489                 .name           = "mipi-dsim",
490                 .parent         = &clk_div_d1_bus.clk,
491                 .enable         = s5pc100_d1_1_ctrl,
492                 .ctrlbit        = (1 << 6),
493         }, {
494                 .name           = "mipi-csis",
495                 .parent         = &clk_div_d1_bus.clk,
496                 .enable         = s5pc100_d1_1_ctrl,
497                 .ctrlbit        = (1 << 7),
498         }, {
499                 .name           = "g3d",
500                 .parent         = &clk_div_d1_bus.clk,
501                 .enable         = s5pc100_d1_0_ctrl,
502                 .ctrlbit        = (1 << 8),
503         }, {
504                 .name           = "tv",
505                 .parent         = &clk_div_d1_bus.clk,
506                 .enable         = s5pc100_d1_2_ctrl,
507                 .ctrlbit        = (1 << 0),
508         }, {
509                 .name           = "vp",
510                 .parent         = &clk_div_d1_bus.clk,
511                 .enable         = s5pc100_d1_2_ctrl,
512                 .ctrlbit        = (1 << 1),
513         }, {
514                 .name           = "mixer",
515                 .parent         = &clk_div_d1_bus.clk,
516                 .enable         = s5pc100_d1_2_ctrl,
517                 .ctrlbit        = (1 << 2),
518         }, {
519                 .name           = "hdmi",
520                 .parent         = &clk_div_d1_bus.clk,
521                 .enable         = s5pc100_d1_2_ctrl,
522                 .ctrlbit        = (1 << 3),
523         }, {
524                 .name           = "mfc",
525                 .parent         = &clk_div_d1_bus.clk,
526                 .enable         = s5pc100_d1_2_ctrl,
527                 .ctrlbit        = (1 << 4),
528         }, {
529                 .name           = "apc",
530                 .parent         = &clk_div_d1_bus.clk,
531                 .enable         = s5pc100_d1_3_ctrl,
532                 .ctrlbit        = (1 << 2),
533         }, {
534                 .name           = "iec",
535                 .parent         = &clk_div_d1_bus.clk,
536                 .enable         = s5pc100_d1_3_ctrl,
537                 .ctrlbit        = (1 << 3),
538         }, {
539                 .name           = "systimer",
540                 .parent         = &clk_div_d1_bus.clk,
541                 .enable         = s5pc100_d1_3_ctrl,
542                 .ctrlbit        = (1 << 7),
543         }, {
544                 .name           = "watchdog",
545                 .parent         = &clk_div_d1_bus.clk,
546                 .enable         = s5pc100_d1_3_ctrl,
547                 .ctrlbit        = (1 << 8),
548         }, {
549                 .name           = "rtc",
550                 .parent         = &clk_div_d1_bus.clk,
551                 .enable         = s5pc100_d1_3_ctrl,
552                 .ctrlbit        = (1 << 9),
553         }, {
554                 .name           = "i2c",
555                 .devname        = "s3c2440-i2c.0",
556                 .parent         = &clk_div_d1_bus.clk,
557                 .enable         = s5pc100_d1_4_ctrl,
558                 .ctrlbit        = (1 << 4),
559         }, {
560                 .name           = "i2c",
561                 .devname        = "s3c2440-i2c.1",
562                 .parent         = &clk_div_d1_bus.clk,
563                 .enable         = s5pc100_d1_4_ctrl,
564                 .ctrlbit        = (1 << 5),
565         }, {
566                 .name           = "spi",
567                 .devname        = "s3c64xx-spi.0",
568                 .parent         = &clk_div_d1_bus.clk,
569                 .enable         = s5pc100_d1_4_ctrl,
570                 .ctrlbit        = (1 << 6),
571         }, {
572                 .name           = "spi",
573                 .devname        = "s3c64xx-spi.1",
574                 .parent         = &clk_div_d1_bus.clk,
575                 .enable         = s5pc100_d1_4_ctrl,
576                 .ctrlbit        = (1 << 7),
577         }, {
578                 .name           = "spi",
579                 .devname        = "s3c64xx-spi.2",
580                 .parent         = &clk_div_d1_bus.clk,
581                 .enable         = s5pc100_d1_4_ctrl,
582                 .ctrlbit        = (1 << 8),
583         }, {
584                 .name           = "irda",
585                 .parent         = &clk_div_d1_bus.clk,
586                 .enable         = s5pc100_d1_4_ctrl,
587                 .ctrlbit        = (1 << 9),
588         }, {
589                 .name           = "ccan",
590                 .parent         = &clk_div_d1_bus.clk,
591                 .enable         = s5pc100_d1_4_ctrl,
592                 .ctrlbit        = (1 << 10),
593         }, {
594                 .name           = "ccan",
595                 .parent         = &clk_div_d1_bus.clk,
596                 .enable         = s5pc100_d1_4_ctrl,
597                 .ctrlbit        = (1 << 11),
598         }, {
599                 .name           = "hsitx",
600                 .parent         = &clk_div_d1_bus.clk,
601                 .enable         = s5pc100_d1_4_ctrl,
602                 .ctrlbit        = (1 << 12),
603         }, {
604                 .name           = "hsirx",
605                 .parent         = &clk_div_d1_bus.clk,
606                 .enable         = s5pc100_d1_4_ctrl,
607                 .ctrlbit        = (1 << 13),
608         }, {
609                 .name           = "iis",
610                 .devname        = "samsung-i2s.0",
611                 .parent         = &clk_div_pclkd1.clk,
612                 .enable         = s5pc100_d1_5_ctrl,
613                 .ctrlbit        = (1 << 0),
614         }, {
615                 .name           = "iis",
616                 .devname        = "samsung-i2s.1",
617                 .parent         = &clk_div_pclkd1.clk,
618                 .enable         = s5pc100_d1_5_ctrl,
619                 .ctrlbit        = (1 << 1),
620         }, {
621                 .name           = "iis",
622                 .devname        = "samsung-i2s.2",
623                 .parent         = &clk_div_pclkd1.clk,
624                 .enable         = s5pc100_d1_5_ctrl,
625                 .ctrlbit        = (1 << 2),
626         }, {
627                 .name           = "ac97",
628                 .parent         = &clk_div_pclkd1.clk,
629                 .enable         = s5pc100_d1_5_ctrl,
630                 .ctrlbit        = (1 << 3),
631         }, {
632                 .name           = "pcm",
633                 .devname        = "samsung-pcm.0",
634                 .parent         = &clk_div_pclkd1.clk,
635                 .enable         = s5pc100_d1_5_ctrl,
636                 .ctrlbit        = (1 << 4),
637         }, {
638                 .name           = "pcm",
639                 .devname        = "samsung-pcm.1",
640                 .parent         = &clk_div_pclkd1.clk,
641                 .enable         = s5pc100_d1_5_ctrl,
642                 .ctrlbit        = (1 << 5),
643         }, {
644                 .name           = "spdif",
645                 .parent         = &clk_div_pclkd1.clk,
646                 .enable         = s5pc100_d1_5_ctrl,
647                 .ctrlbit        = (1 << 6),
648         }, {
649                 .name           = "adc",
650                 .parent         = &clk_div_pclkd1.clk,
651                 .enable         = s5pc100_d1_5_ctrl,
652                 .ctrlbit        = (1 << 7),
653         }, {
654                 .name           = "keypad",
655                 .parent         = &clk_div_pclkd1.clk,
656                 .enable         = s5pc100_d1_5_ctrl,
657                 .ctrlbit        = (1 << 8),
658         }, {
659                 .name           = "mmc_48m",
660                 .devname        = "s3c-sdhci.0",
661                 .parent         = &clk_mout_48m.clk,
662                 .enable         = s5pc100_sclk0_ctrl,
663                 .ctrlbit        = (1 << 15),
664         }, {
665                 .name           = "mmc_48m",
666                 .devname        = "s3c-sdhci.1",
667                 .parent         = &clk_mout_48m.clk,
668                 .enable         = s5pc100_sclk0_ctrl,
669                 .ctrlbit        = (1 << 16),
670         }, {
671                 .name           = "mmc_48m",
672                 .devname        = "s3c-sdhci.2",
673                 .parent         = &clk_mout_48m.clk,
674                 .enable         = s5pc100_sclk0_ctrl,
675                 .ctrlbit        = (1 << 17),
676         },
677 };
678
679 static struct clk clk_hsmmc2 = {
680         .name           = "hsmmc",
681         .devname        = "s3c-sdhci.2",
682         .parent         = &clk_div_d1_bus.clk,
683         .enable         = s5pc100_d1_0_ctrl,
684         .ctrlbit        = (1 << 7),
685 };
686
687 static struct clk clk_hsmmc1 = {
688         .name           = "hsmmc",
689         .devname        = "s3c-sdhci.1",
690         .parent         = &clk_div_d1_bus.clk,
691         .enable         = s5pc100_d1_0_ctrl,
692         .ctrlbit        = (1 << 6),
693 };
694
695 static struct clk clk_hsmmc0 = {
696         .name           = "hsmmc",
697         .devname        = "s3c-sdhci.0",
698         .parent         = &clk_div_d1_bus.clk,
699         .enable         = s5pc100_d1_0_ctrl,
700         .ctrlbit        = (1 << 5),
701 };
702
703 static struct clk clk_48m_spi0 = {
704         .name           = "spi_48m",
705         .devname        = "s3c64xx-spi.0",
706         .parent         = &clk_mout_48m.clk,
707         .enable         = s5pc100_sclk0_ctrl,
708         .ctrlbit        = (1 << 7),
709 };
710
711 static struct clk clk_48m_spi1 = {
712         .name           = "spi_48m",
713         .devname        = "s3c64xx-spi.1",
714         .parent         = &clk_mout_48m.clk,
715         .enable         = s5pc100_sclk0_ctrl,
716         .ctrlbit        = (1 << 8),
717 };
718
719 static struct clk clk_48m_spi2 = {
720         .name           = "spi_48m",
721         .devname        = "s3c64xx-spi.2",
722         .parent         = &clk_mout_48m.clk,
723         .enable         = s5pc100_sclk0_ctrl,
724         .ctrlbit        = (1 << 9),
725 };
726
727 static struct clk clk_vclk54m = {
728         .name           = "vclk_54m",
729         .rate           = 54000000,
730 };
731
732 static struct clk clk_i2scdclk0 = {
733         .name           = "i2s_cdclk0",
734 };
735
736 static struct clk clk_i2scdclk1 = {
737         .name           = "i2s_cdclk1",
738 };
739
740 static struct clk clk_i2scdclk2 = {
741         .name           = "i2s_cdclk2",
742 };
743
744 static struct clk clk_pcmcdclk0 = {
745         .name           = "pcm_cdclk0",
746 };
747
748 static struct clk clk_pcmcdclk1 = {
749         .name           = "pcm_cdclk1",
750 };
751
752 static struct clk *clk_src_group1_list[] = {
753         [0] = &clk_mout_epll.clk,
754         [1] = &clk_div_mpll2.clk,
755         [2] = &clk_fin_epll,
756         [3] = &clk_mout_hpll.clk,
757 };
758
759 struct clksrc_sources clk_src_group1 = {
760         .sources        = clk_src_group1_list,
761         .nr_sources     = ARRAY_SIZE(clk_src_group1_list),
762 };
763
764 static struct clk *clk_src_group2_list[] = {
765         [0] = &clk_mout_epll.clk,
766         [1] = &clk_div_mpll.clk,
767 };
768
769 struct clksrc_sources clk_src_group2 = {
770         .sources        = clk_src_group2_list,
771         .nr_sources     = ARRAY_SIZE(clk_src_group2_list),
772 };
773
774 static struct clk *clk_src_group3_list[] = {
775         [0] = &clk_mout_epll.clk,
776         [1] = &clk_div_mpll.clk,
777         [2] = &clk_fin_epll,
778         [3] = &clk_i2scdclk0,
779         [4] = &clk_pcmcdclk0,
780         [5] = &clk_mout_hpll.clk,
781 };
782
783 struct clksrc_sources clk_src_group3 = {
784         .sources        = clk_src_group3_list,
785         .nr_sources     = ARRAY_SIZE(clk_src_group3_list),
786 };
787
788 static struct clksrc_clk clk_sclk_audio0 = {
789         .clk    = {
790                 .name           = "sclk_audio",
791                 .devname        = "samsung-pcm.0",
792                 .ctrlbit        = (1 << 8),
793                 .enable         = s5pc100_sclk1_ctrl,
794         },
795         .sources = &clk_src_group3,
796         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
797         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
798 };
799
800 static struct clk *clk_src_group4_list[] = {
801         [0] = &clk_mout_epll.clk,
802         [1] = &clk_div_mpll.clk,
803         [2] = &clk_fin_epll,
804         [3] = &clk_i2scdclk1,
805         [4] = &clk_pcmcdclk1,
806         [5] = &clk_mout_hpll.clk,
807 };
808
809 struct clksrc_sources clk_src_group4 = {
810         .sources        = clk_src_group4_list,
811         .nr_sources     = ARRAY_SIZE(clk_src_group4_list),
812 };
813
814 static struct clksrc_clk clk_sclk_audio1 = {
815         .clk    = {
816                 .name           = "sclk_audio",
817                 .devname        = "samsung-pcm.1",
818                 .ctrlbit        = (1 << 9),
819                 .enable         = s5pc100_sclk1_ctrl,
820         },
821         .sources = &clk_src_group4,
822         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
823         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
824 };
825
826 static struct clk *clk_src_group5_list[] = {
827         [0] = &clk_mout_epll.clk,
828         [1] = &clk_div_mpll.clk,
829         [2] = &clk_fin_epll,
830         [3] = &clk_i2scdclk2,
831         [4] = &clk_mout_hpll.clk,
832 };
833
834 struct clksrc_sources clk_src_group5 = {
835         .sources        = clk_src_group5_list,
836         .nr_sources     = ARRAY_SIZE(clk_src_group5_list),
837 };
838
839 static struct clksrc_clk clk_sclk_audio2 = {
840         .clk    = {
841                 .name           = "sclk_audio",
842                 .devname        = "samsung-pcm.2",
843                 .ctrlbit        = (1 << 10),
844                 .enable         = s5pc100_sclk1_ctrl,
845         },
846         .sources = &clk_src_group5,
847         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
848         .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
849 };
850
851 static struct clk *clk_src_group6_list[] = {
852         [0] = &s5p_clk_27m,
853         [1] = &clk_vclk54m,
854         [2] = &clk_div_hdmi.clk,
855 };
856
857 struct clksrc_sources clk_src_group6 = {
858         .sources        = clk_src_group6_list,
859         .nr_sources     = ARRAY_SIZE(clk_src_group6_list),
860 };
861
862 static struct clk *clk_src_group7_list[] = {
863         [0] = &clk_mout_epll.clk,
864         [1] = &clk_div_mpll.clk,
865         [2] = &clk_mout_hpll.clk,
866         [3] = &clk_vclk54m,
867 };
868
869 struct clksrc_sources clk_src_group7 = {
870         .sources        = clk_src_group7_list,
871         .nr_sources     = ARRAY_SIZE(clk_src_group7_list),
872 };
873
874 static struct clk *clk_src_mmc0_list[] = {
875         [0] = &clk_mout_epll.clk,
876         [1] = &clk_div_mpll.clk,
877         [2] = &clk_fin_epll,
878 };
879
880 struct clksrc_sources clk_src_mmc0 = {
881         .sources        = clk_src_mmc0_list,
882         .nr_sources     = ARRAY_SIZE(clk_src_mmc0_list),
883 };
884
885 static struct clk *clk_src_mmc12_list[] = {
886         [0] = &clk_mout_epll.clk,
887         [1] = &clk_div_mpll.clk,
888         [2] = &clk_fin_epll,
889         [3] = &clk_mout_hpll.clk,
890 };
891
892 struct clksrc_sources clk_src_mmc12 = {
893         .sources        = clk_src_mmc12_list,
894         .nr_sources     = ARRAY_SIZE(clk_src_mmc12_list),
895 };
896
897 static struct clk *clk_src_irda_usb_list[] = {
898         [0] = &clk_mout_epll.clk,
899         [1] = &clk_div_mpll.clk,
900         [2] = &clk_fin_epll,
901         [3] = &clk_mout_hpll.clk,
902 };
903
904 struct clksrc_sources clk_src_irda_usb = {
905         .sources        = clk_src_irda_usb_list,
906         .nr_sources     = ARRAY_SIZE(clk_src_irda_usb_list),
907 };
908
909 static struct clk *clk_src_pwi_list[] = {
910         [0] = &clk_fin_epll,
911         [1] = &clk_mout_epll.clk,
912         [2] = &clk_div_mpll.clk,
913 };
914
915 struct clksrc_sources clk_src_pwi = {
916         .sources        = clk_src_pwi_list,
917         .nr_sources     = ARRAY_SIZE(clk_src_pwi_list),
918 };
919
920 static struct clk *clk_sclk_spdif_list[] = {
921         [0] = &clk_sclk_audio0.clk,
922         [1] = &clk_sclk_audio1.clk,
923         [2] = &clk_sclk_audio2.clk,
924 };
925
926 struct clksrc_sources clk_src_sclk_spdif = {
927         .sources        = clk_sclk_spdif_list,
928         .nr_sources     = ARRAY_SIZE(clk_sclk_spdif_list),
929 };
930
931 static struct clksrc_clk clk_sclk_spdif = {
932         .clk    = {
933                 .name           = "sclk_spdif",
934                 .ctrlbit        = (1 << 11),
935                 .enable         = s5pc100_sclk1_ctrl,
936                 .ops            = &s5p_sclk_spdif_ops,
937         },
938         .sources = &clk_src_sclk_spdif,
939         .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
940 };
941
942 static struct clksrc_clk clksrcs[] = {
943         {
944                 .clk    = {
945                         .name           = "sclk_mixer",
946                         .ctrlbit        = (1 << 6),
947                         .enable         = s5pc100_sclk0_ctrl,
948
949                 },
950                 .sources = &clk_src_group6,
951                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
952         }, {
953                 .clk    = {
954                         .name           = "sclk_lcd",
955                         .ctrlbit        = (1 << 0),
956                         .enable         = s5pc100_sclk1_ctrl,
957
958                 },
959                 .sources = &clk_src_group7,
960                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
961                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
962         }, {
963                 .clk    = {
964                         .name           = "sclk_fimc",
965                         .devname        = "s5p-fimc.0",
966                         .ctrlbit        = (1 << 1),
967                         .enable         = s5pc100_sclk1_ctrl,
968
969                 },
970                 .sources = &clk_src_group7,
971                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
972                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
973         }, {
974                 .clk    = {
975                         .name           = "sclk_fimc",
976                         .devname        = "s5p-fimc.1",
977                         .ctrlbit        = (1 << 2),
978                         .enable         = s5pc100_sclk1_ctrl,
979
980                 },
981                 .sources = &clk_src_group7,
982                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
983                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
984         }, {
985                 .clk    = {
986                         .name           = "sclk_fimc",
987                         .devname        = "s5p-fimc.2",
988                         .ctrlbit        = (1 << 3),
989                         .enable         = s5pc100_sclk1_ctrl,
990
991                 },
992                 .sources = &clk_src_group7,
993                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
994                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
995         }, {
996                 .clk    = {
997                         .name           = "sclk_irda",
998                         .ctrlbit        = (1 << 10),
999                         .enable         = s5pc100_sclk0_ctrl,
1000
1001                 },
1002                 .sources = &clk_src_irda_usb,
1003                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1004                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1005         }, {
1006                 .clk    = {
1007                         .name           = "sclk_irda",
1008                         .ctrlbit        = (1 << 10),
1009                         .enable         = s5pc100_sclk0_ctrl,
1010
1011                 },
1012                 .sources = &clk_src_mmc12,
1013                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1014                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1015         }, {
1016                 .clk    = {
1017                         .name           = "sclk_pwi",
1018                         .ctrlbit        = (1 << 1),
1019                         .enable         = s5pc100_sclk0_ctrl,
1020
1021                 },
1022                 .sources = &clk_src_pwi,
1023                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1024                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1025         }, {
1026                 .clk    = {
1027                         .name           = "sclk_uhost",
1028                         .ctrlbit        = (1 << 11),
1029                         .enable         = s5pc100_sclk0_ctrl,
1030
1031                 },
1032                 .sources = &clk_src_irda_usb,
1033                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1034                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1035         },
1036 };
1037
1038 static struct clksrc_clk clk_sclk_uart = {
1039         .clk    = {
1040                 .name           = "uclk1",
1041                 .ctrlbit        = (1 << 3),
1042                 .enable         = s5pc100_sclk0_ctrl,
1043         },
1044         .sources = &clk_src_group2,
1045         .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1046         .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1047 };
1048
1049 static struct clksrc_clk clk_sclk_mmc0 = {
1050         .clk    = {
1051                 .name           = "sclk_mmc",
1052                 .devname        = "s3c-sdhci.0",
1053                 .ctrlbit        = (1 << 12),
1054                 .enable         = s5pc100_sclk1_ctrl,
1055         },
1056         .sources = &clk_src_mmc0,
1057         .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1058         .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1059 };
1060
1061 static struct clksrc_clk clk_sclk_mmc1 = {
1062         .clk    = {
1063                 .name           = "sclk_mmc",
1064                 .devname        = "s3c-sdhci.1",
1065                 .ctrlbit        = (1 << 13),
1066                 .enable         = s5pc100_sclk1_ctrl,
1067         },
1068         .sources = &clk_src_mmc12,
1069         .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1070         .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1071 };
1072
1073 static struct clksrc_clk clk_sclk_mmc2 = {
1074         .clk    = {
1075                 .name           = "sclk_mmc",
1076                 .devname        = "s3c-sdhci.2",
1077                 .ctrlbit        = (1 << 14),
1078                 .enable         = s5pc100_sclk1_ctrl,
1079         },
1080         .sources = &clk_src_mmc12,
1081         .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1082         .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1083 };
1084
1085 static struct clksrc_clk clk_sclk_spi0 = {
1086         .clk    = {
1087                 .name           = "sclk_spi",
1088                 .devname        = "s3c64xx-spi.0",
1089                 .ctrlbit        = (1 << 4),
1090                 .enable         = s5pc100_sclk0_ctrl,
1091         },
1092         .sources = &clk_src_group1,
1093         .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1094         .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1095 };
1096
1097 static struct clksrc_clk clk_sclk_spi1 = {
1098         .clk    = {
1099                 .name           = "sclk_spi",
1100                 .devname        = "s3c64xx-spi.1",
1101                 .ctrlbit        = (1 << 5),
1102                 .enable         = s5pc100_sclk0_ctrl,
1103         },
1104         .sources = &clk_src_group1,
1105         .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1106         .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1107 };
1108
1109 static struct clksrc_clk clk_sclk_spi2 = {
1110         .clk    = {
1111                 .name           = "sclk_spi",
1112                 .devname        = "s3c64xx-spi.2",
1113                 .ctrlbit        = (1 << 6),
1114                 .enable         = s5pc100_sclk0_ctrl,
1115         },
1116         .sources = &clk_src_group1,
1117         .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1118         .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1119 };
1120
1121 /* Clock initialisation code */
1122 static struct clksrc_clk *sysclks[] = {
1123         &clk_mout_apll,
1124         &clk_mout_epll,
1125         &clk_mout_mpll,
1126         &clk_mout_hpll,
1127         &clk_mout_href,
1128         &clk_mout_48m,
1129         &clk_div_apll,
1130         &clk_div_arm,
1131         &clk_div_d0_bus,
1132         &clk_div_pclkd0,
1133         &clk_div_secss,
1134         &clk_div_apll2,
1135         &clk_mout_am,
1136         &clk_div_d1_bus,
1137         &clk_div_mpll2,
1138         &clk_div_mpll,
1139         &clk_mout_onenand,
1140         &clk_div_onenand,
1141         &clk_div_pclkd1,
1142         &clk_div_cam,
1143         &clk_div_hdmi,
1144         &clk_sclk_audio0,
1145         &clk_sclk_audio1,
1146         &clk_sclk_audio2,
1147         &clk_sclk_spdif,
1148 };
1149
1150 static struct clk *clk_cdev[] = {
1151         &clk_hsmmc0,
1152         &clk_hsmmc1,
1153         &clk_hsmmc2,
1154         &clk_48m_spi0,
1155         &clk_48m_spi1,
1156         &clk_48m_spi2,
1157 };
1158
1159 static struct clksrc_clk *clksrc_cdev[] = {
1160         &clk_sclk_uart,
1161         &clk_sclk_mmc0,
1162         &clk_sclk_mmc1,
1163         &clk_sclk_mmc2,
1164         &clk_sclk_spi0,
1165         &clk_sclk_spi1,
1166         &clk_sclk_spi2,
1167 };
1168
1169 void __init_or_cpufreq s5pc100_setup_clocks(void)
1170 {
1171         unsigned long xtal;
1172         unsigned long arm;
1173         unsigned long hclkd0;
1174         unsigned long hclkd1;
1175         unsigned long pclkd0;
1176         unsigned long pclkd1;
1177         unsigned long apll;
1178         unsigned long mpll;
1179         unsigned long epll;
1180         unsigned long hpll;
1181         unsigned int ptr;
1182
1183         /* Set S5PC100 functions for clk_fout_epll */
1184         clk_fout_epll.enable = s5p_epll_enable;
1185         clk_fout_epll.ops = &s5pc100_epll_ops;
1186
1187         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1188
1189         xtal = clk_get_rate(&clk_xtal);
1190
1191         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1192
1193         apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1194         mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1195         epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1196         hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1197
1198         printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1199                         print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1200
1201         clk_fout_apll.rate = apll;
1202         clk_fout_mpll.rate = mpll;
1203         clk_fout_epll.rate = epll;
1204         clk_mout_hpll.clk.rate = hpll;
1205
1206         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1207                 s3c_set_clksrc(&clksrcs[ptr], true);
1208
1209         arm = clk_get_rate(&clk_div_arm.clk);
1210         hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1211         pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1212         hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1213         pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1214
1215         printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1216                         print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1217
1218         clk_f.rate = arm;
1219         clk_h.rate = hclkd1;
1220         clk_p.rate = pclkd1;
1221 }
1222
1223 /*
1224  * The following clocks will be enabled during clock initialization.
1225  */
1226 static struct clk init_clocks[] = {
1227         {
1228                 .name           = "tzic",
1229                 .parent         = &clk_div_d0_bus.clk,
1230                 .enable         = s5pc100_d0_0_ctrl,
1231                 .ctrlbit        = (1 << 1),
1232         }, {
1233                 .name           = "intc",
1234                 .parent         = &clk_div_d0_bus.clk,
1235                 .enable         = s5pc100_d0_0_ctrl,
1236                 .ctrlbit        = (1 << 0),
1237         }, {
1238                 .name           = "ebi",
1239                 .parent         = &clk_div_d0_bus.clk,
1240                 .enable         = s5pc100_d0_1_ctrl,
1241                 .ctrlbit        = (1 << 5),
1242         }, {
1243                 .name           = "intmem",
1244                 .parent         = &clk_div_d0_bus.clk,
1245                 .enable         = s5pc100_d0_1_ctrl,
1246                 .ctrlbit        = (1 << 4),
1247         }, {
1248                 .name           = "sromc",
1249                 .parent         = &clk_div_d0_bus.clk,
1250                 .enable         = s5pc100_d0_1_ctrl,
1251                 .ctrlbit        = (1 << 1),
1252         }, {
1253                 .name           = "dmc",
1254                 .parent         = &clk_div_d0_bus.clk,
1255                 .enable         = s5pc100_d0_1_ctrl,
1256                 .ctrlbit        = (1 << 0),
1257         }, {
1258                 .name           = "chipid",
1259                 .parent         = &clk_div_d0_bus.clk,
1260                 .enable         = s5pc100_d0_1_ctrl,
1261                 .ctrlbit        = (1 << 0),
1262         }, {
1263                 .name           = "gpio",
1264                 .parent         = &clk_div_d1_bus.clk,
1265                 .enable         = s5pc100_d1_3_ctrl,
1266                 .ctrlbit        = (1 << 1),
1267         }, {
1268                 .name           = "uart",
1269                 .devname        = "s3c6400-uart.0",
1270                 .parent         = &clk_div_d1_bus.clk,
1271                 .enable         = s5pc100_d1_4_ctrl,
1272                 .ctrlbit        = (1 << 0),
1273         }, {
1274                 .name           = "uart",
1275                 .devname        = "s3c6400-uart.1",
1276                 .parent         = &clk_div_d1_bus.clk,
1277                 .enable         = s5pc100_d1_4_ctrl,
1278                 .ctrlbit        = (1 << 1),
1279         }, {
1280                 .name           = "uart",
1281                 .devname        = "s3c6400-uart.2",
1282                 .parent         = &clk_div_d1_bus.clk,
1283                 .enable         = s5pc100_d1_4_ctrl,
1284                 .ctrlbit        = (1 << 2),
1285         }, {
1286                 .name           = "uart",
1287                 .devname        = "s3c6400-uart.3",
1288                 .parent         = &clk_div_d1_bus.clk,
1289                 .enable         = s5pc100_d1_4_ctrl,
1290                 .ctrlbit        = (1 << 3),
1291         }, {
1292                 .name           = "timers",
1293                 .parent         = &clk_div_d1_bus.clk,
1294                 .enable         = s5pc100_d1_3_ctrl,
1295                 .ctrlbit        = (1 << 6),
1296         },
1297 };
1298
1299 static struct clk *clks[] __initdata = {
1300         &clk_ext,
1301         &clk_i2scdclk0,
1302         &clk_i2scdclk1,
1303         &clk_i2scdclk2,
1304         &clk_pcmcdclk0,
1305         &clk_pcmcdclk1,
1306 };
1307
1308 static struct clk_lookup s5pc100_clk_lookup[] = {
1309         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1310         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1311         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1312         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1313         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1314         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1315         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1316         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1317         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1318         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
1319         CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1320         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
1321         CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1322         CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
1323         CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1324 };
1325
1326 void __init s5pc100_register_clocks(void)
1327 {
1328         int ptr;
1329
1330         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1331
1332         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1333                 s3c_register_clksrc(sysclks[ptr], 1);
1334
1335         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1336         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1337         for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1338                 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1339
1340         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1341         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1342         clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1343
1344         s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1345         for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1346                 s3c_disable_clocks(clk_cdev[ptr], 1);
1347
1348         s3c24xx_register_clock(&dummy_apb_pclk);
1349
1350         s3c_pwmclk_init();
1351 }