2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Common Codes for S5P64X0 machines
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/interrupt.h>
15 #include <linux/list.h>
16 #include <linux/timer.h>
17 #include <linux/init.h>
18 #include <linux/clk.h>
20 #include <linux/sysdev.h>
21 #include <linux/serial_core.h>
22 #include <linux/platform_device.h>
23 #include <linux/sched.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/gpio.h>
26 #include <linux/irq.h>
29 #include <asm/proc-fns.h>
30 #include <asm/mach/arch.h>
31 #include <asm/mach/map.h>
32 #include <asm/mach/irq.h>
35 #include <mach/hardware.h>
36 #include <mach/regs-clock.h>
37 #include <mach/regs-gpio.h>
40 #include <plat/clock.h>
41 #include <plat/devs.h>
43 #include <plat/adc-core.h>
44 #include <plat/fb-core.h>
45 #include <plat/gpio-cfg.h>
46 #include <plat/regs-irqtype.h>
47 #include <plat/regs-serial.h>
51 static const char name_s5p6440[] = "S5P6440";
52 static const char name_s5p6450[] = "S5P6450";
54 static struct cpu_table cpu_ids[] __initdata = {
56 .idcode = S5P6440_CPU_ID,
57 .idmask = S5P64XX_CPU_MASK,
58 .map_io = s5p6440_map_io,
59 .init_clocks = s5p6440_init_clocks,
60 .init_uarts = s5p6440_init_uarts,
64 .idcode = S5P6450_CPU_ID,
65 .idmask = S5P64XX_CPU_MASK,
66 .map_io = s5p6450_map_io,
67 .init_clocks = s5p6450_init_clocks,
68 .init_uarts = s5p6450_init_uarts,
74 /* Initial IO mappings */
76 static struct map_desc s5p64x0_iodesc[] __initdata = {
78 .virtual = (unsigned long)S5P_VA_CHIPID,
79 .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID),
83 .virtual = (unsigned long)S3C_VA_SYS,
84 .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON),
88 .virtual = (unsigned long)S3C_VA_TIMER,
89 .pfn = __phys_to_pfn(S5P64X0_PA_TIMER),
93 .virtual = (unsigned long)S3C_VA_WATCHDOG,
94 .pfn = __phys_to_pfn(S5P64X0_PA_WDT),
98 .virtual = (unsigned long)S5P_VA_SROMC,
99 .pfn = __phys_to_pfn(S5P64X0_PA_SROMC),
103 .virtual = (unsigned long)S5P_VA_GPIO,
104 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
108 .virtual = (unsigned long)VA_VIC0,
109 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
113 .virtual = (unsigned long)VA_VIC1,
114 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
120 static struct map_desc s5p6440_iodesc[] __initdata = {
122 .virtual = (unsigned long)S3C_VA_UART,
123 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
129 static struct map_desc s5p6450_iodesc[] __initdata = {
131 .virtual = (unsigned long)S3C_VA_UART,
132 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
136 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
137 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
143 static void s5p64x0_idle(void)
147 if (!need_resched()) {
148 val = __raw_readl(S5P64X0_PWR_CFG);
151 __raw_writel(val, S5P64X0_PWR_CFG);
161 * register the standard CPU IO areas
164 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
166 /* initialize the io descriptors we need for initialization */
167 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
169 iotable_init(mach_desc, size);
171 /* detect cpu id and rev. */
172 s5p_init_cpu(S5P64X0_SYS_ID);
174 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
177 void __init s5p6440_map_io(void)
179 /* initialize any device information early */
180 s3c_adc_setname("s3c64xx-adc");
181 s3c_fb_setname("s5p64x0-fb");
183 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
184 init_consistent_dma_size(SZ_8M);
187 void __init s5p6450_map_io(void)
189 /* initialize any device information early */
190 s3c_adc_setname("s3c64xx-adc");
191 s3c_fb_setname("s5p64x0-fb");
193 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
194 init_consistent_dma_size(SZ_8M);
198 * s5p64x0_init_clocks
200 * register and setup the CPU clocks
203 void __init s5p6440_init_clocks(int xtal)
205 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
207 s3c24xx_register_baseclocks(xtal);
208 s5p_register_clocks(xtal);
209 s5p6440_register_clocks();
210 s5p6440_setup_clocks();
213 void __init s5p6450_init_clocks(int xtal)
215 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
217 s3c24xx_register_baseclocks(xtal);
218 s5p_register_clocks(xtal);
219 s5p6450_register_clocks();
220 s5p6450_setup_clocks();
226 * register the CPU interrupts
229 void __init s5p6440_init_irq(void)
231 /* S5P6440 supports 2 VIC */
235 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
236 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
241 s5p_init_irq(vic, ARRAY_SIZE(vic));
244 void __init s5p6450_init_irq(void)
246 /* S5P6450 supports only 2 VIC */
250 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
251 * VIC1 is missing IRQ VIC1[12, 14, 23]
256 s5p_init_irq(vic, ARRAY_SIZE(vic));
259 struct sysdev_class s5p64x0_sysclass = {
260 .name = "s5p64x0-core",
263 static struct sys_device s5p64x0_sysdev = {
264 .cls = &s5p64x0_sysclass,
267 static int __init s5p64x0_core_init(void)
269 return sysdev_class_register(&s5p64x0_sysclass);
271 core_initcall(s5p64x0_core_init);
273 int __init s5p64x0_init(void)
275 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
277 /* set idle function */
278 pm_idle = s5p64x0_idle;
280 return sysdev_register(&s5p64x0_sysdev);
283 static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = {
298 /* uart registration process */
300 void __init s5p64x0_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
302 struct s3c2410_uartcfg *tcfg = cfg;
305 for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
307 tcfg->clocks = s5p64x0_serial_clocks;
308 tcfg->clocks_size = ARRAY_SIZE(s5p64x0_serial_clocks);
313 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
317 for (uart = 0; uart < no; uart++) {
318 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
319 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
322 s5p64x0_common_init_uarts(cfg, no);
323 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
326 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
328 s5p64x0_common_init_uarts(cfg, no);
329 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
332 #define eint_offset(irq) ((irq) - IRQ_EINT(0))
334 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
336 int offs = eint_offset(data->irq);
346 printk(KERN_WARNING "No edge setting!\n");
348 case IRQ_TYPE_EDGE_RISING:
349 newvalue = S3C2410_EXTINT_RISEEDGE;
351 case IRQ_TYPE_EDGE_FALLING:
352 newvalue = S3C2410_EXTINT_FALLEDGE;
354 case IRQ_TYPE_EDGE_BOTH:
355 newvalue = S3C2410_EXTINT_BOTHEDGE;
357 case IRQ_TYPE_LEVEL_LOW:
358 newvalue = S3C2410_EXTINT_LOWLEV;
360 case IRQ_TYPE_LEVEL_HIGH:
361 newvalue = S3C2410_EXTINT_HILEV;
364 printk(KERN_ERR "No such irq type %d", type);
368 shift = (offs / 2) * 4;
371 ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
372 ctrl |= newvalue << shift;
373 __raw_writel(ctrl, S5P64X0_EINT0CON0);
375 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
376 if (soc_is_s5p6450())
377 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
379 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
385 * s5p64x0_irq_demux_eint
387 * This function demuxes the IRQ from the group0 external interrupts,
388 * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
389 * the specific handlers s5p64x0_irq_demux_eintX_Y.
391 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
393 u32 status = __raw_readl(S5P64X0_EINT0PEND);
394 u32 mask = __raw_readl(S5P64X0_EINT0MASK);
399 status &= (1 << (end - start + 1)) - 1;
401 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
403 generic_handle_irq(irq);
408 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
410 s5p64x0_irq_demux_eint(0, 3);
413 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
415 s5p64x0_irq_demux_eint(4, 11);
418 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
419 struct irq_desc *desc)
421 s5p64x0_irq_demux_eint(12, 15);
424 static int s5p64x0_alloc_gc(void)
426 struct irq_chip_generic *gc;
427 struct irq_chip_type *ct;
429 gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
430 S5P_VA_GPIO, handle_level_irq);
432 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
433 "external interrupts failed\n", __func__);
438 ct->chip.irq_ack = irq_gc_ack_set_bit;
439 ct->chip.irq_mask = irq_gc_mask_set_bit;
440 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
441 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
442 ct->chip.irq_set_wake = s3c_irqext_wake;
443 ct->regs.ack = EINT0PEND_OFFSET;
444 ct->regs.mask = EINT0MASK_OFFSET;
445 irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
446 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
450 static int __init s5p64x0_init_irq_eint(void)
452 int ret = s5p64x0_alloc_gc();
453 irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
454 irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
455 irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
459 arch_initcall(s5p64x0_init_irq_eint);