3d211dc2f2f90923136b55a8e814e842463e49d0
[linux-3.10.git] / arch / arm / mach-s3c2410 / dma.c
1 /* linux/arch/arm/mach-s3c2410/dma.c
2  *
3  * (c) 2003-2005,2006 Simtec Electronics
4  *      Ben Dooks <ben@simtec.co.uk>
5  *
6  * S3C2410 DMA core
7  *
8  * http://armlinux.simtec.co.uk/
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13 */
14
15
16 #ifdef CONFIG_S3C2410_DMA_DEBUG
17 #define DEBUG
18 #endif
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/sched.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/delay.h>
29
30 #include <asm/system.h>
31 #include <asm/irq.h>
32 #include <asm/hardware.h>
33 #include <asm/io.h>
34 #include <asm/dma.h>
35
36 #include <asm/mach/dma.h>
37 #include <asm/arch/map.h>
38
39 #include "dma.h"
40
41 /* io map for dma */
42 static void __iomem *dma_base;
43 static kmem_cache_t *dma_kmem;
44
45 struct s3c24xx_dma_selection dma_sel;
46
47 /* dma channel state information */
48 struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
49
50 /* debugging functions */
51
52 #define BUF_MAGIC (0xcafebabe)
53
54 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
55
56 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
57
58 #if 1
59 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
60 #else
61 static inline void
62 dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
63 {
64         pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
65         writel(val, dma_regaddr(chan, reg));
66 }
67 #endif
68
69 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
70
71 /* captured register state for debug */
72
73 struct s3c2410_dma_regstate {
74         unsigned long         dcsrc;
75         unsigned long         disrc;
76         unsigned long         dstat;
77         unsigned long         dcon;
78         unsigned long         dmsktrig;
79 };
80
81 #ifdef CONFIG_S3C2410_DMA_DEBUG
82
83 /* dmadbg_showregs
84  *
85  * simple debug routine to print the current state of the dma registers
86 */
87
88 static void
89 dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
90 {
91         regs->dcsrc    = dma_rdreg(chan, S3C2410_DMA_DCSRC);
92         regs->disrc    = dma_rdreg(chan, S3C2410_DMA_DISRC);
93         regs->dstat    = dma_rdreg(chan, S3C2410_DMA_DSTAT);
94         regs->dcon     = dma_rdreg(chan, S3C2410_DMA_DCON);
95         regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
96 }
97
98 static void
99 dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
100                  struct s3c2410_dma_regstate *regs)
101 {
102         printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
103                chan->number, fname, line,
104                regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
105                regs->dcon);
106 }
107
108 static void
109 dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
110 {
111         struct s3c2410_dma_regstate state;
112
113         dmadbg_capture(chan, &state);
114
115         printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
116                chan->number, fname, line, chan->load_state,
117                chan->curr, chan->next, chan->end);
118
119         dmadbg_dumpregs(fname, line, chan, &state);
120 }
121
122 static void
123 dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
124 {
125         struct s3c2410_dma_regstate state;
126
127         dmadbg_capture(chan, &state);
128         dmadbg_dumpregs(fname, line, chan, &state);
129 }
130
131 #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))
132 #define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))
133 #else
134 #define dbg_showregs(chan) do { } while(0)
135 #define dbg_showchan(chan) do { } while(0)
136 #endif /* CONFIG_S3C2410_DMA_DEBUG */
137
138 static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
139
140 /* lookup_dma_channel
141  *
142  * change the dma channel number given into a real dma channel id
143 */
144
145 static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
146 {
147         if (channel & DMACH_LOW_LEVEL)
148                 return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
149         else
150                 return dma_chan_map[channel];
151 }
152
153 /* s3c2410_dma_stats_timeout
154  *
155  * Update DMA stats from timeout info
156 */
157
158 static void
159 s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
160 {
161         if (stats == NULL)
162                 return;
163
164         if (val > stats->timeout_longest)
165                 stats->timeout_longest = val;
166         if (val < stats->timeout_shortest)
167                 stats->timeout_shortest = val;
168
169         stats->timeout_avg += val;
170 }
171
172 /* s3c2410_dma_waitforload
173  *
174  * wait for the DMA engine to load a buffer, and update the state accordingly
175 */
176
177 static int
178 s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
179 {
180         int timeout = chan->load_timeout;
181         int took;
182
183         if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
184                 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
185                 return 0;
186         }
187
188         if (chan->stats != NULL)
189                 chan->stats->loads++;
190
191         while (--timeout > 0) {
192                 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
193                         took = chan->load_timeout - timeout;
194
195                         s3c2410_dma_stats_timeout(chan->stats, took);
196
197                         switch (chan->load_state) {
198                         case S3C2410_DMALOAD_1LOADED:
199                                 chan->load_state = S3C2410_DMALOAD_1RUNNING;
200                                 break;
201
202                         default:
203                                 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
204                         }
205
206                         return 1;
207                 }
208         }
209
210         if (chan->stats != NULL) {
211                 chan->stats->timeout_failed++;
212         }
213
214         return 0;
215 }
216
217
218
219 /* s3c2410_dma_loadbuffer
220  *
221  * load a buffer, and update the channel state
222 */
223
224 static inline int
225 s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
226                        struct s3c2410_dma_buf *buf)
227 {
228         unsigned long reload;
229
230         pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
231                  buf, (unsigned long)buf->data, buf->size);
232
233         if (buf == NULL) {
234                 dmawarn("buffer is NULL\n");
235                 return -EINVAL;
236         }
237
238         /* check the state of the channel before we do anything */
239
240         if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
241                 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
242         }
243
244         if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
245                 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
246         }
247
248         /* it would seem sensible if we are the last buffer to not bother
249          * with the auto-reload bit, so that the DMA engine will not try
250          * and load another transfer after this one has finished...
251          */
252         if (chan->load_state == S3C2410_DMALOAD_NONE) {
253                 pr_debug("load_state is none, checking for noreload (next=%p)\n",
254                          buf->next);
255                 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
256         } else {
257                 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
258                 reload = S3C2410_DCON_AUTORELOAD;
259         }
260
261         if ((buf->data & 0xf0000000) != 0x30000000) {
262                 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
263         }
264
265         writel(buf->data, chan->addr_reg);
266
267         dma_wrreg(chan, S3C2410_DMA_DCON,
268                   chan->dcon | reload | (buf->size/chan->xfer_unit));
269
270         chan->next = buf->next;
271
272         /* update the state of the channel */
273
274         switch (chan->load_state) {
275         case S3C2410_DMALOAD_NONE:
276                 chan->load_state = S3C2410_DMALOAD_1LOADED;
277                 break;
278
279         case S3C2410_DMALOAD_1RUNNING:
280                 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
281                 break;
282
283         default:
284                 dmawarn("dmaload: unknown state %d in loadbuffer\n",
285                         chan->load_state);
286                 break;
287         }
288
289         return 0;
290 }
291
292 /* s3c2410_dma_call_op
293  *
294  * small routine to call the op routine with the given op if it has been
295  * registered
296 */
297
298 static void
299 s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
300 {
301         if (chan->op_fn != NULL) {
302                 (chan->op_fn)(chan, op);
303         }
304 }
305
306 /* s3c2410_dma_buffdone
307  *
308  * small wrapper to check if callback routine needs to be called, and
309  * if so, call it
310 */
311
312 static inline void
313 s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
314                      enum s3c2410_dma_buffresult result)
315 {
316 #if 0
317         pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
318                  chan->callback_fn, buf, buf->id, buf->size, result);
319 #endif
320
321         if (chan->callback_fn != NULL) {
322                 (chan->callback_fn)(chan, buf->id, buf->size, result);
323         }
324 }
325
326 /* s3c2410_dma_start
327  *
328  * start a dma channel going
329 */
330
331 static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
332 {
333         unsigned long tmp;
334         unsigned long flags;
335
336         pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
337
338         local_irq_save(flags);
339
340         if (chan->state == S3C2410_DMA_RUNNING) {
341                 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
342                 local_irq_restore(flags);
343                 return 0;
344         }
345
346         chan->state = S3C2410_DMA_RUNNING;
347
348         /* check wether there is anything to load, and if not, see
349          * if we can find anything to load
350          */
351
352         if (chan->load_state == S3C2410_DMALOAD_NONE) {
353                 if (chan->next == NULL) {
354                         printk(KERN_ERR "dma%d: channel has nothing loaded\n",
355                                chan->number);
356                         chan->state = S3C2410_DMA_IDLE;
357                         local_irq_restore(flags);
358                         return -EINVAL;
359                 }
360
361                 s3c2410_dma_loadbuffer(chan, chan->next);
362         }
363
364         dbg_showchan(chan);
365
366         /* enable the channel */
367
368         if (!chan->irq_enabled) {
369                 enable_irq(chan->irq);
370                 chan->irq_enabled = 1;
371         }
372
373         /* start the channel going */
374
375         tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
376         tmp &= ~S3C2410_DMASKTRIG_STOP;
377         tmp |= S3C2410_DMASKTRIG_ON;
378         dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
379
380         pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
381
382 #if 0
383         /* the dma buffer loads should take care of clearing the AUTO
384          * reloading feature */
385         tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
386         tmp &= ~S3C2410_DCON_NORELOAD;
387         dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
388 #endif
389
390         s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
391
392         dbg_showchan(chan);
393
394         /* if we've only loaded one buffer onto the channel, then chec
395          * to see if we have another, and if so, try and load it so when
396          * the first buffer is finished, the new one will be loaded onto
397          * the channel */
398
399         if (chan->next != NULL) {
400                 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
401
402                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
403                                 pr_debug("%s: buff not yet loaded, no more todo\n",
404                                          __FUNCTION__);
405                         } else {
406                                 chan->load_state = S3C2410_DMALOAD_1RUNNING;
407                                 s3c2410_dma_loadbuffer(chan, chan->next);
408                         }
409
410                 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
411                         s3c2410_dma_loadbuffer(chan, chan->next);
412                 }
413         }
414
415
416         local_irq_restore(flags);
417
418         return 0;
419 }
420
421 /* s3c2410_dma_canload
422  *
423  * work out if we can queue another buffer into the DMA engine
424 */
425
426 static int
427 s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
428 {
429         if (chan->load_state == S3C2410_DMALOAD_NONE ||
430             chan->load_state == S3C2410_DMALOAD_1RUNNING)
431                 return 1;
432
433         return 0;
434 }
435
436 /* s3c2410_dma_enqueue
437  *
438  * queue an given buffer for dma transfer.
439  *
440  * id         the device driver's id information for this buffer
441  * data       the physical address of the buffer data
442  * size       the size of the buffer in bytes
443  *
444  * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
445  * is checked, and if set, the channel is started. If this flag isn't set,
446  * then an error will be returned.
447  *
448  * It is possible to queue more than one DMA buffer onto a channel at
449  * once, and the code will deal with the re-loading of the next buffer
450  * when necessary.
451 */
452
453 int s3c2410_dma_enqueue(unsigned int channel, void *id,
454                         dma_addr_t data, int size)
455 {
456         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
457         struct s3c2410_dma_buf *buf;
458         unsigned long flags;
459
460         if (chan == NULL)
461                 return -EINVAL;
462
463         pr_debug("%s: id=%p, data=%08x, size=%d\n",
464                  __FUNCTION__, id, (unsigned int)data, size);
465
466         buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
467         if (buf == NULL) {
468                 pr_debug("%s: out of memory (%ld alloc)\n",
469                          __FUNCTION__, (long)sizeof(*buf));
470                 return -ENOMEM;
471         }
472
473         //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
474         //dbg_showchan(chan);
475
476         buf->next  = NULL;
477         buf->data  = buf->ptr = data;
478         buf->size  = size;
479         buf->id    = id;
480         buf->magic = BUF_MAGIC;
481
482         local_irq_save(flags);
483
484         if (chan->curr == NULL) {
485                 /* we've got nothing loaded... */
486                 pr_debug("%s: buffer %p queued onto empty channel\n",
487                          __FUNCTION__, buf);
488
489                 chan->curr = buf;
490                 chan->end  = buf;
491                 chan->next = NULL;
492         } else {
493                 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
494                          chan->number, __FUNCTION__, buf);
495
496                 if (chan->end == NULL)
497                         pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
498                                  chan->number, __FUNCTION__, chan);
499
500                 chan->end->next = buf;
501                 chan->end = buf;
502         }
503
504         /* if necessary, update the next buffer field */
505         if (chan->next == NULL)
506                 chan->next = buf;
507
508         /* check to see if we can load a buffer */
509         if (chan->state == S3C2410_DMA_RUNNING) {
510                 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
511                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
512                                 printk(KERN_ERR "dma%d: loadbuffer:"
513                                        "timeout loading buffer\n",
514                                        chan->number);
515                                 dbg_showchan(chan);
516                                 local_irq_restore(flags);
517                                 return -EINVAL;
518                         }
519                 }
520
521                 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
522                         s3c2410_dma_loadbuffer(chan, chan->next);
523                 }
524         } else if (chan->state == S3C2410_DMA_IDLE) {
525                 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
526                         s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);
527                 }
528         }
529
530         local_irq_restore(flags);
531         return 0;
532 }
533
534 EXPORT_SYMBOL(s3c2410_dma_enqueue);
535
536 static inline void
537 s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
538 {
539         int magicok = (buf->magic == BUF_MAGIC);
540
541         buf->magic = -1;
542
543         if (magicok) {
544                 kmem_cache_free(dma_kmem, buf);
545         } else {
546                 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
547         }
548 }
549
550 /* s3c2410_dma_lastxfer
551  *
552  * called when the system is out of buffers, to ensure that the channel
553  * is prepared for shutdown.
554 */
555
556 static inline void
557 s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
558 {
559 #if 0
560         pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
561                  chan->number, chan->load_state);
562 #endif
563
564         switch (chan->load_state) {
565         case S3C2410_DMALOAD_NONE:
566                 break;
567
568         case S3C2410_DMALOAD_1LOADED:
569                 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
570                                 /* flag error? */
571                         printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
572                                chan->number, __FUNCTION__);
573                         return;
574                 }
575                 break;
576
577         case S3C2410_DMALOAD_1LOADED_1RUNNING:
578                 /* I belive in this case we do not have anything to do
579                  * until the next buffer comes along, and we turn off the
580                  * reload */
581                 return;
582
583         default:
584                 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
585                          chan->number, chan->load_state);
586                 return;
587
588         }
589
590         /* hopefully this'll shut the damned thing up after the transfer... */
591         dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
592 }
593
594
595 #define dmadbg2(x...)
596
597 static irqreturn_t
598 s3c2410_dma_irq(int irq, void *devpw)
599 {
600         struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
601         struct s3c2410_dma_buf  *buf;
602
603         buf = chan->curr;
604
605         dbg_showchan(chan);
606
607         /* modify the channel state */
608
609         switch (chan->load_state) {
610         case S3C2410_DMALOAD_1RUNNING:
611                 /* TODO - if we are running only one buffer, we probably
612                  * want to reload here, and then worry about the buffer
613                  * callback */
614
615                 chan->load_state = S3C2410_DMALOAD_NONE;
616                 break;
617
618         case S3C2410_DMALOAD_1LOADED:
619                 /* iirc, we should go back to NONE loaded here, we
620                  * had a buffer, and it was never verified as being
621                  * loaded.
622                  */
623
624                 chan->load_state = S3C2410_DMALOAD_NONE;
625                 break;
626
627         case S3C2410_DMALOAD_1LOADED_1RUNNING:
628                 /* we'll worry about checking to see if another buffer is
629                  * ready after we've called back the owner. This should
630                  * ensure we do not wait around too long for the DMA
631                  * engine to start the next transfer
632                  */
633
634                 chan->load_state = S3C2410_DMALOAD_1LOADED;
635                 break;
636
637         case S3C2410_DMALOAD_NONE:
638                 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
639                        chan->number);
640                 break;
641
642         default:
643                 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
644                        chan->number, chan->load_state);
645                 break;
646         }
647
648         if (buf != NULL) {
649                 /* update the chain to make sure that if we load any more
650                  * buffers when we call the callback function, things should
651                  * work properly */
652
653                 chan->curr = buf->next;
654                 buf->next  = NULL;
655
656                 if (buf->magic != BUF_MAGIC) {
657                         printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
658                                chan->number, __FUNCTION__, buf);
659                         return IRQ_HANDLED;
660                 }
661
662                 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
663
664                 /* free resouces */
665                 s3c2410_dma_freebuf(buf);
666         } else {
667         }
668
669         /* only reload if the channel is still running... our buffer done
670          * routine may have altered the state by requesting the dma channel
671          * to stop or shutdown... */
672
673         /* todo: check that when the channel is shut-down from inside this
674          * function, we cope with unsetting reload, etc */
675
676         if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
677                 unsigned long flags;
678
679                 switch (chan->load_state) {
680                 case S3C2410_DMALOAD_1RUNNING:
681                         /* don't need to do anything for this state */
682                         break;
683
684                 case S3C2410_DMALOAD_NONE:
685                         /* can load buffer immediately */
686                         break;
687
688                 case S3C2410_DMALOAD_1LOADED:
689                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
690                                 /* flag error? */
691                                 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
692                                        chan->number, __FUNCTION__);
693                                 return IRQ_HANDLED;
694                         }
695
696                         break;
697
698                 case S3C2410_DMALOAD_1LOADED_1RUNNING:
699                         goto no_load;
700
701                 default:
702                         printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
703                                chan->number, chan->load_state);
704                         return IRQ_HANDLED;
705                 }
706
707                 local_irq_save(flags);
708                 s3c2410_dma_loadbuffer(chan, chan->next);
709                 local_irq_restore(flags);
710         } else {
711                 s3c2410_dma_lastxfer(chan);
712
713                 /* see if we can stop this channel.. */
714                 if (chan->load_state == S3C2410_DMALOAD_NONE) {
715                         pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
716                                  chan->number, jiffies);
717                         s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
718                                          S3C2410_DMAOP_STOP);
719                 }
720         }
721
722  no_load:
723         return IRQ_HANDLED;
724 }
725
726 static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
727
728 /* s3c2410_request_dma
729  *
730  * get control of an dma channel
731 */
732
733 int s3c2410_dma_request(unsigned int channel,
734                         struct s3c2410_dma_client *client,
735                         void *dev)
736 {
737         struct s3c2410_dma_chan *chan;
738         unsigned long flags;
739         int err;
740
741         pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
742                  channel, client->name, dev);
743
744         local_irq_save(flags);
745
746         chan = s3c2410_dma_map_channel(channel);
747         if (chan == NULL) {
748                 local_irq_restore(flags);
749                 return -EBUSY;
750         }
751
752         dbg_showchan(chan);
753
754         chan->client = client;
755         chan->in_use = 1;
756
757         if (!chan->irq_claimed) {
758                 pr_debug("dma%d: %s : requesting irq %d\n",
759                          channel, __FUNCTION__, chan->irq);
760
761                 chan->irq_claimed = 1;
762                 local_irq_restore(flags);
763
764                 err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
765                                   client->name, (void *)chan);
766
767                 local_irq_save(flags);
768
769                 if (err) {
770                         chan->in_use = 0;
771                         chan->irq_claimed = 0;
772                         local_irq_restore(flags);
773
774                         printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
775                                client->name, chan->irq, chan->number);
776                         return err;
777                 }
778
779                 chan->irq_enabled = 1;
780         }
781
782         local_irq_restore(flags);
783
784         /* need to setup */
785
786         pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
787
788         return 0;
789 }
790
791 EXPORT_SYMBOL(s3c2410_dma_request);
792
793 /* s3c2410_dma_free
794  *
795  * release the given channel back to the system, will stop and flush
796  * any outstanding transfers, and ensure the channel is ready for the
797  * next claimant.
798  *
799  * Note, although a warning is currently printed if the freeing client
800  * info is not the same as the registrant's client info, the free is still
801  * allowed to go through.
802 */
803
804 int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
805 {
806         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
807         unsigned long flags;
808
809         if (chan == NULL)
810                 return -EINVAL;
811
812         local_irq_save(flags);
813
814         if (chan->client != client) {
815                 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
816                        channel, chan->client, client);
817         }
818
819         /* sort out stopping and freeing the channel */
820
821         if (chan->state != S3C2410_DMA_IDLE) {
822                 pr_debug("%s: need to stop dma channel %p\n",
823                        __FUNCTION__, chan);
824
825                 /* possibly flush the channel */
826                 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
827         }
828
829         chan->client = NULL;
830         chan->in_use = 0;
831
832         if (chan->irq_claimed)
833                 free_irq(chan->irq, (void *)chan);
834
835         chan->irq_claimed = 0;
836
837         if (!(channel & DMACH_LOW_LEVEL))
838                 dma_chan_map[channel] = NULL;
839
840         local_irq_restore(flags);
841
842         return 0;
843 }
844
845 EXPORT_SYMBOL(s3c2410_dma_free);
846
847 static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
848 {
849         unsigned long flags;
850         unsigned long tmp;
851
852         pr_debug("%s:\n", __FUNCTION__);
853
854         dbg_showchan(chan);
855
856         local_irq_save(flags);
857
858         s3c2410_dma_call_op(chan,  S3C2410_DMAOP_STOP);
859
860         tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
861         tmp |= S3C2410_DMASKTRIG_STOP;
862         //tmp &= ~S3C2410_DMASKTRIG_ON;
863         dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
864
865 #if 0
866         /* should also clear interrupts, according to WinCE BSP */
867         tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
868         tmp |= S3C2410_DCON_NORELOAD;
869         dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
870 #endif
871
872         /* should stop do this, or should we wait for flush? */
873         chan->state      = S3C2410_DMA_IDLE;
874         chan->load_state = S3C2410_DMALOAD_NONE;
875
876         local_irq_restore(flags);
877
878         return 0;
879 }
880
881 void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
882 {
883         unsigned long tmp;
884         unsigned int timeout = 0x10000;
885
886         while (timeout-- > 0) {
887                 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
888
889                 if (!(tmp & S3C2410_DMASKTRIG_ON))
890                         return;
891         }
892
893         pr_debug("dma%d: failed to stop?\n", chan->number);
894 }
895
896
897 /* s3c2410_dma_flush
898  *
899  * stop the channel, and remove all current and pending transfers
900 */
901
902 static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
903 {
904         struct s3c2410_dma_buf *buf, *next;
905         unsigned long flags;
906
907         pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number);
908
909         dbg_showchan(chan);
910
911         local_irq_save(flags);
912
913         if (chan->state != S3C2410_DMA_IDLE) {
914                 pr_debug("%s: stopping channel...\n", __FUNCTION__ );
915                 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
916         }
917
918         buf = chan->curr;
919         if (buf == NULL)
920                 buf = chan->next;
921
922         chan->curr = chan->next = chan->end = NULL;
923
924         if (buf != NULL) {
925                 for ( ; buf != NULL; buf = next) {
926                         next = buf->next;
927
928                         pr_debug("%s: free buffer %p, next %p\n",
929                                __FUNCTION__, buf, buf->next);
930
931                         s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
932                         s3c2410_dma_freebuf(buf);
933                 }
934         }
935
936         dbg_showregs(chan);
937
938         s3c2410_dma_waitforstop(chan);
939
940 #if 0
941         /* should also clear interrupts, according to WinCE BSP */
942         {
943                 unsigned long tmp;
944
945                 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
946                 tmp |= S3C2410_DCON_NORELOAD;
947                 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
948         }
949 #endif
950
951         dbg_showregs(chan);
952
953         local_irq_restore(flags);
954
955         return 0;
956 }
957
958 int
959 s3c2410_dma_started(struct s3c2410_dma_chan *chan)
960 {
961         unsigned long flags;
962
963         local_irq_save(flags);
964
965         dbg_showchan(chan);
966
967         /* if we've only loaded one buffer onto the channel, then chec
968          * to see if we have another, and if so, try and load it so when
969          * the first buffer is finished, the new one will be loaded onto
970          * the channel */
971
972         if (chan->next != NULL) {
973                 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
974
975                         if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
976                                 pr_debug("%s: buff not yet loaded, no more todo\n",
977                                          __FUNCTION__);
978                         } else {
979                                 chan->load_state = S3C2410_DMALOAD_1RUNNING;
980                                 s3c2410_dma_loadbuffer(chan, chan->next);
981                         }
982
983                 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
984                         s3c2410_dma_loadbuffer(chan, chan->next);
985                 }
986         }
987
988
989         local_irq_restore(flags);
990
991         return 0;
992
993 }
994
995 int
996 s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
997 {
998         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
999
1000         if (chan == NULL)
1001                 return -EINVAL;
1002
1003         switch (op) {
1004         case S3C2410_DMAOP_START:
1005                 return s3c2410_dma_start(chan);
1006
1007         case S3C2410_DMAOP_STOP:
1008                 return s3c2410_dma_dostop(chan);
1009
1010         case S3C2410_DMAOP_PAUSE:
1011         case S3C2410_DMAOP_RESUME:
1012                 return -ENOENT;
1013
1014         case S3C2410_DMAOP_FLUSH:
1015                 return s3c2410_dma_flush(chan);
1016
1017         case S3C2410_DMAOP_STARTED:
1018                 return s3c2410_dma_started(chan);
1019
1020         case S3C2410_DMAOP_TIMEOUT:
1021                 return 0;
1022
1023         }
1024
1025         return -ENOENT;      /* unknown, don't bother */
1026 }
1027
1028 EXPORT_SYMBOL(s3c2410_dma_ctrl);
1029
1030 /* DMA configuration for each channel
1031  *
1032  * DISRCC -> source of the DMA (AHB,APB)
1033  * DISRC  -> source address of the DMA
1034  * DIDSTC -> destination of the DMA (AHB,APD)
1035  * DIDST  -> destination address of the DMA
1036 */
1037
1038 /* s3c2410_dma_config
1039  *
1040  * xfersize:     size of unit in bytes (1,2,4)
1041  * dcon:         base value of the DCONx register
1042 */
1043
1044 int s3c2410_dma_config(dmach_t channel,
1045                        int xferunit,
1046                        int dcon)
1047 {
1048         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1049
1050         pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
1051                  __FUNCTION__, channel, xferunit, dcon);
1052
1053         if (chan == NULL)
1054                 return -EINVAL;
1055
1056         printk("Initial dcon is %08x\n", dcon);
1057
1058         dcon |= chan->dcon & dma_sel.dcon_mask;
1059
1060         printk("New dcon is %08x\n", dcon);
1061
1062         switch (xferunit) {
1063         case 1:
1064                 dcon |= S3C2410_DCON_BYTE;
1065                 break;
1066
1067         case 2:
1068                 dcon |= S3C2410_DCON_HALFWORD;
1069                 break;
1070
1071         case 4:
1072                 dcon |= S3C2410_DCON_WORD;
1073                 break;
1074
1075         default:
1076                 pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit);
1077                 return -EINVAL;
1078         }
1079
1080         dcon |= S3C2410_DCON_HWTRIG;
1081         dcon |= S3C2410_DCON_INTREQ;
1082
1083         pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
1084
1085         chan->dcon = dcon;
1086         chan->xfer_unit = xferunit;
1087
1088         return 0;
1089 }
1090
1091 EXPORT_SYMBOL(s3c2410_dma_config);
1092
1093 int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
1094 {
1095         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1096
1097         if (chan == NULL)
1098                 return -EINVAL;
1099
1100         pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
1101
1102         chan->flags = flags;
1103
1104         return 0;
1105 }
1106
1107 EXPORT_SYMBOL(s3c2410_dma_setflags);
1108
1109
1110 /* do we need to protect the settings of the fields from
1111  * irq?
1112 */
1113
1114 int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
1115 {
1116         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1117
1118         if (chan == NULL)
1119                 return -EINVAL;
1120
1121         pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
1122
1123         chan->op_fn = rtn;
1124
1125         return 0;
1126 }
1127
1128 EXPORT_SYMBOL(s3c2410_dma_set_opfn);
1129
1130 int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
1131 {
1132         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1133
1134         if (chan == NULL)
1135                 return -EINVAL;
1136
1137         pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
1138
1139         chan->callback_fn = rtn;
1140
1141         return 0;
1142 }
1143
1144 EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
1145
1146 /* s3c2410_dma_devconfig
1147  *
1148  * configure the dma source/destination hardware type and address
1149  *
1150  * source:    S3C2410_DMASRC_HW: source is hardware
1151  *            S3C2410_DMASRC_MEM: source is memory
1152  *
1153  * hwcfg:     the value for xxxSTCn register,
1154  *            bit 0: 0=increment pointer, 1=leave pointer
1155  *            bit 1: 0=soucre is AHB, 1=soucre is APB
1156  *
1157  * devaddr:   physical address of the source
1158 */
1159
1160 int s3c2410_dma_devconfig(int channel,
1161                           enum s3c2410_dmasrc source,
1162                           int hwcfg,
1163                           unsigned long devaddr)
1164 {
1165         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1166
1167         if (chan == NULL)
1168                 return -EINVAL;
1169
1170         pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
1171                  __FUNCTION__, (int)source, hwcfg, devaddr);
1172
1173         chan->source = source;
1174         chan->dev_addr = devaddr;
1175
1176         switch (source) {
1177         case S3C2410_DMASRC_HW:
1178                 /* source is hardware */
1179                 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1180                          __FUNCTION__, devaddr, hwcfg);
1181                 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1182                 dma_wrreg(chan, S3C2410_DMA_DISRC,  devaddr);
1183                 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1184
1185                 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1186                 return 0;
1187
1188         case S3C2410_DMASRC_MEM:
1189                 /* source is memory */
1190                 pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1191                           __FUNCTION__, devaddr, hwcfg);
1192                 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1193                 dma_wrreg(chan, S3C2410_DMA_DIDST,  devaddr);
1194                 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1195
1196                 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1197                 return 0;
1198         }
1199
1200         printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source);
1201         return -EINVAL;
1202 }
1203
1204 EXPORT_SYMBOL(s3c2410_dma_devconfig);
1205
1206 /* s3c2410_dma_getposition
1207  *
1208  * returns the current transfer points for the dma source and destination
1209 */
1210
1211 int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
1212 {
1213         struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
1214
1215         if (chan == NULL)
1216                 return -EINVAL;
1217
1218         if (src != NULL)
1219                 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1220
1221         if (dst != NULL)
1222                 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1223
1224         return 0;
1225 }
1226
1227 EXPORT_SYMBOL(s3c2410_dma_getposition);
1228
1229
1230 /* system device class */
1231
1232 #ifdef CONFIG_PM
1233
1234 static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
1235 {
1236         struct s3c2410_dma_chan *cp = container_of(dev, struct s3c2410_dma_chan, dev);
1237
1238         printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1239
1240         if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1241                 /* the dma channel is still working, which is probably
1242                  * a bad thing to do over suspend/resume. We stop the
1243                  * channel and assume that the client is either going to
1244                  * retry after resume, or that it is broken.
1245                  */
1246
1247                 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1248                        cp->number);
1249
1250                 s3c2410_dma_dostop(cp);
1251         }
1252
1253         return 0;
1254 }
1255
1256 static int s3c2410_dma_resume(struct sys_device *dev)
1257 {
1258         return 0;
1259 }
1260
1261 #else
1262 #define s3c2410_dma_suspend NULL
1263 #define s3c2410_dma_resume  NULL
1264 #endif /* CONFIG_PM */
1265
1266 struct sysdev_class dma_sysclass = {
1267         set_kset_name("s3c24xx-dma"),
1268         .suspend        = s3c2410_dma_suspend,
1269         .resume         = s3c2410_dma_resume,
1270 };
1271
1272 /* kmem cache implementation */
1273
1274 static void s3c2410_dma_cache_ctor(void *p, kmem_cache_t *c, unsigned long f)
1275 {
1276         memset(p, 0, sizeof(struct s3c2410_dma_buf));
1277 }
1278
1279 /* initialisation code */
1280
1281 static int __init s3c2410_init_dma(void)
1282 {
1283         struct s3c2410_dma_chan *cp;
1284         int channel;
1285         int ret;
1286
1287         printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
1288
1289         dma_base = ioremap(S3C24XX_PA_DMA, 0x200);
1290         if (dma_base == NULL) {
1291                 printk(KERN_ERR "dma failed to remap register block\n");
1292                 return -ENOMEM;
1293         }
1294
1295         printk("Registering sysclass\n");
1296
1297         ret = sysdev_class_register(&dma_sysclass);
1298         if (ret != 0) {
1299                 printk(KERN_ERR "dma sysclass registration failed\n");
1300                 goto err;
1301         }
1302
1303         dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0,
1304                                      SLAB_HWCACHE_ALIGN,
1305                                      s3c2410_dma_cache_ctor, NULL);
1306
1307         if (dma_kmem == NULL) {
1308                 printk(KERN_ERR "dma failed to make kmem cache\n");
1309                 ret = -ENOMEM;
1310                 goto err;
1311         }
1312
1313         for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) {
1314                 cp = &s3c2410_chans[channel];
1315
1316                 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1317
1318                 /* dma channel irqs are in order.. */
1319                 cp->number = channel;
1320                 cp->irq    = channel + IRQ_DMA0;
1321                 cp->regs   = dma_base + (channel*0x40);
1322
1323                 /* point current stats somewhere */
1324                 cp->stats  = &cp->stats_store;
1325                 cp->stats_store.timeout_shortest = LONG_MAX;
1326
1327                 /* basic channel configuration */
1328
1329                 cp->load_timeout = 1<<18;
1330
1331                 /* register system device */
1332
1333                 cp->dev.cls = &dma_sysclass;
1334                 cp->dev.id  = channel;
1335                 ret = sysdev_register(&cp->dev);
1336
1337                 printk("DMA channel %d at %p, irq %d\n",
1338                        cp->number, cp->regs, cp->irq);
1339         }
1340
1341         return 0;
1342
1343  err:
1344         kmem_cache_destroy(dma_kmem);
1345         iounmap(dma_base);
1346         dma_base = NULL;
1347         return ret;
1348 }
1349
1350 core_initcall(s3c2410_init_dma);
1351
1352 static inline int is_channel_valid(unsigned int channel)
1353 {
1354         return (channel & DMA_CH_VALID);
1355 }
1356
1357 /* s3c2410_dma_map_channel()
1358  *
1359  * turn the virtual channel number into a real, and un-used hardware
1360  * channel.
1361  *
1362  * currently this code uses first-free channel from the specified harware
1363  * map, not taking into account anything that the board setup code may
1364  * have to say about the likely peripheral set to be in use.
1365 */
1366
1367 struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1368 {
1369         struct s3c24xx_dma_map *ch_map;
1370         struct s3c2410_dma_chan *dmach;
1371         int ch;
1372
1373         if (dma_sel.map == NULL || channel > dma_sel.map_size)
1374                 return NULL;
1375
1376         ch_map = dma_sel.map + channel;
1377
1378         for (ch = 0; ch < S3C2410_DMA_CHANNELS; ch++) {
1379                 if (!is_channel_valid(ch_map->channels[ch]))
1380                         continue;
1381
1382                 if (s3c2410_chans[ch].in_use == 0) {
1383                         printk("mapped channel %d to %d\n", channel, ch);
1384                         break;
1385                 }
1386         }
1387
1388         if (ch >= S3C2410_DMA_CHANNELS)
1389                 return NULL;
1390
1391         /* update our channel mapping */
1392
1393         dmach = &s3c2410_chans[ch];
1394         dma_chan_map[channel] = dmach;
1395
1396         /* select the channel */
1397
1398         (dma_sel.select)(dmach, ch_map);
1399
1400         return dmach;
1401 }
1402
1403 static void s3c24xx_dma_show_ch(struct s3c24xx_dma_map *map, int ch)
1404 {
1405         /* show the channel configuration */
1406
1407         printk("%2d: %20s, channels %c%c%c%c\n", ch, map->name,
1408                (is_channel_valid(map->channels[0]) ? '0' : '-'),
1409                (is_channel_valid(map->channels[1]) ? '1' : '-'),
1410                (is_channel_valid(map->channels[2]) ? '2' : '-'),
1411                (is_channel_valid(map->channels[3]) ? '3' : '-'));
1412 }
1413
1414 static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1415 {
1416         if (1)
1417                 s3c24xx_dma_show_ch(map, ch);
1418
1419         return 0;
1420 }
1421
1422 int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1423 {
1424         struct s3c24xx_dma_map *nmap;
1425         size_t map_sz = sizeof(*nmap) * sel->map_size;
1426         int ptr;
1427
1428         nmap = kmalloc(map_sz, GFP_KERNEL);
1429         if (nmap == NULL)
1430                 return -ENOMEM;
1431
1432         memcpy(nmap, sel->map, map_sz);
1433         memcpy(&dma_sel, sel, sizeof(*sel));
1434
1435         dma_sel.map = nmap;
1436
1437         for (ptr = 0; ptr < sel->map_size; ptr++)
1438                 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1439
1440         return 0;
1441 }