[PATCH] ARM: fixup irqflags breakage after ARM genirq merge
[linux-3.10.git] / arch / arm / mach-pxa / mainstone.c
1 /*
2  *  linux/arch/arm/mach-pxa/mainstone.c
3  *
4  *  Support for the Intel HCDDBBVA0 Development Platform.
5  *  (go figure how they came up with such name...)
6  *
7  *  Author:     Nicolas Pitre
8  *  Created:    Nov 05, 2002
9  *  Copyright:  MontaVista Software Inc.
10  *
11  *  This program is free software; you can redistribute it and/or modify
12  *  it under the terms of the GNU General Public License version 2 as
13  *  published by the Free Software Foundation.
14  */
15
16 #include <linux/init.h>
17 #include <linux/platform_device.h>
18 #include <linux/sysdev.h>
19 #include <linux/interrupt.h>
20 #include <linux/sched.h>
21 #include <linux/bitops.h>
22 #include <linux/fb.h>
23 #include <linux/ioport.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/partitions.h>
26
27 #include <asm/types.h>
28 #include <asm/setup.h>
29 #include <asm/memory.h>
30 #include <asm/mach-types.h>
31 #include <asm/hardware.h>
32 #include <asm/irq.h>
33 #include <asm/sizes.h>
34
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach/flash.h>
39
40 #include <asm/arch/pxa-regs.h>
41 #include <asm/arch/mainstone.h>
42 #include <asm/arch/audio.h>
43 #include <asm/arch/pxafb.h>
44 #include <asm/arch/mmc.h>
45 #include <asm/arch/irda.h>
46 #include <asm/arch/ohci.h>
47
48 #include "generic.h"
49
50
51 static unsigned long mainstone_irq_enabled;
52
53 static void mainstone_mask_irq(unsigned int irq)
54 {
55         int mainstone_irq = (irq - MAINSTONE_IRQ(0));
56         MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
57 }
58
59 static void mainstone_unmask_irq(unsigned int irq)
60 {
61         int mainstone_irq = (irq - MAINSTONE_IRQ(0));
62         /* the irq can be acknowledged only if deasserted, so it's done here */
63         MST_INTSETCLR &= ~(1 << mainstone_irq);
64         MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
65 }
66
67 static struct irqchip mainstone_irq_chip = {
68         .ack            = mainstone_mask_irq,
69         .mask           = mainstone_mask_irq,
70         .unmask         = mainstone_unmask_irq,
71 };
72
73 static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc,
74                                   struct pt_regs *regs)
75 {
76         unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
77         do {
78                 GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
79                 if (likely(pending)) {
80                         irq = MAINSTONE_IRQ(0) + __ffs(pending);
81                         desc = irq_desc + irq;
82                         desc_handle_irq(irq, desc, regs);
83                 }
84                 pending = MST_INTSETCLR & mainstone_irq_enabled;
85         } while (pending);
86 }
87
88 static void __init mainstone_init_irq(void)
89 {
90         int irq;
91
92         pxa_init_irq();
93
94         /* setup extra Mainstone irqs */
95         for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
96                 set_irq_chip(irq, &mainstone_irq_chip);
97                 set_irq_handler(irq, do_level_IRQ);
98                 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
99                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
100                 else
101                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
102         }
103         set_irq_flags(MAINSTONE_IRQ(8), 0);
104         set_irq_flags(MAINSTONE_IRQ(12), 0);
105
106         MST_INTMSKENA = 0;
107         MST_INTSETCLR = 0;
108
109         set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
110         set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
111 }
112
113 #ifdef CONFIG_PM
114
115 static int mainstone_irq_resume(struct sys_device *dev)
116 {
117         MST_INTMSKENA = mainstone_irq_enabled;
118         return 0;
119 }
120
121 static struct sysdev_class mainstone_irq_sysclass = {
122         set_kset_name("cpld_irq"),
123         .resume = mainstone_irq_resume,
124 };
125
126 static struct sys_device mainstone_irq_device = {
127         .cls = &mainstone_irq_sysclass,
128 };
129
130 static int __init mainstone_irq_device_init(void)
131 {
132         int ret = sysdev_class_register(&mainstone_irq_sysclass);
133         if (ret == 0)
134                 ret = sysdev_register(&mainstone_irq_device);
135         return ret;
136 }
137
138 device_initcall(mainstone_irq_device_init);
139
140 #endif
141
142
143 static struct resource smc91x_resources[] = {
144         [0] = {
145                 .start  = (MST_ETH_PHYS + 0x300),
146                 .end    = (MST_ETH_PHYS + 0xfffff),
147                 .flags  = IORESOURCE_MEM,
148         },
149         [1] = {
150                 .start  = MAINSTONE_IRQ(3),
151                 .end    = MAINSTONE_IRQ(3),
152                 .flags  = IORESOURCE_IRQ,
153         }
154 };
155
156 static struct platform_device smc91x_device = {
157         .name           = "smc91x",
158         .id             = 0,
159         .num_resources  = ARRAY_SIZE(smc91x_resources),
160         .resource       = smc91x_resources,
161 };
162
163 static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
164 {
165         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
166                 MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
167         return 0;
168 }
169
170 static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
171 {
172         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
173                 MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
174 }
175
176 static long mst_audio_suspend_mask;
177
178 static void mst_audio_suspend(void *priv)
179 {
180         mst_audio_suspend_mask = MST_MSCWR2;
181         MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
182 }
183
184 static void mst_audio_resume(void *priv)
185 {
186         MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
187 }
188
189 static pxa2xx_audio_ops_t mst_audio_ops = {
190         .startup        = mst_audio_startup,
191         .shutdown       = mst_audio_shutdown,
192         .suspend        = mst_audio_suspend,
193         .resume         = mst_audio_resume,
194 };
195
196 static struct platform_device mst_audio_device = {
197         .name           = "pxa2xx-ac97",
198         .id             = -1,
199         .dev            = { .platform_data = &mst_audio_ops },
200 };
201
202 static struct resource flash_resources[] = {
203         [0] = {
204                 .start  = PXA_CS0_PHYS,
205                 .end    = PXA_CS0_PHYS + SZ_64M - 1,
206                 .flags  = IORESOURCE_MEM,
207         },
208         [1] = {
209                 .start  = PXA_CS1_PHYS,
210                 .end    = PXA_CS1_PHYS + SZ_64M - 1,
211                 .flags  = IORESOURCE_MEM,
212         },
213 };
214
215 static struct mtd_partition mainstoneflash0_partitions[] = {
216         {
217                 .name =         "Bootloader",
218                 .size =         0x00040000,
219                 .offset =       0,
220                 .mask_flags =   MTD_WRITEABLE  /* force read-only */
221         },{
222                 .name =         "Kernel",
223                 .size =         0x00400000,
224                 .offset =       0x00040000,
225         },{
226                 .name =         "Filesystem",
227                 .size =         MTDPART_SIZ_FULL,
228                 .offset =       0x00440000
229         }
230 };
231
232 static struct flash_platform_data mst_flash_data[2] = {
233         {
234                 .map_name       = "cfi_probe",
235                 .parts          = mainstoneflash0_partitions,
236                 .nr_parts       = ARRAY_SIZE(mainstoneflash0_partitions),
237         }, {
238                 .map_name       = "cfi_probe",
239                 .parts          = NULL,
240                 .nr_parts       = 0,
241         }
242 };
243
244 static struct platform_device mst_flash_device[2] = {
245         {
246                 .name           = "pxa2xx-flash",
247                 .id             = 0,
248                 .dev = {
249                         .platform_data = &mst_flash_data[0],
250                 },
251                 .resource = &flash_resources[0],
252                 .num_resources = 1,
253         },
254         {
255                 .name           = "pxa2xx-flash",
256                 .id             = 1,
257                 .dev = {
258                         .platform_data = &mst_flash_data[1],
259                 },
260                 .resource = &flash_resources[1],
261                 .num_resources = 1,
262         },
263 };
264
265 static void mainstone_backlight_power(int on)
266 {
267         if (on) {
268                 pxa_gpio_mode(GPIO16_PWM0_MD);
269                 pxa_set_cken(CKEN0_PWM0, 1);
270                 PWM_CTRL0 = 0;
271                 PWM_PWDUTY0 = 0x3ff;
272                 PWM_PERVAL0 = 0x3ff;
273         } else {
274                 PWM_CTRL0 = 0;
275                 PWM_PWDUTY0 = 0x0;
276                 PWM_PERVAL0 = 0x3FF;
277                 pxa_set_cken(CKEN0_PWM0, 0);
278         }
279 }
280
281 static struct pxafb_mach_info toshiba_ltm04c380k __initdata = {
282         .pixclock               = 50000,
283         .xres                   = 640,
284         .yres                   = 480,
285         .bpp                    = 16,
286         .hsync_len              = 1,
287         .left_margin            = 0x9f,
288         .right_margin           = 1,
289         .vsync_len              = 44,
290         .upper_margin           = 0,
291         .lower_margin           = 0,
292         .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
293         .lccr0                  = LCCR0_Act,
294         .lccr3                  = LCCR3_PCP,
295         .pxafb_backlight_power  = mainstone_backlight_power,
296 };
297
298 static struct pxafb_mach_info toshiba_ltm035a776c __initdata = {
299         .pixclock               = 110000,
300         .xres                   = 240,
301         .yres                   = 320,
302         .bpp                    = 16,
303         .hsync_len              = 4,
304         .left_margin            = 8,
305         .right_margin           = 20,
306         .vsync_len              = 3,
307         .upper_margin           = 1,
308         .lower_margin           = 10,
309         .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
310         .lccr0                  = LCCR0_Act,
311         .lccr3                  = LCCR3_PCP,
312         .pxafb_backlight_power  = mainstone_backlight_power,
313 };
314
315 static int mainstone_mci_init(struct device *dev, irqreturn_t (*mstone_detect_int)(int, void *, struct pt_regs *), void *data)
316 {
317         int err;
318
319         /*
320          * setup GPIO for PXA27x MMC controller
321          */
322         pxa_gpio_mode(GPIO32_MMCCLK_MD);
323         pxa_gpio_mode(GPIO112_MMCCMD_MD);
324         pxa_gpio_mode(GPIO92_MMCDAT0_MD);
325         pxa_gpio_mode(GPIO109_MMCDAT1_MD);
326         pxa_gpio_mode(GPIO110_MMCDAT2_MD);
327         pxa_gpio_mode(GPIO111_MMCDAT3_MD);
328
329         /* make sure SD/Memory Stick multiplexer's signals
330          * are routed to MMC controller
331          */
332         MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
333
334         err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
335                              "MMC card detect", data);
336         if (err) {
337                 printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
338                 return -1;
339         }
340
341         return 0;
342 }
343
344 static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
345 {
346         struct pxamci_platform_data* p_d = dev->platform_data;
347
348         if (( 1 << vdd) & p_d->ocr_mask) {
349                 printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
350                 MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
351                 MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
352         } else {
353                 printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
354                 MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
355         }
356 }
357
358 static void mainstone_mci_exit(struct device *dev, void *data)
359 {
360         free_irq(MAINSTONE_MMC_IRQ, data);
361 }
362
363 static struct pxamci_platform_data mainstone_mci_platform_data = {
364         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
365         .init           = mainstone_mci_init,
366         .setpower       = mainstone_mci_setpower,
367         .exit           = mainstone_mci_exit,
368 };
369
370 static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
371 {
372         unsigned long flags;
373
374         local_irq_save(flags);
375         if (mode & IR_SIRMODE) {
376                 MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
377         } else if (mode & IR_FIRMODE) {
378                 MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
379         }
380         if (mode & IR_OFF) {
381                 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
382         } else {
383                 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
384         }
385         local_irq_restore(flags);
386 }
387
388 static struct pxaficp_platform_data mainstone_ficp_platform_data = {
389         .transceiver_cap  = IR_SIRMODE | IR_FIRMODE | IR_OFF,
390         .transceiver_mode = mainstone_irda_transceiver_mode,
391 };
392
393 static struct platform_device *platform_devices[] __initdata = {
394         &smc91x_device,
395         &mst_audio_device,
396         &mst_flash_device[0],
397         &mst_flash_device[1],
398 };
399
400 static int mainstone_ohci_init(struct device *dev)
401 {
402         /* setup Port1 GPIO pin. */
403         pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);  /* USBHPWR1 */
404         pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
405
406         /* Set the Power Control Polarity Low and Power Sense
407            Polarity Low to active low. */
408         UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
409                 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
410
411         return 0;
412 }
413
414 static struct pxaohci_platform_data mainstone_ohci_platform_data = {
415         .port_mode      = PMM_PERPORT_MODE,
416         .init           = mainstone_ohci_init,
417 };
418
419 static void __init mainstone_init(void)
420 {
421         int SW7 = 0;  /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
422
423         mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
424         mst_flash_data[1].width = 4;
425
426         /* Compensate for SW7 which swaps the flash banks */
427         mst_flash_data[SW7].name = "processor-flash";
428         mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
429
430         printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
431                mst_flash_data[0].name);
432
433         /* system bus arbiter setting
434          * - Core_Park
435          * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
436          */
437         ARB_CNTRL = ARB_CORE_PARK | 0x234;
438
439         /*
440          * On Mainstone, we route AC97_SYSCLK via GPIO45 to
441          * the audio daughter card
442          */
443         pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
444
445         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
446
447         /* reading Mainstone's "Virtual Configuration Register"
448            might be handy to select LCD type here */
449         if (0)
450                 set_pxa_fb_info(&toshiba_ltm04c380k);
451         else
452                 set_pxa_fb_info(&toshiba_ltm035a776c);
453
454         pxa_set_mci_info(&mainstone_mci_platform_data);
455         pxa_set_ficp_info(&mainstone_ficp_platform_data);
456         pxa_set_ohci_info(&mainstone_ohci_platform_data);
457 }
458
459
460 static struct map_desc mainstone_io_desc[] __initdata = {
461         {       /* CPLD */
462                 .virtual        =  MST_FPGA_VIRT,
463                 .pfn            = __phys_to_pfn(MST_FPGA_PHYS),
464                 .length         = 0x00100000,
465                 .type           = MT_DEVICE
466         }
467 };
468
469 static void __init mainstone_map_io(void)
470 {
471         pxa_map_io();
472         iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
473
474         /* initialize sleep mode regs (wake-up sources, etc) */
475         PGSR0 = 0x00008800;
476         PGSR1 = 0x00000002;
477         PGSR2 = 0x0001FC00;
478         PGSR3 = 0x00001F81;
479         PWER  = 0xC0000002;
480         PRER  = 0x00000002;
481         PFER  = 0x00000002;
482         /*      for use I SRAM as framebuffer.  */
483         PSLR |= 0xF04;
484         PCFR = 0x66;
485         /*      For Keypad wakeup.      */
486         KPC &=~KPC_ASACT;
487         KPC |=KPC_AS;
488         PKWR  = 0x000FD000;
489         /*      Need read PKWR back after set it.       */
490         PKWR;
491 }
492
493 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
494         /* Maintainer: MontaVista Software Inc. */
495         .phys_io        = 0x40000000,
496         .boot_params    = 0xa0000100,   /* BLOB boot parameter setting */
497         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
498         .map_io         = mainstone_map_io,
499         .init_irq       = mainstone_init_irq,
500         .timer          = &pxa_timer,
501         .init_machine   = mainstone_init,
502 MACHINE_END