756228ddd035de276cb27fef771e55ec5b92f532
[linux-3.10.git] / arch / arm / mach-pnx4008 / time.c
1 /*
2  * arch/arm/mach-pnx4008/time.c
3  *
4  * PNX4008 Timers
5  *
6  * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
7  *
8  * 2005 (c) MontaVista Software, Inc. This file is licensed under
9  * the terms of the GNU General Public License version 2. This program
10  * is licensed "as is" without any warranty of any kind, whether express
11  * or implied.
12  */
13
14 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/sched.h>
20 #include <linux/spinlock.h>
21 #include <linux/module.h>
22 #include <linux/kallsyms.h>
23 #include <linux/time.h>
24 #include <linux/timex.h>
25 #include <linux/irq.h>
26
27 #include <asm/system.h>
28 #include <asm/hardware.h>
29 #include <asm/io.h>
30 #include <asm/leds.h>
31 #include <asm/mach/time.h>
32 #include <asm/errno.h>
33
34 /*! Note: all timers are UPCOUNTING */
35
36 /*!
37  * Returns number of us since last clock interrupt.  Note that interrupts
38  * will have been disabled by do_gettimeoffset()
39  */
40 static unsigned long pnx4008_gettimeoffset(void)
41 {
42         u32 ticks_to_match =
43             __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
44         u32 elapsed = LATCH - ticks_to_match;
45         return (elapsed * (tick_nsec / 1000)) / LATCH;
46 }
47
48 /*!
49  * IRQ handler for the timer
50  */
51 static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id,
52                                            struct pt_regs *regs)
53 {
54         if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
55
56                 write_seqlock(&xtime_lock);
57
58                 do {
59                         timer_tick(regs);
60
61                         /*
62                          * this algorithm takes care of possible delay
63                          * for this interrupt handling longer than a normal
64                          * timer period
65                          */
66                         __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
67                                      HSTIM_MATCH0);
68                         __raw_writel(MATCH0_INT, HSTIM_INT);    /* clear interrupt */
69
70                         /*
71                          * The goal is to keep incrementing HSTIM_MATCH0
72                          * register until HSTIM_MATCH0 indicates time after
73                          * what HSTIM_COUNTER indicates.
74                          */
75                 } while ((signed)
76                          (__raw_readl(HSTIM_MATCH0) -
77                           __raw_readl(HSTIM_COUNTER)) < 0);
78
79                 write_sequnlock(&xtime_lock);
80         }
81
82         return IRQ_HANDLED;
83 }
84
85 static struct irqaction pnx4008_timer_irq = {
86         .name = "PNX4008 Tick Timer",
87         .flags = IRQF_DISABLED | IRQF_TIMER,
88         .handler = pnx4008_timer_interrupt
89 };
90
91 /*!
92  * Set up timer and timer interrupt.
93  */
94 static __init void pnx4008_setup_timer(void)
95 {
96         __raw_writel(RESET_COUNT, MSTIM_CTRL);
97         while (__raw_readl(MSTIM_COUNTER)) ;    /* wait for reset to complete. 100% guarantee event */
98         __raw_writel(0, MSTIM_CTRL);    /* stop the timer */
99         __raw_writel(0, MSTIM_MCTRL);
100
101         __raw_writel(RESET_COUNT, HSTIM_CTRL);
102         while (__raw_readl(HSTIM_COUNTER)) ;    /* wait for reset to complete. 100% guarantee event */
103         __raw_writel(0, HSTIM_CTRL);
104         __raw_writel(0, HSTIM_MCTRL);
105         __raw_writel(0, HSTIM_CCR);
106         __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
107         __raw_writel(LATCH, HSTIM_MATCH0);
108         __raw_writel(MR0_INT, HSTIM_MCTRL);
109
110         setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
111
112         __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL);        /*start timer, stop when JTAG active */
113 }
114
115 /* Timer Clock Control in PM register */
116 #define TIMCLK_CTRL_REG  IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
117 #define WATCHDOG_CLK_EN                   1
118 #define TIMER_CLK_EN                      2     /* HS and MS timers? */
119
120 static u32 timclk_ctrl_reg_save;
121
122 void pnx4008_timer_suspend(void)
123 {
124         timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
125         __raw_writel(0, TIMCLK_CTRL_REG);       /* disable timers */
126 }
127
128 void pnx4008_timer_resume(void)
129 {
130         __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG);    /* enable timers */
131 }
132
133 struct sys_timer pnx4008_timer = {
134         .init = pnx4008_setup_timer,
135         .offset = pnx4008_gettimeoffset,
136         .suspend = pnx4008_timer_suspend,
137         .resume = pnx4008_timer_resume,
138 };
139