2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
45 #include <asm/mach/time.h>
46 #include <asm/smp_twd.h>
47 #include <asm/sched_clock.h>
49 #include <asm/arch_timer.h>
50 #include "omap_hwmod.h"
51 #include "omap_device.h"
52 #include <plat/counter-32k.h>
53 #include <plat/dmtimer.h>
58 #include "powerdomain.h"
60 #define REALTIME_COUNTER_BASE 0x48243200
61 #define INCREMENTER_NUMERATOR_OFFSET 0x10
62 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
63 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
67 static struct omap_dm_timer clkev;
68 static struct clock_event_device clockevent_gpt;
70 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
72 struct clock_event_device *evt = &clockevent_gpt;
74 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
76 evt->event_handler(evt);
80 static struct irqaction omap2_gp_timer_irq = {
82 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
83 .handler = omap2_gp_timer_interrupt,
86 static int omap2_gp_timer_set_next_event(unsigned long cycles,
87 struct clock_event_device *evt)
89 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
90 0xffffffff - cycles, OMAP_TIMER_POSTED);
95 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
96 struct clock_event_device *evt)
100 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
103 case CLOCK_EVT_MODE_PERIODIC:
104 period = clkev.rate / HZ;
106 /* Looks like we need to first set the load value separately */
107 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
108 0xffffffff - period, OMAP_TIMER_POSTED);
109 __omap_dm_timer_load_start(&clkev,
110 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
111 0xffffffff - period, OMAP_TIMER_POSTED);
113 case CLOCK_EVT_MODE_ONESHOT:
115 case CLOCK_EVT_MODE_UNUSED:
116 case CLOCK_EVT_MODE_SHUTDOWN:
117 case CLOCK_EVT_MODE_RESUME:
122 static struct clock_event_device clockevent_gpt = {
123 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
125 .set_next_event = omap2_gp_timer_set_next_event,
126 .set_mode = omap2_gp_timer_set_mode,
129 static struct property device_disabled = {
131 .length = sizeof("disabled"),
135 static struct of_device_id omap_timer_match[] __initdata = {
136 { .compatible = "ti,omap2420-timer", },
137 { .compatible = "ti,omap3430-timer", },
138 { .compatible = "ti,omap4430-timer", },
139 { .compatible = "ti,omap5430-timer", },
140 { .compatible = "ti,am335x-timer", },
141 { .compatible = "ti,am335x-timer-1ms", },
146 * omap_get_timer_dt - get a timer using device-tree
147 * @match - device-tree match structure for matching a device type
148 * @property - optional timer property to match
150 * Helper function to get a timer during early boot using device-tree for use
151 * as kernel system timer. Optionally, the property argument can be used to
152 * select a timer with a specific property. Once a timer is found then mark
153 * the timer node in device-tree as disabled, to prevent the kernel from
154 * registering this timer as a platform device and so no one else can use it.
156 static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
157 const char *property)
159 struct device_node *np;
161 for_each_matching_node(np, match) {
162 if (!of_device_is_available(np))
165 if (property && !of_get_property(np, property, NULL))
168 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
169 of_get_property(np, "ti,timer-dsp", NULL) ||
170 of_get_property(np, "ti,timer-pwm", NULL) ||
171 of_get_property(np, "ti,timer-secure", NULL)))
174 of_add_property(np, &device_disabled);
182 * omap_dmtimer_init - initialisation function when device tree is used
184 * For secure OMAP3 devices, timers with device type "timer-secure" cannot
185 * be used by the kernel as they are reserved. Therefore, to prevent the
186 * kernel registering these devices remove them dynamically from the device
189 static void __init omap_dmtimer_init(void)
191 struct device_node *np;
193 if (!cpu_is_omap34xx())
196 /* If we are a secure device, remove any secure timer nodes */
197 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
198 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
205 * omap_dm_timer_get_errata - get errata flags for a timer
207 * Get the timer errata flags that are specific to the OMAP device being used.
209 static u32 __init omap_dm_timer_get_errata(void)
211 if (cpu_is_omap24xx())
214 return OMAP_TIMER_ERRATA_I103_I767;
217 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
218 const char *fck_source,
219 const char *property,
220 const char **timer_name,
223 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
225 struct device_node *np;
226 struct omap_hwmod *oh;
227 struct resource irq, mem;
231 if (of_have_populated_dt()) {
232 np = omap_get_timer_dt(omap_timer_match, property);
236 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
240 timer->irq = irq_of_parse_and_map(np, 0);
244 timer->io_base = of_iomap(np, 0);
248 if (omap_dm_timer_reserve_systimer(timer->id))
251 sprintf(name, "timer%d", timer->id);
255 oh = omap_hwmod_lookup(oh_name);
259 *timer_name = oh->name;
261 if (!of_have_populated_dt()) {
262 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
266 timer->irq = irq.start;
268 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
273 /* Static mapping, never released */
274 timer->io_base = ioremap(mem.start, mem.end - mem.start);
280 /* After the dmtimer is using hwmod these clocks won't be needed */
281 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
282 if (IS_ERR(timer->fclk))
283 return PTR_ERR(timer->fclk);
285 src = clk_get(NULL, fck_source);
289 if (clk_get_parent(timer->fclk) != src) {
290 r = clk_set_parent(timer->fclk, src);
292 pr_warn("%s: %s cannot set source\n", __func__,
301 omap_hwmod_setup_one(oh_name);
302 omap_hwmod_enable(oh);
303 __omap_dm_timer_init_regs(timer);
306 __omap_dm_timer_enable_posted(timer);
308 /* Check that the intended posted configuration matches the actual */
309 if (posted != timer->posted)
312 timer->rate = clk_get_rate(timer->fclk);
318 static void __init omap2_gp_clockevent_init(int gptimer_id,
319 const char *fck_source,
320 const char *property)
324 clkev.id = gptimer_id;
325 clkev.errata = omap_dm_timer_get_errata();
328 * For clock-event timers we never read the timer counter and
329 * so we are not impacted by errata i103 and i767. Therefore,
330 * we can safely ignore this errata for clock-event timers.
332 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
334 res = omap_dm_timer_init_one(&clkev, fck_source, property,
335 &clockevent_gpt.name, OMAP_TIMER_POSTED);
338 omap2_gp_timer_irq.dev_id = &clkev;
339 setup_irq(clkev.irq, &omap2_gp_timer_irq);
341 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
343 clockevent_gpt.cpumask = cpu_possible_mask;
344 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
345 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
346 3, /* Timer internal resynch latency */
349 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
353 /* Clocksource code */
354 static struct omap_dm_timer clksrc;
355 static bool use_gptimer_clksrc;
360 static cycle_t clocksource_read_cycles(struct clocksource *cs)
362 return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
363 OMAP_TIMER_NONPOSTED);
366 static struct clocksource clocksource_gpt = {
368 .read = clocksource_read_cycles,
369 .mask = CLOCKSOURCE_MASK(32),
370 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
373 static u32 notrace dmtimer_read_sched_clock(void)
376 return __omap_dm_timer_read_counter(&clksrc,
377 OMAP_TIMER_NONPOSTED);
382 static struct of_device_id omap_counter_match[] __initdata = {
383 { .compatible = "ti,omap-counter32k", },
387 /* Setup free-running counter for clocksource */
388 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
391 struct device_node *np = NULL;
392 struct omap_hwmod *oh;
394 const char *oh_name = "counter_32k";
397 * If device-tree is present, then search the DT blob
398 * to see if the 32kHz counter is supported.
400 if (of_have_populated_dt()) {
401 np = omap_get_timer_dt(omap_counter_match, NULL);
405 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
411 * First check hwmod data is available for sync32k counter
413 oh = omap_hwmod_lookup(oh_name);
414 if (!oh || oh->slaves_cnt == 0)
417 omap_hwmod_setup_one(oh_name);
420 vbase = of_iomap(np, 0);
423 vbase = omap_hwmod_get_mpu_rt_va(oh);
427 pr_warn("%s: failed to get counter_32k resource\n", __func__);
431 ret = omap_hwmod_enable(oh);
433 pr_warn("%s: failed to enable counter_32k module (%d)\n",
438 ret = omap_init_clocksource_32k(vbase);
440 pr_warn("%s: failed to initialize counter_32k as a clocksource (%d)\n",
448 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
449 const char *fck_source,
450 const char *property)
454 clksrc.id = gptimer_id;
455 clksrc.errata = omap_dm_timer_get_errata();
457 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
458 &clocksource_gpt.name,
459 OMAP_TIMER_NONPOSTED);
462 __omap_dm_timer_load_start(&clksrc,
463 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
464 OMAP_TIMER_NONPOSTED);
465 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
467 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
468 pr_err("Could not register clocksource %s\n",
469 clocksource_gpt.name);
471 pr_info("OMAP clocksource: %s at %lu Hz\n",
472 clocksource_gpt.name, clksrc.rate);
475 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
477 * The realtime counter also called master counter, is a free-running
478 * counter, which is related to real time. It produces the count used
479 * by the CPU local timer peripherals in the MPU cluster. The timer counts
480 * at a rate of 6.144 MHz. Because the device operates on different clocks
481 * in different power modes, the master counter shifts operation between
482 * clocks, adjusting the increment per clock in hardware accordingly to
483 * maintain a constant count rate.
485 static void __init realtime_counter_init(void)
488 static struct clk *sys_clk;
490 unsigned int reg, num, den;
492 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
494 pr_err("%s: ioremap failed\n", __func__);
497 sys_clk = clk_get(NULL, "sys_clkin");
498 if (IS_ERR(sys_clk)) {
499 pr_err("%s: failed to get system clock handle\n", __func__);
504 rate = clk_get_rate(sys_clk);
505 /* Numerator/denumerator values refer TRM Realtime Counter section */
529 /* Program it for 38.4 MHz */
535 /* Program numerator and denumerator registers */
536 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
537 NUMERATOR_DENUMERATOR_MASK;
539 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
541 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
542 NUMERATOR_DENUMERATOR_MASK;
544 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
549 static inline void __init realtime_counter_init(void)
553 #define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
554 clksrc_nr, clksrc_src, clksrc_prop) \
555 void __init omap##name##_gptimer_timer_init(void) \
557 omap_dmtimer_init(); \
558 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
559 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
563 #define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
564 clksrc_nr, clksrc_src, clksrc_prop) \
565 void __init omap##name##_sync32k_timer_init(void) \
567 omap_dmtimer_init(); \
568 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
569 /* Enable the use of clocksource="gp_timer" kernel parameter */ \
570 if (use_gptimer_clksrc) \
571 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src, \
574 omap2_sync32k_clocksource_init(); \
577 #ifdef CONFIG_ARCH_OMAP2
578 OMAP_SYS_32K_TIMER_INIT(2, 1, "timer_32k_ck", "ti,timer-alwon",
579 2, "timer_sys_ck", NULL);
580 #endif /* CONFIG_ARCH_OMAP2 */
582 #ifdef CONFIG_ARCH_OMAP3
583 OMAP_SYS_32K_TIMER_INIT(3, 1, "timer_32k_ck", "ti,timer-alwon",
584 2, "timer_sys_ck", NULL);
585 OMAP_SYS_32K_TIMER_INIT(3_secure, 12, "secure_32k_fck", "ti,timer-secure",
586 2, "timer_sys_ck", NULL);
587 #endif /* CONFIG_ARCH_OMAP3 */
589 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
590 OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
591 1, "timer_sys_ck", "ti,timer-alwon");
594 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
595 static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
596 2, "sys_clkin_ck", NULL);
599 #ifdef CONFIG_ARCH_OMAP4
600 #ifdef CONFIG_LOCAL_TIMERS
601 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
602 void __init omap4_local_timer_init(void)
604 omap4_sync32k_timer_init();
605 /* Local timers are not supprted on OMAP4430 ES1.0 */
606 if (omap_rev() != OMAP4430_REV_ES1_0) {
609 if (of_have_populated_dt()) {
610 clocksource_of_init();
614 err = twd_local_timer_register(&twd_local_timer);
616 pr_err("twd_local_timer_register failed %d\n", err);
619 #else /* CONFIG_LOCAL_TIMERS */
620 void __init omap4_local_timer_init(void)
622 omap4_sync32k_timer_init();
624 #endif /* CONFIG_LOCAL_TIMERS */
625 #endif /* CONFIG_ARCH_OMAP4 */
627 #ifdef CONFIG_SOC_OMAP5
628 void __init omap5_realtime_timer_init(void)
632 omap4_sync32k_timer_init();
633 realtime_counter_init();
635 err = arch_timer_of_register();
637 pr_err("%s: arch_timer_register failed %d\n", __func__, err);
639 #endif /* CONFIG_SOC_OMAP5 */
642 * omap_timer_init - build and register timer device with an
643 * associated timer hwmod
644 * @oh: timer hwmod pointer to be used to build timer device
645 * @user: parameter that can be passed from calling hwmod API
647 * Called by omap_hwmod_for_each_by_class to register each of the timer
648 * devices present in the system. The number of timer devices is known
649 * by parsing through the hwmod database for a given class name. At the
650 * end of function call memory is allocated for timer device and it is
651 * registered to the framework ready to be proved by the driver.
653 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
657 char *name = "omap_timer";
658 struct dmtimer_platform_data *pdata;
659 struct platform_device *pdev;
660 struct omap_timer_capability_dev_attr *timer_dev_attr;
662 pr_debug("%s: %s\n", __func__, oh->name);
664 /* on secure device, do not register secure timer */
665 timer_dev_attr = oh->dev_attr;
666 if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
667 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
670 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
672 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
677 * Extract the IDs from name field in hwmod database
678 * and use the same for constructing ids' for the
679 * timer devices. In a way, we are avoiding usage of
680 * static variable witin the function to do the same.
681 * CAUTION: We have to be careful and make sure the
682 * name in hwmod database does not change in which case
683 * we might either make corresponding change here or
684 * switch back static variable mechanism.
686 sscanf(oh->name, "timer%2d", &id);
689 pdata->timer_capability = timer_dev_attr->timer_capability;
691 pdata->timer_errata = omap_dm_timer_get_errata();
692 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
694 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata));
697 pr_err("%s: Can't build omap_device for %s: %s.\n",
698 __func__, name, oh->name);
708 * omap2_dm_timer_init - top level regular device initialization
710 * Uses dedicated hwmod api to parse through hwmod database for
711 * given class name and then build and register the timer device.
713 static int __init omap2_dm_timer_init(void)
717 /* If dtb is there, the devices will be created dynamically */
718 if (of_have_populated_dt())
721 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
723 pr_err("%s: device registration failed.\n", __func__);
729 omap_arch_initcall(omap2_dm_timer_init);
732 * omap2_override_clocksource - clocksource override with user configuration
734 * Allows user to override default clocksource, using kernel parameter
735 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
737 * Note that, here we are using same standard kernel parameter "clocksource=",
738 * and not introducing any OMAP specific interface.
740 static int __init omap2_override_clocksource(char *str)
745 * For OMAP architecture, we only have two options
746 * - sync_32k (default)
747 * - gp_timer (sys_clk based)
749 if (!strcmp(str, "gp_timer"))
750 use_gptimer_clksrc = true;
754 early_param("clocksource", omap2_override_clocksource);