Merge tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[linux-3.10.git] / arch / arm / mach-omap2 / sram.c
1 /*
2  *
3  * OMAP SRAM detection and management
4  *
5  * Copyright (C) 2005 Nokia Corporation
6  * Written by Tony Lindgren <tony@atomide.com>
7  *
8  * Copyright (C) 2009-2012 Texas Instruments
9  * Added OMAP4/5 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as
13  * published by the Free Software Foundation.
14  */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20
21 #include <asm/fncpy.h>
22 #include <asm/tlb.h>
23 #include <asm/cacheflush.h>
24
25 #include <asm/mach/map.h>
26
27 #include "soc.h"
28 #include "iomap.h"
29 #include "prm2xxx_3xxx.h"
30 #include "sdrc.h"
31 #include "sram.h"
32
33 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
34 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
35 #ifdef CONFIG_OMAP4_ERRATA_I688
36 #define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
37 #else
38 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
39 #endif
40 #define OMAP5_SRAM_PA           0x40300000
41
42 #define SRAM_BOOTLOADER_SZ      0x00
43
44 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
45 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
46 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
47
48 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
49 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
50 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
51 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
52 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
53
54 #define GP_DEVICE               0x300
55
56 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
57
58 static unsigned long omap_sram_start;
59 static unsigned long omap_sram_skip;
60 static unsigned long omap_sram_size;
61
62 /*
63  * Depending on the target RAMFS firewall setup, the public usable amount of
64  * SRAM varies.  The default accessible size for all device types is 2k. A GP
65  * device allows ARM11 but not other initiators for full size. This
66  * functionality seems ok until some nice security API happens.
67  */
68 static int is_sram_locked(void)
69 {
70         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
71                 /* RAMFW: R/W access to all initiators for all qualifier sets */
72                 if (cpu_is_omap242x()) {
73                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
74                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
75                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
76                 }
77                 if (cpu_is_omap34xx()) {
78                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
79                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
80                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
81                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
82                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
83                 }
84                 return 0;
85         } else
86                 return 1; /* assume locked with no PPA or security driver */
87 }
88
89 /*
90  * The amount of SRAM depends on the core type.
91  * Note that we cannot try to test for SRAM here because writes
92  * to secure SRAM will hang the system. Also the SRAM is not
93  * yet mapped at this point.
94  */
95 static void __init omap_detect_sram(void)
96 {
97         omap_sram_skip = SRAM_BOOTLOADER_SZ;
98         if (is_sram_locked()) {
99                 if (cpu_is_omap34xx()) {
100                         omap_sram_start = OMAP3_SRAM_PUB_PA;
101                         if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
102                             (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
103                                 omap_sram_size = 0x7000; /* 28K */
104                                 omap_sram_skip += SZ_16K;
105                         } else {
106                                 omap_sram_size = 0x8000; /* 32K */
107                         }
108                 } else if (cpu_is_omap44xx()) {
109                         omap_sram_start = OMAP4_SRAM_PUB_PA;
110                         omap_sram_size = 0xa000; /* 40K */
111                 } else if (soc_is_omap54xx()) {
112                         omap_sram_start = OMAP5_SRAM_PA;
113                         omap_sram_size = SZ_128K; /* 128KB */
114                 } else {
115                         omap_sram_start = OMAP2_SRAM_PUB_PA;
116                         omap_sram_size = 0x800; /* 2K */
117                 }
118         } else {
119                 if (soc_is_am33xx()) {
120                         omap_sram_start = AM33XX_SRAM_PA;
121                         omap_sram_size = 0x10000; /* 64K */
122                 } else if (cpu_is_omap34xx()) {
123                         omap_sram_start = OMAP3_SRAM_PA;
124                         omap_sram_size = 0x10000; /* 64K */
125                 } else if (cpu_is_omap44xx()) {
126                         omap_sram_start = OMAP4_SRAM_PA;
127                         omap_sram_size = 0xe000; /* 56K */
128                 } else if (soc_is_omap54xx()) {
129                         omap_sram_start = OMAP5_SRAM_PA;
130                         omap_sram_size = SZ_128K; /* 128KB */
131                 } else {
132                         omap_sram_start = OMAP2_SRAM_PA;
133                         if (cpu_is_omap242x())
134                                 omap_sram_size = 0xa0000; /* 640K */
135                         else if (cpu_is_omap243x())
136                                 omap_sram_size = 0x10000; /* 64K */
137                 }
138         }
139 }
140
141 /*
142  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
143  */
144 static void __init omap2_map_sram(void)
145 {
146         int cached = 1;
147
148 #ifdef CONFIG_OMAP4_ERRATA_I688
149         if (cpu_is_omap44xx()) {
150                 omap_sram_start += PAGE_SIZE;
151                 omap_sram_size -= SZ_16K;
152         }
153 #endif
154         if (cpu_is_omap34xx()) {
155                 /*
156                  * SRAM must be marked as non-cached on OMAP3 since the
157                  * CORE DPLL M2 divider change code (in SRAM) runs with the
158                  * SDRAM controller disabled, and if it is marked cached,
159                  * the ARM may attempt to write cache lines back to SDRAM
160                  * which will cause the system to hang.
161                  */
162                 cached = 0;
163         }
164
165         omap_map_sram(omap_sram_start, omap_sram_size,
166                         omap_sram_skip, cached);
167 }
168
169 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
170                               u32 base_cs, u32 force_unlock);
171
172 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
173                    u32 base_cs, u32 force_unlock)
174 {
175         BUG_ON(!_omap2_sram_ddr_init);
176         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
177                              base_cs, force_unlock);
178 }
179
180 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
181                                           u32 mem_type);
182
183 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
184 {
185         BUG_ON(!_omap2_sram_reprogram_sdrc);
186         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
187 }
188
189 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
190
191 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
192 {
193         BUG_ON(!_omap2_set_prcm);
194         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
195 }
196
197 #ifdef CONFIG_SOC_OMAP2420
198 static int __init omap242x_sram_init(void)
199 {
200         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
201                                         omap242x_sram_ddr_init_sz);
202
203         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
204                                             omap242x_sram_reprogram_sdrc_sz);
205
206         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
207                                          omap242x_sram_set_prcm_sz);
208
209         return 0;
210 }
211 #else
212 static inline int omap242x_sram_init(void)
213 {
214         return 0;
215 }
216 #endif
217
218 #ifdef CONFIG_SOC_OMAP2430
219 static int __init omap243x_sram_init(void)
220 {
221         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
222                                         omap243x_sram_ddr_init_sz);
223
224         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
225                                             omap243x_sram_reprogram_sdrc_sz);
226
227         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
228                                          omap243x_sram_set_prcm_sz);
229
230         return 0;
231 }
232 #else
233 static inline int omap243x_sram_init(void)
234 {
235         return 0;
236 }
237 #endif
238
239 #ifdef CONFIG_ARCH_OMAP3
240
241 static u32 (*_omap3_sram_configure_core_dpll)(
242                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
243                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
244                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
245                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
246                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
247
248 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
249                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
250                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
251                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
252                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
253 {
254         BUG_ON(!_omap3_sram_configure_core_dpll);
255         return _omap3_sram_configure_core_dpll(
256                         m2, unlock_dll, f, inc,
257                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
258                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
259                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
260                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
261 }
262
263 void omap3_sram_restore_context(void)
264 {
265         omap_sram_reset();
266
267         _omap3_sram_configure_core_dpll =
268                 omap_sram_push(omap3_sram_configure_core_dpll,
269                                omap3_sram_configure_core_dpll_sz);
270         omap_push_sram_idle();
271 }
272
273 static inline int omap34xx_sram_init(void)
274 {
275         omap3_sram_restore_context();
276         return 0;
277 }
278 #else
279 static inline int omap34xx_sram_init(void)
280 {
281         return 0;
282 }
283 #endif /* CONFIG_ARCH_OMAP3 */
284
285 static inline int am33xx_sram_init(void)
286 {
287         return 0;
288 }
289
290 int __init omap_sram_init(void)
291 {
292         omap_detect_sram();
293         omap2_map_sram();
294
295         if (cpu_is_omap242x())
296                 omap242x_sram_init();
297         else if (cpu_is_omap2430())
298                 omap243x_sram_init();
299         else if (soc_is_am33xx())
300                 am33xx_sram_init();
301         else if (cpu_is_omap34xx())
302                 omap34xx_sram_init();
303
304         return 0;
305 }