Merge tag 'v3.7-rc7' into next/cleanup
[linux-3.10.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2  * Hardware modules present on the OMAP44xx chips
3  *
4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley
8  * Benoit Cousson
9  *
10  * This file is automatically generated from the OMAP hardware databases.
11  * We respectfully ask that any modifications to this file be coordinated
12  * with the public linux-omap@vger.kernel.org mailing list and the
13  * authors above to ensure that the autogeneration scripts are kept
14  * up-to-date with the file contents.
15  *
16  * This program is free software; you can redistribute it and/or modify
17  * it under the terms of the GNU General Public License version 2 as
18  * published by the Free Software Foundation.
19  */
20
21 #include <linux/io.h>
22 #include <linux/platform_data/gpio-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
25
26 #include <plat-omap/dma-omap.h>
27
28 #include <linux/platform_data/omap_ocp2scp.h>
29 #include <linux/platform_data/spi-omap2-mcspi.h>
30 #include <linux/platform_data/asoc-ti-mcbsp.h>
31 #include <plat/dmtimer.h>
32 #include <plat/iommu.h>
33
34 #include "omap_hwmod.h"
35 #include "omap_hwmod_common_data.h"
36 #include "cm1_44xx.h"
37 #include "cm2_44xx.h"
38 #include "prm44xx.h"
39 #include "prm-regbits-44xx.h"
40 #include "i2c.h"
41 #include "mmc.h"
42 #include "wd_timer.h"
43
44 /* Base offset for all OMAP4 interrupts external to MPUSS */
45 #define OMAP44XX_IRQ_GIC_START  32
46
47 /* Base offset for all OMAP4 dma requests */
48 #define OMAP44XX_DMA_REQ_START  1
49
50 /*
51  * IP blocks
52  */
53
54 /*
55  * 'c2c_target_fw' class
56  * instance(s): c2c_target_fw
57  */
58 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class = {
59         .name   = "c2c_target_fw",
60 };
61
62 /* c2c_target_fw */
63 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod = {
64         .name           = "c2c_target_fw",
65         .class          = &omap44xx_c2c_target_fw_hwmod_class,
66         .clkdm_name     = "d2d_clkdm",
67         .prcm = {
68                 .omap4 = {
69                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET,
70                         .context_offs = OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET,
71                 },
72         },
73 };
74
75 /*
76  * 'dmm' class
77  * instance(s): dmm
78  */
79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
80         .name   = "dmm",
81 };
82
83 /* dmm */
84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
86         { .irq = -1 }
87 };
88
89 static struct omap_hwmod omap44xx_dmm_hwmod = {
90         .name           = "dmm",
91         .class          = &omap44xx_dmm_hwmod_class,
92         .clkdm_name     = "l3_emif_clkdm",
93         .mpu_irqs       = omap44xx_dmm_irqs,
94         .prcm = {
95                 .omap4 = {
96                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
97                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
98                 },
99         },
100 };
101
102 /*
103  * 'emif_fw' class
104  * instance(s): emif_fw
105  */
106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
107         .name   = "emif_fw",
108 };
109
110 /* emif_fw */
111 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
112         .name           = "emif_fw",
113         .class          = &omap44xx_emif_fw_hwmod_class,
114         .clkdm_name     = "l3_emif_clkdm",
115         .prcm = {
116                 .omap4 = {
117                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
118                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
119                 },
120         },
121 };
122
123 /*
124  * 'l3' class
125  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
126  */
127 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
128         .name   = "l3",
129 };
130
131 /* l3_instr */
132 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
133         .name           = "l3_instr",
134         .class          = &omap44xx_l3_hwmod_class,
135         .clkdm_name     = "l3_instr_clkdm",
136         .prcm = {
137                 .omap4 = {
138                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
139                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
140                         .modulemode   = MODULEMODE_HWCTRL,
141                 },
142         },
143 };
144
145 /* l3_main_1 */
146 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
147         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
148         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
149         { .irq = -1 }
150 };
151
152 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
153         .name           = "l3_main_1",
154         .class          = &omap44xx_l3_hwmod_class,
155         .clkdm_name     = "l3_1_clkdm",
156         .mpu_irqs       = omap44xx_l3_main_1_irqs,
157         .prcm = {
158                 .omap4 = {
159                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
160                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
161                 },
162         },
163 };
164
165 /* l3_main_2 */
166 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
167         .name           = "l3_main_2",
168         .class          = &omap44xx_l3_hwmod_class,
169         .clkdm_name     = "l3_2_clkdm",
170         .prcm = {
171                 .omap4 = {
172                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
173                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
174                 },
175         },
176 };
177
178 /* l3_main_3 */
179 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
180         .name           = "l3_main_3",
181         .class          = &omap44xx_l3_hwmod_class,
182         .clkdm_name     = "l3_instr_clkdm",
183         .prcm = {
184                 .omap4 = {
185                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
186                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
187                         .modulemode   = MODULEMODE_HWCTRL,
188                 },
189         },
190 };
191
192 /*
193  * 'l4' class
194  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
195  */
196 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
197         .name   = "l4",
198 };
199
200 /* l4_abe */
201 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
202         .name           = "l4_abe",
203         .class          = &omap44xx_l4_hwmod_class,
204         .clkdm_name     = "abe_clkdm",
205         .prcm = {
206                 .omap4 = {
207                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
208                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
209                         .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
210                         .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
211                 },
212         },
213 };
214
215 /* l4_cfg */
216 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
217         .name           = "l4_cfg",
218         .class          = &omap44xx_l4_hwmod_class,
219         .clkdm_name     = "l4_cfg_clkdm",
220         .prcm = {
221                 .omap4 = {
222                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
223                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
224                 },
225         },
226 };
227
228 /* l4_per */
229 static struct omap_hwmod omap44xx_l4_per_hwmod = {
230         .name           = "l4_per",
231         .class          = &omap44xx_l4_hwmod_class,
232         .clkdm_name     = "l4_per_clkdm",
233         .prcm = {
234                 .omap4 = {
235                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
236                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
237                 },
238         },
239 };
240
241 /* l4_wkup */
242 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
243         .name           = "l4_wkup",
244         .class          = &omap44xx_l4_hwmod_class,
245         .clkdm_name     = "l4_wkup_clkdm",
246         .prcm = {
247                 .omap4 = {
248                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
249                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
250                 },
251         },
252 };
253
254 /*
255  * 'mpu_bus' class
256  * instance(s): mpu_private
257  */
258 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
259         .name   = "mpu_bus",
260 };
261
262 /* mpu_private */
263 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
264         .name           = "mpu_private",
265         .class          = &omap44xx_mpu_bus_hwmod_class,
266         .clkdm_name     = "mpuss_clkdm",
267         .prcm = {
268                 .omap4 = {
269                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
270                 },
271         },
272 };
273
274 /*
275  * 'ocp_wp_noc' class
276  * instance(s): ocp_wp_noc
277  */
278 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
279         .name   = "ocp_wp_noc",
280 };
281
282 /* ocp_wp_noc */
283 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
284         .name           = "ocp_wp_noc",
285         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
286         .clkdm_name     = "l3_instr_clkdm",
287         .prcm = {
288                 .omap4 = {
289                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
290                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
291                         .modulemode   = MODULEMODE_HWCTRL,
292                 },
293         },
294 };
295
296 /*
297  * Modules omap_hwmod structures
298  *
299  * The following IPs are excluded for the moment because:
300  * - They do not need an explicit SW control using omap_hwmod API.
301  * - They still need to be validated with the driver
302  *   properly adapted to omap_hwmod / omap_device
303  *
304  * usim
305  */
306
307 /*
308  * 'aess' class
309  * audio engine sub system
310  */
311
312 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
313         .rev_offs       = 0x0000,
314         .sysc_offs      = 0x0010,
315         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
317                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
318                            MSTANDBY_SMART_WKUP),
319         .sysc_fields    = &omap_hwmod_sysc_type2,
320 };
321
322 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
323         .name   = "aess",
324         .sysc   = &omap44xx_aess_sysc,
325 };
326
327 /* aess */
328 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
329         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
330         { .irq = -1 }
331 };
332
333 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
334         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
335         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
336         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
337         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
338         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
339         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
340         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
341         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
342         { .dma_req = -1 }
343 };
344
345 static struct omap_hwmod omap44xx_aess_hwmod = {
346         .name           = "aess",
347         .class          = &omap44xx_aess_hwmod_class,
348         .clkdm_name     = "abe_clkdm",
349         .mpu_irqs       = omap44xx_aess_irqs,
350         .sdma_reqs      = omap44xx_aess_sdma_reqs,
351         .main_clk       = "aess_fck",
352         .prcm = {
353                 .omap4 = {
354                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
355                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
356                         .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
357                         .modulemode   = MODULEMODE_SWCTRL,
358                 },
359         },
360 };
361
362 /*
363  * 'c2c' class
364  * chip 2 chip interface used to plug the ape soc (omap) with an external modem
365  * soc
366  */
367
368 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
369         .name   = "c2c",
370 };
371
372 /* c2c */
373 static struct omap_hwmod_irq_info omap44xx_c2c_irqs[] = {
374         { .irq = 88 + OMAP44XX_IRQ_GIC_START },
375         { .irq = -1 }
376 };
377
378 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs[] = {
379         { .dma_req = 68 + OMAP44XX_DMA_REQ_START },
380         { .dma_req = -1 }
381 };
382
383 static struct omap_hwmod omap44xx_c2c_hwmod = {
384         .name           = "c2c",
385         .class          = &omap44xx_c2c_hwmod_class,
386         .clkdm_name     = "d2d_clkdm",
387         .mpu_irqs       = omap44xx_c2c_irqs,
388         .sdma_reqs      = omap44xx_c2c_sdma_reqs,
389         .prcm = {
390                 .omap4 = {
391                         .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
392                         .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
393                 },
394         },
395 };
396
397 /*
398  * 'counter' class
399  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
400  */
401
402 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
403         .rev_offs       = 0x0000,
404         .sysc_offs      = 0x0004,
405         .sysc_flags     = SYSC_HAS_SIDLEMODE,
406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
407         .sysc_fields    = &omap_hwmod_sysc_type1,
408 };
409
410 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
411         .name   = "counter",
412         .sysc   = &omap44xx_counter_sysc,
413 };
414
415 /* counter_32k */
416 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
417         .name           = "counter_32k",
418         .class          = &omap44xx_counter_hwmod_class,
419         .clkdm_name     = "l4_wkup_clkdm",
420         .flags          = HWMOD_SWSUP_SIDLE,
421         .main_clk       = "sys_32k_ck",
422         .prcm = {
423                 .omap4 = {
424                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
425                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
426                 },
427         },
428 };
429
430 /*
431  * 'ctrl_module' class
432  * attila core control module + core pad control module + wkup pad control
433  * module + attila wkup control module
434  */
435
436 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
437         .rev_offs       = 0x0000,
438         .sysc_offs      = 0x0010,
439         .sysc_flags     = SYSC_HAS_SIDLEMODE,
440         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
441                            SIDLE_SMART_WKUP),
442         .sysc_fields    = &omap_hwmod_sysc_type2,
443 };
444
445 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
446         .name   = "ctrl_module",
447         .sysc   = &omap44xx_ctrl_module_sysc,
448 };
449
450 /* ctrl_module_core */
451 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs[] = {
452         { .irq = 8 + OMAP44XX_IRQ_GIC_START },
453         { .irq = -1 }
454 };
455
456 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
457         .name           = "ctrl_module_core",
458         .class          = &omap44xx_ctrl_module_hwmod_class,
459         .clkdm_name     = "l4_cfg_clkdm",
460         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
461         .prcm = {
462                 .omap4 = {
463                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
464                 },
465         },
466 };
467
468 /* ctrl_module_pad_core */
469 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
470         .name           = "ctrl_module_pad_core",
471         .class          = &omap44xx_ctrl_module_hwmod_class,
472         .clkdm_name     = "l4_cfg_clkdm",
473         .prcm = {
474                 .omap4 = {
475                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
476                 },
477         },
478 };
479
480 /* ctrl_module_wkup */
481 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
482         .name           = "ctrl_module_wkup",
483         .class          = &omap44xx_ctrl_module_hwmod_class,
484         .clkdm_name     = "l4_wkup_clkdm",
485         .prcm = {
486                 .omap4 = {
487                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
488                 },
489         },
490 };
491
492 /* ctrl_module_pad_wkup */
493 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
494         .name           = "ctrl_module_pad_wkup",
495         .class          = &omap44xx_ctrl_module_hwmod_class,
496         .clkdm_name     = "l4_wkup_clkdm",
497         .prcm = {
498                 .omap4 = {
499                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
500                 },
501         },
502 };
503
504 /*
505  * 'debugss' class
506  * debug and emulation sub system
507  */
508
509 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
510         .name   = "debugss",
511 };
512
513 /* debugss */
514 static struct omap_hwmod omap44xx_debugss_hwmod = {
515         .name           = "debugss",
516         .class          = &omap44xx_debugss_hwmod_class,
517         .clkdm_name     = "emu_sys_clkdm",
518         .main_clk       = "trace_clk_div_ck",
519         .prcm = {
520                 .omap4 = {
521                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
522                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
523                 },
524         },
525 };
526
527 /*
528  * 'dma' class
529  * dma controller for data exchange between memory to memory (i.e. internal or
530  * external memory) and gp peripherals to memory or memory to gp peripherals
531  */
532
533 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
534         .rev_offs       = 0x0000,
535         .sysc_offs      = 0x002c,
536         .syss_offs      = 0x0028,
537         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
538                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
539                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
540                            SYSS_HAS_RESET_STATUS),
541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
542                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
543         .sysc_fields    = &omap_hwmod_sysc_type1,
544 };
545
546 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
547         .name   = "dma",
548         .sysc   = &omap44xx_dma_sysc,
549 };
550
551 /* dma dev_attr */
552 static struct omap_dma_dev_attr dma_dev_attr = {
553         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
554                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
555         .lch_count      = 32,
556 };
557
558 /* dma_system */
559 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
560         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
561         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
562         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
563         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
564         { .irq = -1 }
565 };
566
567 static struct omap_hwmod omap44xx_dma_system_hwmod = {
568         .name           = "dma_system",
569         .class          = &omap44xx_dma_hwmod_class,
570         .clkdm_name     = "l3_dma_clkdm",
571         .mpu_irqs       = omap44xx_dma_system_irqs,
572         .main_clk       = "l3_div_ck",
573         .prcm = {
574                 .omap4 = {
575                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
576                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
577                 },
578         },
579         .dev_attr       = &dma_dev_attr,
580 };
581
582 /*
583  * 'dmic' class
584  * digital microphone controller
585  */
586
587 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
588         .rev_offs       = 0x0000,
589         .sysc_offs      = 0x0010,
590         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
591                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
592         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
593                            SIDLE_SMART_WKUP),
594         .sysc_fields    = &omap_hwmod_sysc_type2,
595 };
596
597 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
598         .name   = "dmic",
599         .sysc   = &omap44xx_dmic_sysc,
600 };
601
602 /* dmic */
603 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
604         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
605         { .irq = -1 }
606 };
607
608 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
609         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
610         { .dma_req = -1 }
611 };
612
613 static struct omap_hwmod omap44xx_dmic_hwmod = {
614         .name           = "dmic",
615         .class          = &omap44xx_dmic_hwmod_class,
616         .clkdm_name     = "abe_clkdm",
617         .mpu_irqs       = omap44xx_dmic_irqs,
618         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
619         .main_clk       = "dmic_fck",
620         .prcm = {
621                 .omap4 = {
622                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
623                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
624                         .modulemode   = MODULEMODE_SWCTRL,
625                 },
626         },
627 };
628
629 /*
630  * 'dsp' class
631  * dsp sub-system
632  */
633
634 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
635         .name   = "dsp",
636 };
637
638 /* dsp */
639 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
640         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
641         { .irq = -1 }
642 };
643
644 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
645         { .name = "dsp", .rst_shift = 0 },
646 };
647
648 static struct omap_hwmod omap44xx_dsp_hwmod = {
649         .name           = "dsp",
650         .class          = &omap44xx_dsp_hwmod_class,
651         .clkdm_name     = "tesla_clkdm",
652         .mpu_irqs       = omap44xx_dsp_irqs,
653         .rst_lines      = omap44xx_dsp_resets,
654         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
655         .main_clk       = "dsp_fck",
656         .prcm = {
657                 .omap4 = {
658                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
659                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
660                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
661                         .modulemode   = MODULEMODE_HWCTRL,
662                 },
663         },
664 };
665
666 /*
667  * 'dss' class
668  * display sub-system
669  */
670
671 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
672         .rev_offs       = 0x0000,
673         .syss_offs      = 0x0014,
674         .sysc_flags     = SYSS_HAS_RESET_STATUS,
675 };
676
677 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
678         .name   = "dss",
679         .sysc   = &omap44xx_dss_sysc,
680         .reset  = omap_dss_reset,
681 };
682
683 /* dss */
684 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
685         { .role = "sys_clk", .clk = "dss_sys_clk" },
686         { .role = "tv_clk", .clk = "dss_tv_clk" },
687         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
688 };
689
690 static struct omap_hwmod omap44xx_dss_hwmod = {
691         .name           = "dss_core",
692         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
693         .class          = &omap44xx_dss_hwmod_class,
694         .clkdm_name     = "l3_dss_clkdm",
695         .main_clk       = "dss_dss_clk",
696         .prcm = {
697                 .omap4 = {
698                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
699                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
700                 },
701         },
702         .opt_clks       = dss_opt_clks,
703         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
704 };
705
706 /*
707  * 'dispc' class
708  * display controller
709  */
710
711 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
712         .rev_offs       = 0x0000,
713         .sysc_offs      = 0x0010,
714         .syss_offs      = 0x0014,
715         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
716                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
717                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
718                            SYSS_HAS_RESET_STATUS),
719         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
720                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
721         .sysc_fields    = &omap_hwmod_sysc_type1,
722 };
723
724 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
725         .name   = "dispc",
726         .sysc   = &omap44xx_dispc_sysc,
727 };
728
729 /* dss_dispc */
730 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
731         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
732         { .irq = -1 }
733 };
734
735 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
736         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
737         { .dma_req = -1 }
738 };
739
740 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
741         .manager_count          = 3,
742         .has_framedonetv_irq    = 1
743 };
744
745 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
746         .name           = "dss_dispc",
747         .class          = &omap44xx_dispc_hwmod_class,
748         .clkdm_name     = "l3_dss_clkdm",
749         .mpu_irqs       = omap44xx_dss_dispc_irqs,
750         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
751         .main_clk       = "dss_dss_clk",
752         .prcm = {
753                 .omap4 = {
754                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
755                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
756                 },
757         },
758         .dev_attr       = &omap44xx_dss_dispc_dev_attr
759 };
760
761 /*
762  * 'dsi' class
763  * display serial interface controller
764  */
765
766 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
767         .rev_offs       = 0x0000,
768         .sysc_offs      = 0x0010,
769         .syss_offs      = 0x0014,
770         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
771                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
772                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
774         .sysc_fields    = &omap_hwmod_sysc_type1,
775 };
776
777 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
778         .name   = "dsi",
779         .sysc   = &omap44xx_dsi_sysc,
780 };
781
782 /* dss_dsi1 */
783 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
784         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
785         { .irq = -1 }
786 };
787
788 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
789         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
790         { .dma_req = -1 }
791 };
792
793 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
794         { .role = "sys_clk", .clk = "dss_sys_clk" },
795 };
796
797 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
798         .name           = "dss_dsi1",
799         .class          = &omap44xx_dsi_hwmod_class,
800         .clkdm_name     = "l3_dss_clkdm",
801         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
802         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
803         .main_clk       = "dss_dss_clk",
804         .prcm = {
805                 .omap4 = {
806                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
807                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
808                 },
809         },
810         .opt_clks       = dss_dsi1_opt_clks,
811         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
812 };
813
814 /* dss_dsi2 */
815 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
816         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
817         { .irq = -1 }
818 };
819
820 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
821         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
822         { .dma_req = -1 }
823 };
824
825 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
826         { .role = "sys_clk", .clk = "dss_sys_clk" },
827 };
828
829 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
830         .name           = "dss_dsi2",
831         .class          = &omap44xx_dsi_hwmod_class,
832         .clkdm_name     = "l3_dss_clkdm",
833         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
834         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
835         .main_clk       = "dss_dss_clk",
836         .prcm = {
837                 .omap4 = {
838                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
839                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
840                 },
841         },
842         .opt_clks       = dss_dsi2_opt_clks,
843         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
844 };
845
846 /*
847  * 'hdmi' class
848  * hdmi controller
849  */
850
851 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
852         .rev_offs       = 0x0000,
853         .sysc_offs      = 0x0010,
854         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
855                            SYSC_HAS_SOFTRESET),
856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
857                            SIDLE_SMART_WKUP),
858         .sysc_fields    = &omap_hwmod_sysc_type2,
859 };
860
861 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
862         .name   = "hdmi",
863         .sysc   = &omap44xx_hdmi_sysc,
864 };
865
866 /* dss_hdmi */
867 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
868         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
869         { .irq = -1 }
870 };
871
872 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
873         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
874         { .dma_req = -1 }
875 };
876
877 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
878         { .role = "sys_clk", .clk = "dss_sys_clk" },
879 };
880
881 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
882         .name           = "dss_hdmi",
883         .class          = &omap44xx_hdmi_hwmod_class,
884         .clkdm_name     = "l3_dss_clkdm",
885         /*
886          * HDMI audio requires to use no-idle mode. Hence,
887          * set idle mode by software.
888          */
889         .flags          = HWMOD_SWSUP_SIDLE,
890         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
891         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
892         .main_clk       = "dss_48mhz_clk",
893         .prcm = {
894                 .omap4 = {
895                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
896                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
897                 },
898         },
899         .opt_clks       = dss_hdmi_opt_clks,
900         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
901 };
902
903 /*
904  * 'rfbi' class
905  * remote frame buffer interface
906  */
907
908 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
909         .rev_offs       = 0x0000,
910         .sysc_offs      = 0x0010,
911         .syss_offs      = 0x0014,
912         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
913                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
914         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
915         .sysc_fields    = &omap_hwmod_sysc_type1,
916 };
917
918 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
919         .name   = "rfbi",
920         .sysc   = &omap44xx_rfbi_sysc,
921 };
922
923 /* dss_rfbi */
924 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
925         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
926         { .dma_req = -1 }
927 };
928
929 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
930         { .role = "ick", .clk = "dss_fck" },
931 };
932
933 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
934         .name           = "dss_rfbi",
935         .class          = &omap44xx_rfbi_hwmod_class,
936         .clkdm_name     = "l3_dss_clkdm",
937         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
938         .main_clk       = "dss_dss_clk",
939         .prcm = {
940                 .omap4 = {
941                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
942                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
943                 },
944         },
945         .opt_clks       = dss_rfbi_opt_clks,
946         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
947 };
948
949 /*
950  * 'venc' class
951  * video encoder
952  */
953
954 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
955         .name   = "venc",
956 };
957
958 /* dss_venc */
959 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
960         .name           = "dss_venc",
961         .class          = &omap44xx_venc_hwmod_class,
962         .clkdm_name     = "l3_dss_clkdm",
963         .main_clk       = "dss_tv_clk",
964         .prcm = {
965                 .omap4 = {
966                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
967                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
968                 },
969         },
970 };
971
972 /*
973  * 'elm' class
974  * bch error location module
975  */
976
977 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
978         .rev_offs       = 0x0000,
979         .sysc_offs      = 0x0010,
980         .syss_offs      = 0x0014,
981         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
982                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
983                            SYSS_HAS_RESET_STATUS),
984         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
985         .sysc_fields    = &omap_hwmod_sysc_type1,
986 };
987
988 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
989         .name   = "elm",
990         .sysc   = &omap44xx_elm_sysc,
991 };
992
993 /* elm */
994 static struct omap_hwmod_irq_info omap44xx_elm_irqs[] = {
995         { .irq = 4 + OMAP44XX_IRQ_GIC_START },
996         { .irq = -1 }
997 };
998
999 static struct omap_hwmod omap44xx_elm_hwmod = {
1000         .name           = "elm",
1001         .class          = &omap44xx_elm_hwmod_class,
1002         .clkdm_name     = "l4_per_clkdm",
1003         .mpu_irqs       = omap44xx_elm_irqs,
1004         .prcm = {
1005                 .omap4 = {
1006                         .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
1007                         .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
1008                 },
1009         },
1010 };
1011
1012 /*
1013  * 'emif' class
1014  * external memory interface no1
1015  */
1016
1017 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
1018         .rev_offs       = 0x0000,
1019 };
1020
1021 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
1022         .name   = "emif",
1023         .sysc   = &omap44xx_emif_sysc,
1024 };
1025
1026 /* emif1 */
1027 static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = {
1028         { .irq = 110 + OMAP44XX_IRQ_GIC_START },
1029         { .irq = -1 }
1030 };
1031
1032 static struct omap_hwmod omap44xx_emif1_hwmod = {
1033         .name           = "emif1",
1034         .class          = &omap44xx_emif_hwmod_class,
1035         .clkdm_name     = "l3_emif_clkdm",
1036         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1037         .mpu_irqs       = omap44xx_emif1_irqs,
1038         .main_clk       = "ddrphy_ck",
1039         .prcm = {
1040                 .omap4 = {
1041                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
1042                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
1043                         .modulemode   = MODULEMODE_HWCTRL,
1044                 },
1045         },
1046 };
1047
1048 /* emif2 */
1049 static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = {
1050         { .irq = 111 + OMAP44XX_IRQ_GIC_START },
1051         { .irq = -1 }
1052 };
1053
1054 static struct omap_hwmod omap44xx_emif2_hwmod = {
1055         .name           = "emif2",
1056         .class          = &omap44xx_emif_hwmod_class,
1057         .clkdm_name     = "l3_emif_clkdm",
1058         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1059         .mpu_irqs       = omap44xx_emif2_irqs,
1060         .main_clk       = "ddrphy_ck",
1061         .prcm = {
1062                 .omap4 = {
1063                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
1064                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
1065                         .modulemode   = MODULEMODE_HWCTRL,
1066                 },
1067         },
1068 };
1069
1070 /*
1071  * 'fdif' class
1072  * face detection hw accelerator module
1073  */
1074
1075 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1076         .rev_offs       = 0x0000,
1077         .sysc_offs      = 0x0010,
1078         /*
1079          * FDIF needs 100 OCP clk cycles delay after a softreset before
1080          * accessing sysconfig again.
1081          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1082          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1083          *
1084          * TODO: Indicate errata when available.
1085          */
1086         .srst_udelay    = 2,
1087         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1088                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1089         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1090                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1091         .sysc_fields    = &omap_hwmod_sysc_type2,
1092 };
1093
1094 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1095         .name   = "fdif",
1096         .sysc   = &omap44xx_fdif_sysc,
1097 };
1098
1099 /* fdif */
1100 static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = {
1101         { .irq = 69 + OMAP44XX_IRQ_GIC_START },
1102         { .irq = -1 }
1103 };
1104
1105 static struct omap_hwmod omap44xx_fdif_hwmod = {
1106         .name           = "fdif",
1107         .class          = &omap44xx_fdif_hwmod_class,
1108         .clkdm_name     = "iss_clkdm",
1109         .mpu_irqs       = omap44xx_fdif_irqs,
1110         .main_clk       = "fdif_fck",
1111         .prcm = {
1112                 .omap4 = {
1113                         .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1114                         .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1115                         .modulemode   = MODULEMODE_SWCTRL,
1116                 },
1117         },
1118 };
1119
1120 /*
1121  * 'gpio' class
1122  * general purpose io module
1123  */
1124
1125 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1126         .rev_offs       = 0x0000,
1127         .sysc_offs      = 0x0010,
1128         .syss_offs      = 0x0114,
1129         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1130                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1131                            SYSS_HAS_RESET_STATUS),
1132         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1133                            SIDLE_SMART_WKUP),
1134         .sysc_fields    = &omap_hwmod_sysc_type1,
1135 };
1136
1137 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1138         .name   = "gpio",
1139         .sysc   = &omap44xx_gpio_sysc,
1140         .rev    = 2,
1141 };
1142
1143 /* gpio dev_attr */
1144 static struct omap_gpio_dev_attr gpio_dev_attr = {
1145         .bank_width     = 32,
1146         .dbck_flag      = true,
1147 };
1148
1149 /* gpio1 */
1150 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1151         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1152         { .irq = -1 }
1153 };
1154
1155 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1156         { .role = "dbclk", .clk = "gpio1_dbclk" },
1157 };
1158
1159 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1160         .name           = "gpio1",
1161         .class          = &omap44xx_gpio_hwmod_class,
1162         .clkdm_name     = "l4_wkup_clkdm",
1163         .mpu_irqs       = omap44xx_gpio1_irqs,
1164         .main_clk       = "gpio1_ick",
1165         .prcm = {
1166                 .omap4 = {
1167                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1168                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1169                         .modulemode   = MODULEMODE_HWCTRL,
1170                 },
1171         },
1172         .opt_clks       = gpio1_opt_clks,
1173         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1174         .dev_attr       = &gpio_dev_attr,
1175 };
1176
1177 /* gpio2 */
1178 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1179         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1180         { .irq = -1 }
1181 };
1182
1183 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1184         { .role = "dbclk", .clk = "gpio2_dbclk" },
1185 };
1186
1187 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1188         .name           = "gpio2",
1189         .class          = &omap44xx_gpio_hwmod_class,
1190         .clkdm_name     = "l4_per_clkdm",
1191         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1192         .mpu_irqs       = omap44xx_gpio2_irqs,
1193         .main_clk       = "gpio2_ick",
1194         .prcm = {
1195                 .omap4 = {
1196                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1197                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1198                         .modulemode   = MODULEMODE_HWCTRL,
1199                 },
1200         },
1201         .opt_clks       = gpio2_opt_clks,
1202         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1203         .dev_attr       = &gpio_dev_attr,
1204 };
1205
1206 /* gpio3 */
1207 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1208         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1209         { .irq = -1 }
1210 };
1211
1212 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1213         { .role = "dbclk", .clk = "gpio3_dbclk" },
1214 };
1215
1216 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1217         .name           = "gpio3",
1218         .class          = &omap44xx_gpio_hwmod_class,
1219         .clkdm_name     = "l4_per_clkdm",
1220         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1221         .mpu_irqs       = omap44xx_gpio3_irqs,
1222         .main_clk       = "gpio3_ick",
1223         .prcm = {
1224                 .omap4 = {
1225                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1226                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1227                         .modulemode   = MODULEMODE_HWCTRL,
1228                 },
1229         },
1230         .opt_clks       = gpio3_opt_clks,
1231         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1232         .dev_attr       = &gpio_dev_attr,
1233 };
1234
1235 /* gpio4 */
1236 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1237         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1238         { .irq = -1 }
1239 };
1240
1241 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1242         { .role = "dbclk", .clk = "gpio4_dbclk" },
1243 };
1244
1245 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1246         .name           = "gpio4",
1247         .class          = &omap44xx_gpio_hwmod_class,
1248         .clkdm_name     = "l4_per_clkdm",
1249         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1250         .mpu_irqs       = omap44xx_gpio4_irqs,
1251         .main_clk       = "gpio4_ick",
1252         .prcm = {
1253                 .omap4 = {
1254                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1255                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1256                         .modulemode   = MODULEMODE_HWCTRL,
1257                 },
1258         },
1259         .opt_clks       = gpio4_opt_clks,
1260         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1261         .dev_attr       = &gpio_dev_attr,
1262 };
1263
1264 /* gpio5 */
1265 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1266         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1267         { .irq = -1 }
1268 };
1269
1270 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1271         { .role = "dbclk", .clk = "gpio5_dbclk" },
1272 };
1273
1274 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1275         .name           = "gpio5",
1276         .class          = &omap44xx_gpio_hwmod_class,
1277         .clkdm_name     = "l4_per_clkdm",
1278         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1279         .mpu_irqs       = omap44xx_gpio5_irqs,
1280         .main_clk       = "gpio5_ick",
1281         .prcm = {
1282                 .omap4 = {
1283                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1284                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1285                         .modulemode   = MODULEMODE_HWCTRL,
1286                 },
1287         },
1288         .opt_clks       = gpio5_opt_clks,
1289         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1290         .dev_attr       = &gpio_dev_attr,
1291 };
1292
1293 /* gpio6 */
1294 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1295         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1296         { .irq = -1 }
1297 };
1298
1299 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1300         { .role = "dbclk", .clk = "gpio6_dbclk" },
1301 };
1302
1303 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1304         .name           = "gpio6",
1305         .class          = &omap44xx_gpio_hwmod_class,
1306         .clkdm_name     = "l4_per_clkdm",
1307         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1308         .mpu_irqs       = omap44xx_gpio6_irqs,
1309         .main_clk       = "gpio6_ick",
1310         .prcm = {
1311                 .omap4 = {
1312                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1313                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1314                         .modulemode   = MODULEMODE_HWCTRL,
1315                 },
1316         },
1317         .opt_clks       = gpio6_opt_clks,
1318         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1319         .dev_attr       = &gpio_dev_attr,
1320 };
1321
1322 /*
1323  * 'gpmc' class
1324  * general purpose memory controller
1325  */
1326
1327 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1328         .rev_offs       = 0x0000,
1329         .sysc_offs      = 0x0010,
1330         .syss_offs      = 0x0014,
1331         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1332                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1333         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1334         .sysc_fields    = &omap_hwmod_sysc_type1,
1335 };
1336
1337 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1338         .name   = "gpmc",
1339         .sysc   = &omap44xx_gpmc_sysc,
1340 };
1341
1342 /* gpmc */
1343 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = {
1344         { .irq = 20 + OMAP44XX_IRQ_GIC_START },
1345         { .irq = -1 }
1346 };
1347
1348 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = {
1349         { .dma_req = 3 + OMAP44XX_DMA_REQ_START },
1350         { .dma_req = -1 }
1351 };
1352
1353 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1354         .name           = "gpmc",
1355         .class          = &omap44xx_gpmc_hwmod_class,
1356         .clkdm_name     = "l3_2_clkdm",
1357         /*
1358          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1359          * block.  It is not being added due to any known bugs with
1360          * resetting the GPMC IP block, but rather because any timings
1361          * set by the bootloader are not being correctly programmed by
1362          * the kernel from the board file or DT data.
1363          * HWMOD_INIT_NO_RESET should be removed ASAP.
1364          */
1365         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1366         .mpu_irqs       = omap44xx_gpmc_irqs,
1367         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
1368         .prcm = {
1369                 .omap4 = {
1370                         .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1371                         .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1372                         .modulemode   = MODULEMODE_HWCTRL,
1373                 },
1374         },
1375 };
1376
1377 /*
1378  * 'gpu' class
1379  * 2d/3d graphics accelerator
1380  */
1381
1382 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1383         .rev_offs       = 0x1fc00,
1384         .sysc_offs      = 0x1fc10,
1385         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1386         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1387                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1388                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1389         .sysc_fields    = &omap_hwmod_sysc_type2,
1390 };
1391
1392 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1393         .name   = "gpu",
1394         .sysc   = &omap44xx_gpu_sysc,
1395 };
1396
1397 /* gpu */
1398 static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = {
1399         { .irq = 21 + OMAP44XX_IRQ_GIC_START },
1400         { .irq = -1 }
1401 };
1402
1403 static struct omap_hwmod omap44xx_gpu_hwmod = {
1404         .name           = "gpu",
1405         .class          = &omap44xx_gpu_hwmod_class,
1406         .clkdm_name     = "l3_gfx_clkdm",
1407         .mpu_irqs       = omap44xx_gpu_irqs,
1408         .main_clk       = "gpu_fck",
1409         .prcm = {
1410                 .omap4 = {
1411                         .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1412                         .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1413                         .modulemode   = MODULEMODE_SWCTRL,
1414                 },
1415         },
1416 };
1417
1418 /*
1419  * 'hdq1w' class
1420  * hdq / 1-wire serial interface controller
1421  */
1422
1423 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1424         .rev_offs       = 0x0000,
1425         .sysc_offs      = 0x0014,
1426         .syss_offs      = 0x0018,
1427         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1428                            SYSS_HAS_RESET_STATUS),
1429         .sysc_fields    = &omap_hwmod_sysc_type1,
1430 };
1431
1432 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1433         .name   = "hdq1w",
1434         .sysc   = &omap44xx_hdq1w_sysc,
1435 };
1436
1437 /* hdq1w */
1438 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = {
1439         { .irq = 58 + OMAP44XX_IRQ_GIC_START },
1440         { .irq = -1 }
1441 };
1442
1443 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1444         .name           = "hdq1w",
1445         .class          = &omap44xx_hdq1w_hwmod_class,
1446         .clkdm_name     = "l4_per_clkdm",
1447         .flags          = HWMOD_INIT_NO_RESET, /* XXX temporary */
1448         .mpu_irqs       = omap44xx_hdq1w_irqs,
1449         .main_clk       = "hdq1w_fck",
1450         .prcm = {
1451                 .omap4 = {
1452                         .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1453                         .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1454                         .modulemode   = MODULEMODE_SWCTRL,
1455                 },
1456         },
1457 };
1458
1459 /*
1460  * 'hsi' class
1461  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1462  * serial if)
1463  */
1464
1465 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1466         .rev_offs       = 0x0000,
1467         .sysc_offs      = 0x0010,
1468         .syss_offs      = 0x0014,
1469         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1470                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1471                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1472         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1473                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1474                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1475         .sysc_fields    = &omap_hwmod_sysc_type1,
1476 };
1477
1478 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1479         .name   = "hsi",
1480         .sysc   = &omap44xx_hsi_sysc,
1481 };
1482
1483 /* hsi */
1484 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1485         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1486         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1487         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1488         { .irq = -1 }
1489 };
1490
1491 static struct omap_hwmod omap44xx_hsi_hwmod = {
1492         .name           = "hsi",
1493         .class          = &omap44xx_hsi_hwmod_class,
1494         .clkdm_name     = "l3_init_clkdm",
1495         .mpu_irqs       = omap44xx_hsi_irqs,
1496         .main_clk       = "hsi_fck",
1497         .prcm = {
1498                 .omap4 = {
1499                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1500                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1501                         .modulemode   = MODULEMODE_HWCTRL,
1502                 },
1503         },
1504 };
1505
1506 /*
1507  * 'i2c' class
1508  * multimaster high-speed i2c controller
1509  */
1510
1511 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1512         .sysc_offs      = 0x0010,
1513         .syss_offs      = 0x0090,
1514         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1515                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1516                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1517         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1518                            SIDLE_SMART_WKUP),
1519         .clockact       = CLOCKACT_TEST_ICLK,
1520         .sysc_fields    = &omap_hwmod_sysc_type1,
1521 };
1522
1523 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1524         .name   = "i2c",
1525         .sysc   = &omap44xx_i2c_sysc,
1526         .rev    = OMAP_I2C_IP_VERSION_2,
1527         .reset  = &omap_i2c_reset,
1528 };
1529
1530 static struct omap_i2c_dev_attr i2c_dev_attr = {
1531         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1532                         OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1533 };
1534
1535 /* i2c1 */
1536 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1537         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1538         { .irq = -1 }
1539 };
1540
1541 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1542         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1543         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1544         { .dma_req = -1 }
1545 };
1546
1547 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1548         .name           = "i2c1",
1549         .class          = &omap44xx_i2c_hwmod_class,
1550         .clkdm_name     = "l4_per_clkdm",
1551         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1552         .mpu_irqs       = omap44xx_i2c1_irqs,
1553         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1554         .main_clk       = "i2c1_fck",
1555         .prcm = {
1556                 .omap4 = {
1557                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1558                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1559                         .modulemode   = MODULEMODE_SWCTRL,
1560                 },
1561         },
1562         .dev_attr       = &i2c_dev_attr,
1563 };
1564
1565 /* i2c2 */
1566 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1567         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1568         { .irq = -1 }
1569 };
1570
1571 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1572         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1573         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1574         { .dma_req = -1 }
1575 };
1576
1577 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1578         .name           = "i2c2",
1579         .class          = &omap44xx_i2c_hwmod_class,
1580         .clkdm_name     = "l4_per_clkdm",
1581         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1582         .mpu_irqs       = omap44xx_i2c2_irqs,
1583         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1584         .main_clk       = "i2c2_fck",
1585         .prcm = {
1586                 .omap4 = {
1587                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1588                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1589                         .modulemode   = MODULEMODE_SWCTRL,
1590                 },
1591         },
1592         .dev_attr       = &i2c_dev_attr,
1593 };
1594
1595 /* i2c3 */
1596 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1597         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1598         { .irq = -1 }
1599 };
1600
1601 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1602         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1603         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1604         { .dma_req = -1 }
1605 };
1606
1607 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1608         .name           = "i2c3",
1609         .class          = &omap44xx_i2c_hwmod_class,
1610         .clkdm_name     = "l4_per_clkdm",
1611         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1612         .mpu_irqs       = omap44xx_i2c3_irqs,
1613         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1614         .main_clk       = "i2c3_fck",
1615         .prcm = {
1616                 .omap4 = {
1617                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1618                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1619                         .modulemode   = MODULEMODE_SWCTRL,
1620                 },
1621         },
1622         .dev_attr       = &i2c_dev_attr,
1623 };
1624
1625 /* i2c4 */
1626 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1627         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1628         { .irq = -1 }
1629 };
1630
1631 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1632         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1633         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1634         { .dma_req = -1 }
1635 };
1636
1637 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1638         .name           = "i2c4",
1639         .class          = &omap44xx_i2c_hwmod_class,
1640         .clkdm_name     = "l4_per_clkdm",
1641         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1642         .mpu_irqs       = omap44xx_i2c4_irqs,
1643         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1644         .main_clk       = "i2c4_fck",
1645         .prcm = {
1646                 .omap4 = {
1647                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1648                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1649                         .modulemode   = MODULEMODE_SWCTRL,
1650                 },
1651         },
1652         .dev_attr       = &i2c_dev_attr,
1653 };
1654
1655 /*
1656  * 'ipu' class
1657  * imaging processor unit
1658  */
1659
1660 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1661         .name   = "ipu",
1662 };
1663
1664 /* ipu */
1665 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
1666         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
1667         { .irq = -1 }
1668 };
1669
1670 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1671         { .name = "cpu0", .rst_shift = 0 },
1672         { .name = "cpu1", .rst_shift = 1 },
1673 };
1674
1675 static struct omap_hwmod omap44xx_ipu_hwmod = {
1676         .name           = "ipu",
1677         .class          = &omap44xx_ipu_hwmod_class,
1678         .clkdm_name     = "ducati_clkdm",
1679         .mpu_irqs       = omap44xx_ipu_irqs,
1680         .rst_lines      = omap44xx_ipu_resets,
1681         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
1682         .main_clk       = "ipu_fck",
1683         .prcm = {
1684                 .omap4 = {
1685                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1686                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1687                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1688                         .modulemode   = MODULEMODE_HWCTRL,
1689                 },
1690         },
1691 };
1692
1693 /*
1694  * 'iss' class
1695  * external images sensor pixel data processor
1696  */
1697
1698 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1699         .rev_offs       = 0x0000,
1700         .sysc_offs      = 0x0010,
1701         /*
1702          * ISS needs 100 OCP clk cycles delay after a softreset before
1703          * accessing sysconfig again.
1704          * The lowest frequency at the moment for L3 bus is 100 MHz, so
1705          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1706          *
1707          * TODO: Indicate errata when available.
1708          */
1709         .srst_udelay    = 2,
1710         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1711                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1713                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1714                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1715         .sysc_fields    = &omap_hwmod_sysc_type2,
1716 };
1717
1718 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1719         .name   = "iss",
1720         .sysc   = &omap44xx_iss_sysc,
1721 };
1722
1723 /* iss */
1724 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
1725         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
1726         { .irq = -1 }
1727 };
1728
1729 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
1730         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
1731         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
1732         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
1733         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
1734         { .dma_req = -1 }
1735 };
1736
1737 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1738         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1739 };
1740
1741 static struct omap_hwmod omap44xx_iss_hwmod = {
1742         .name           = "iss",
1743         .class          = &omap44xx_iss_hwmod_class,
1744         .clkdm_name     = "iss_clkdm",
1745         .mpu_irqs       = omap44xx_iss_irqs,
1746         .sdma_reqs      = omap44xx_iss_sdma_reqs,
1747         .main_clk       = "iss_fck",
1748         .prcm = {
1749                 .omap4 = {
1750                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1751                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1752                         .modulemode   = MODULEMODE_SWCTRL,
1753                 },
1754         },
1755         .opt_clks       = iss_opt_clks,
1756         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
1757 };
1758
1759 /*
1760  * 'iva' class
1761  * multi-standard video encoder/decoder hardware accelerator
1762  */
1763
1764 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1765         .name   = "iva",
1766 };
1767
1768 /* iva */
1769 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1770         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1771         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1772         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1773         { .irq = -1 }
1774 };
1775
1776 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1777         { .name = "seq0", .rst_shift = 0 },
1778         { .name = "seq1", .rst_shift = 1 },
1779         { .name = "logic", .rst_shift = 2 },
1780 };
1781
1782 static struct omap_hwmod omap44xx_iva_hwmod = {
1783         .name           = "iva",
1784         .class          = &omap44xx_iva_hwmod_class,
1785         .clkdm_name     = "ivahd_clkdm",
1786         .mpu_irqs       = omap44xx_iva_irqs,
1787         .rst_lines      = omap44xx_iva_resets,
1788         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1789         .main_clk       = "iva_fck",
1790         .prcm = {
1791                 .omap4 = {
1792                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1793                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1794                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1795                         .modulemode   = MODULEMODE_HWCTRL,
1796                 },
1797         },
1798 };
1799
1800 /*
1801  * 'kbd' class
1802  * keyboard controller
1803  */
1804
1805 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1806         .rev_offs       = 0x0000,
1807         .sysc_offs      = 0x0010,
1808         .syss_offs      = 0x0014,
1809         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1810                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1811                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1812                            SYSS_HAS_RESET_STATUS),
1813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1814         .sysc_fields    = &omap_hwmod_sysc_type1,
1815 };
1816
1817 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1818         .name   = "kbd",
1819         .sysc   = &omap44xx_kbd_sysc,
1820 };
1821
1822 /* kbd */
1823 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
1824         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
1825         { .irq = -1 }
1826 };
1827
1828 static struct omap_hwmod omap44xx_kbd_hwmod = {
1829         .name           = "kbd",
1830         .class          = &omap44xx_kbd_hwmod_class,
1831         .clkdm_name     = "l4_wkup_clkdm",
1832         .mpu_irqs       = omap44xx_kbd_irqs,
1833         .main_clk       = "kbd_fck",
1834         .prcm = {
1835                 .omap4 = {
1836                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1837                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1838                         .modulemode   = MODULEMODE_SWCTRL,
1839                 },
1840         },
1841 };
1842
1843 /*
1844  * 'mailbox' class
1845  * mailbox module allowing communication between the on-chip processors using a
1846  * queued mailbox-interrupt mechanism.
1847  */
1848
1849 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1850         .rev_offs       = 0x0000,
1851         .sysc_offs      = 0x0010,
1852         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1853                            SYSC_HAS_SOFTRESET),
1854         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1855         .sysc_fields    = &omap_hwmod_sysc_type2,
1856 };
1857
1858 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1859         .name   = "mailbox",
1860         .sysc   = &omap44xx_mailbox_sysc,
1861 };
1862
1863 /* mailbox */
1864 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
1865         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
1866         { .irq = -1 }
1867 };
1868
1869 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1870         .name           = "mailbox",
1871         .class          = &omap44xx_mailbox_hwmod_class,
1872         .clkdm_name     = "l4_cfg_clkdm",
1873         .mpu_irqs       = omap44xx_mailbox_irqs,
1874         .prcm = {
1875                 .omap4 = {
1876                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1877                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1878                 },
1879         },
1880 };
1881
1882 /*
1883  * 'mcasp' class
1884  * multi-channel audio serial port controller
1885  */
1886
1887 /* The IP is not compliant to type1 / type2 scheme */
1888 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1889         .sidle_shift    = 0,
1890 };
1891
1892 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1893         .sysc_offs      = 0x0004,
1894         .sysc_flags     = SYSC_HAS_SIDLEMODE,
1895         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1896                            SIDLE_SMART_WKUP),
1897         .sysc_fields    = &omap_hwmod_sysc_type_mcasp,
1898 };
1899
1900 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1901         .name   = "mcasp",
1902         .sysc   = &omap44xx_mcasp_sysc,
1903 };
1904
1905 /* mcasp */
1906 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs[] = {
1907         { .name = "arevt", .irq = 108 + OMAP44XX_IRQ_GIC_START },
1908         { .name = "axevt", .irq = 109 + OMAP44XX_IRQ_GIC_START },
1909         { .irq = -1 }
1910 };
1911
1912 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs[] = {
1913         { .name = "axevt", .dma_req = 7 + OMAP44XX_DMA_REQ_START },
1914         { .name = "arevt", .dma_req = 10 + OMAP44XX_DMA_REQ_START },
1915         { .dma_req = -1 }
1916 };
1917
1918 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1919         .name           = "mcasp",
1920         .class          = &omap44xx_mcasp_hwmod_class,
1921         .clkdm_name     = "abe_clkdm",
1922         .mpu_irqs       = omap44xx_mcasp_irqs,
1923         .sdma_reqs      = omap44xx_mcasp_sdma_reqs,
1924         .main_clk       = "mcasp_fck",
1925         .prcm = {
1926                 .omap4 = {
1927                         .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1928                         .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1929                         .modulemode   = MODULEMODE_SWCTRL,
1930                 },
1931         },
1932 };
1933
1934 /*
1935  * 'mcbsp' class
1936  * multi channel buffered serial port controller
1937  */
1938
1939 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1940         .sysc_offs      = 0x008c,
1941         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1942                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1943         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1944         .sysc_fields    = &omap_hwmod_sysc_type1,
1945 };
1946
1947 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1948         .name   = "mcbsp",
1949         .sysc   = &omap44xx_mcbsp_sysc,
1950         .rev    = MCBSP_CONFIG_TYPE4,
1951 };
1952
1953 /* mcbsp1 */
1954 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
1955         { .name = "common", .irq = 17 + OMAP44XX_IRQ_GIC_START },
1956         { .irq = -1 }
1957 };
1958
1959 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
1960         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
1961         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
1962         { .dma_req = -1 }
1963 };
1964
1965 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1966         { .role = "pad_fck", .clk = "pad_clks_ck" },
1967         { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1968 };
1969
1970 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1971         .name           = "mcbsp1",
1972         .class          = &omap44xx_mcbsp_hwmod_class,
1973         .clkdm_name     = "abe_clkdm",
1974         .mpu_irqs       = omap44xx_mcbsp1_irqs,
1975         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
1976         .main_clk       = "mcbsp1_fck",
1977         .prcm = {
1978                 .omap4 = {
1979                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1980                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1981                         .modulemode   = MODULEMODE_SWCTRL,
1982                 },
1983         },
1984         .opt_clks       = mcbsp1_opt_clks,
1985         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
1986 };
1987
1988 /* mcbsp2 */
1989 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
1990         { .name = "common", .irq = 22 + OMAP44XX_IRQ_GIC_START },
1991         { .irq = -1 }
1992 };
1993
1994 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
1995         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
1996         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
1997         { .dma_req = -1 }
1998 };
1999
2000 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2001         { .role = "pad_fck", .clk = "pad_clks_ck" },
2002         { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
2003 };
2004
2005 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2006         .name           = "mcbsp2",
2007         .class          = &omap44xx_mcbsp_hwmod_class,
2008         .clkdm_name     = "abe_clkdm",
2009         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2010         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2011         .main_clk       = "mcbsp2_fck",
2012         .prcm = {
2013                 .omap4 = {
2014                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2015                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2016                         .modulemode   = MODULEMODE_SWCTRL,
2017                 },
2018         },
2019         .opt_clks       = mcbsp2_opt_clks,
2020         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2021 };
2022
2023 /* mcbsp3 */
2024 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2025         { .name = "common", .irq = 23 + OMAP44XX_IRQ_GIC_START },
2026         { .irq = -1 }
2027 };
2028
2029 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2030         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2031         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2032         { .dma_req = -1 }
2033 };
2034
2035 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2036         { .role = "pad_fck", .clk = "pad_clks_ck" },
2037         { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
2038 };
2039
2040 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2041         .name           = "mcbsp3",
2042         .class          = &omap44xx_mcbsp_hwmod_class,
2043         .clkdm_name     = "abe_clkdm",
2044         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2045         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2046         .main_clk       = "mcbsp3_fck",
2047         .prcm = {
2048                 .omap4 = {
2049                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2050                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2051                         .modulemode   = MODULEMODE_SWCTRL,
2052                 },
2053         },
2054         .opt_clks       = mcbsp3_opt_clks,
2055         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2056 };
2057
2058 /* mcbsp4 */
2059 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2060         { .name = "common", .irq = 16 + OMAP44XX_IRQ_GIC_START },
2061         { .irq = -1 }
2062 };
2063
2064 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2065         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2066         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2067         { .dma_req = -1 }
2068 };
2069
2070 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2071         { .role = "pad_fck", .clk = "pad_clks_ck" },
2072         { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
2073 };
2074
2075 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2076         .name           = "mcbsp4",
2077         .class          = &omap44xx_mcbsp_hwmod_class,
2078         .clkdm_name     = "l4_per_clkdm",
2079         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2080         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2081         .main_clk       = "mcbsp4_fck",
2082         .prcm = {
2083                 .omap4 = {
2084                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2085                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2086                         .modulemode   = MODULEMODE_SWCTRL,
2087                 },
2088         },
2089         .opt_clks       = mcbsp4_opt_clks,
2090         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2091 };
2092
2093 /*
2094  * 'mcpdm' class
2095  * multi channel pdm controller (proprietary interface with phoenix power
2096  * ic)
2097  */
2098
2099 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2100         .rev_offs       = 0x0000,
2101         .sysc_offs      = 0x0010,
2102         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2103                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2105                            SIDLE_SMART_WKUP),
2106         .sysc_fields    = &omap_hwmod_sysc_type2,
2107 };
2108
2109 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2110         .name   = "mcpdm",
2111         .sysc   = &omap44xx_mcpdm_sysc,
2112 };
2113
2114 /* mcpdm */
2115 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2116         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2117         { .irq = -1 }
2118 };
2119
2120 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2121         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2122         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2123         { .dma_req = -1 }
2124 };
2125
2126 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2127         .name           = "mcpdm",
2128         .class          = &omap44xx_mcpdm_hwmod_class,
2129         .clkdm_name     = "abe_clkdm",
2130         /*
2131          * It's suspected that the McPDM requires an off-chip main
2132          * functional clock, controlled via I2C.  This IP block is
2133          * currently reset very early during boot, before I2C is
2134          * available, so it doesn't seem that we have any choice in
2135          * the kernel other than to avoid resetting it.
2136          */
2137         .flags          = HWMOD_EXT_OPT_MAIN_CLK,
2138         .mpu_irqs       = omap44xx_mcpdm_irqs,
2139         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2140         .main_clk       = "mcpdm_fck",
2141         .prcm = {
2142                 .omap4 = {
2143                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2144                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2145                         .modulemode   = MODULEMODE_SWCTRL,
2146                 },
2147         },
2148 };
2149
2150 /*
2151  * 'mcspi' class
2152  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2153  * bus
2154  */
2155
2156 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2157         .rev_offs       = 0x0000,
2158         .sysc_offs      = 0x0010,
2159         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2160                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2161         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2162                            SIDLE_SMART_WKUP),
2163         .sysc_fields    = &omap_hwmod_sysc_type2,
2164 };
2165
2166 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2167         .name   = "mcspi",
2168         .sysc   = &omap44xx_mcspi_sysc,
2169         .rev    = OMAP4_MCSPI_REV,
2170 };
2171
2172 /* mcspi1 */
2173 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2174         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2175         { .irq = -1 }
2176 };
2177
2178 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2179         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2180         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2181         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2182         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2183         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2184         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2185         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2186         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2187         { .dma_req = -1 }
2188 };
2189
2190 /* mcspi1 dev_attr */
2191 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2192         .num_chipselect = 4,
2193 };
2194
2195 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2196         .name           = "mcspi1",
2197         .class          = &omap44xx_mcspi_hwmod_class,
2198         .clkdm_name     = "l4_per_clkdm",
2199         .mpu_irqs       = omap44xx_mcspi1_irqs,
2200         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2201         .main_clk       = "mcspi1_fck",
2202         .prcm = {
2203                 .omap4 = {
2204                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2205                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2206                         .modulemode   = MODULEMODE_SWCTRL,
2207                 },
2208         },
2209         .dev_attr       = &mcspi1_dev_attr,
2210 };
2211
2212 /* mcspi2 */
2213 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2214         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2215         { .irq = -1 }
2216 };
2217
2218 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2219         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2220         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2221         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2222         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2223         { .dma_req = -1 }
2224 };
2225
2226 /* mcspi2 dev_attr */
2227 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2228         .num_chipselect = 2,
2229 };
2230
2231 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2232         .name           = "mcspi2",
2233         .class          = &omap44xx_mcspi_hwmod_class,
2234         .clkdm_name     = "l4_per_clkdm",
2235         .mpu_irqs       = omap44xx_mcspi2_irqs,
2236         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2237         .main_clk       = "mcspi2_fck",
2238         .prcm = {
2239                 .omap4 = {
2240                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2241                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2242                         .modulemode   = MODULEMODE_SWCTRL,
2243                 },
2244         },
2245         .dev_attr       = &mcspi2_dev_attr,
2246 };
2247
2248 /* mcspi3 */
2249 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2250         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2251         { .irq = -1 }
2252 };
2253
2254 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2255         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2256         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2257         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2258         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2259         { .dma_req = -1 }
2260 };
2261
2262 /* mcspi3 dev_attr */
2263 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
2264         .num_chipselect = 2,
2265 };
2266
2267 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
2268         .name           = "mcspi3",
2269         .class          = &omap44xx_mcspi_hwmod_class,
2270         .clkdm_name     = "l4_per_clkdm",
2271         .mpu_irqs       = omap44xx_mcspi3_irqs,
2272         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
2273         .main_clk       = "mcspi3_fck",
2274         .prcm = {
2275                 .omap4 = {
2276                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
2277                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
2278                         .modulemode   = MODULEMODE_SWCTRL,
2279                 },
2280         },
2281         .dev_attr       = &mcspi3_dev_attr,
2282 };
2283
2284 /* mcspi4 */
2285 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
2286         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
2287         { .irq = -1 }
2288 };
2289
2290 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
2291         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
2292         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
2293         { .dma_req = -1 }
2294 };
2295
2296 /* mcspi4 dev_attr */
2297 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
2298         .num_chipselect = 1,
2299 };
2300
2301 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
2302         .name           = "mcspi4",
2303         .class          = &omap44xx_mcspi_hwmod_class,
2304         .clkdm_name     = "l4_per_clkdm",
2305         .mpu_irqs       = omap44xx_mcspi4_irqs,
2306         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
2307         .main_clk       = "mcspi4_fck",
2308         .prcm = {
2309                 .omap4 = {
2310                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
2311                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
2312                         .modulemode   = MODULEMODE_SWCTRL,
2313                 },
2314         },
2315         .dev_attr       = &mcspi4_dev_attr,
2316 };
2317
2318 /*
2319  * 'mmc' class
2320  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2321  */
2322
2323 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
2324         .rev_offs       = 0x0000,
2325         .sysc_offs      = 0x0010,
2326         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
2327                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2328                            SYSC_HAS_SOFTRESET),
2329         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2330                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2331                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2332         .sysc_fields    = &omap_hwmod_sysc_type2,
2333 };
2334
2335 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
2336         .name   = "mmc",
2337         .sysc   = &omap44xx_mmc_sysc,
2338 };
2339
2340 /* mmc1 */
2341 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
2342         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
2343         { .irq = -1 }
2344 };
2345
2346 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
2347         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
2348         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
2349         { .dma_req = -1 }
2350 };
2351
2352 /* mmc1 dev_attr */
2353 static struct omap_mmc_dev_attr mmc1_dev_attr = {
2354         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2355 };
2356
2357 static struct omap_hwmod omap44xx_mmc1_hwmod = {
2358         .name           = "mmc1",
2359         .class          = &omap44xx_mmc_hwmod_class,
2360         .clkdm_name     = "l3_init_clkdm",
2361         .mpu_irqs       = omap44xx_mmc1_irqs,
2362         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
2363         .main_clk       = "mmc1_fck",
2364         .prcm = {
2365                 .omap4 = {
2366                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
2367                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
2368                         .modulemode   = MODULEMODE_SWCTRL,
2369                 },
2370         },
2371         .dev_attr       = &mmc1_dev_attr,
2372 };
2373
2374 /* mmc2 */
2375 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
2376         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
2377         { .irq = -1 }
2378 };
2379
2380 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
2381         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
2382         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
2383         { .dma_req = -1 }
2384 };
2385
2386 static struct omap_hwmod omap44xx_mmc2_hwmod = {
2387         .name           = "mmc2",
2388         .class          = &omap44xx_mmc_hwmod_class,
2389         .clkdm_name     = "l3_init_clkdm",
2390         .mpu_irqs       = omap44xx_mmc2_irqs,
2391         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
2392         .main_clk       = "mmc2_fck",
2393         .prcm = {
2394                 .omap4 = {
2395                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
2396                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
2397                         .modulemode   = MODULEMODE_SWCTRL,
2398                 },
2399         },
2400 };
2401
2402 /* mmc3 */
2403 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
2404         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
2405         { .irq = -1 }
2406 };
2407
2408 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
2409         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2410         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2411         { .dma_req = -1 }
2412 };
2413
2414 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2415         .name           = "mmc3",
2416         .class          = &omap44xx_mmc_hwmod_class,
2417         .clkdm_name     = "l4_per_clkdm",
2418         .mpu_irqs       = omap44xx_mmc3_irqs,
2419         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
2420         .main_clk       = "mmc3_fck",
2421         .prcm = {
2422                 .omap4 = {
2423                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2424                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2425                         .modulemode   = MODULEMODE_SWCTRL,
2426                 },
2427         },
2428 };
2429
2430 /* mmc4 */
2431 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
2432         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
2433         { .irq = -1 }
2434 };
2435
2436 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2437         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2438         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2439         { .dma_req = -1 }
2440 };
2441
2442 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2443         .name           = "mmc4",
2444         .class          = &omap44xx_mmc_hwmod_class,
2445         .clkdm_name     = "l4_per_clkdm",
2446         .mpu_irqs       = omap44xx_mmc4_irqs,
2447         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
2448         .main_clk       = "mmc4_fck",
2449         .prcm = {
2450                 .omap4 = {
2451                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2452                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2453                         .modulemode   = MODULEMODE_SWCTRL,
2454                 },
2455         },
2456 };
2457
2458 /* mmc5 */
2459 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
2460         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
2461         { .irq = -1 }
2462 };
2463
2464 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2465         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2466         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2467         { .dma_req = -1 }
2468 };
2469
2470 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2471         .name           = "mmc5",
2472         .class          = &omap44xx_mmc_hwmod_class,
2473         .clkdm_name     = "l4_per_clkdm",
2474         .mpu_irqs       = omap44xx_mmc5_irqs,
2475         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
2476         .main_clk       = "mmc5_fck",
2477         .prcm = {
2478                 .omap4 = {
2479                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2480                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2481                         .modulemode   = MODULEMODE_SWCTRL,
2482                 },
2483         },
2484 };
2485
2486 /*
2487  * 'mmu' class
2488  * The memory management unit performs virtual to physical address translation
2489  * for its requestors.
2490  */
2491
2492 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2493         .rev_offs       = 0x000,
2494         .sysc_offs      = 0x010,
2495         .syss_offs      = 0x014,
2496         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2497                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2498         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2499         .sysc_fields    = &omap_hwmod_sysc_type1,
2500 };
2501
2502 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2503         .name = "mmu",
2504         .sysc = &mmu_sysc,
2505 };
2506
2507 /* mmu ipu */
2508
2509 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2510         .da_start       = 0x0,
2511         .da_end         = 0xfffff000,
2512         .nr_tlb_entries = 32,
2513 };
2514
2515 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2516 static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
2517         { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
2518         { .irq = -1 }
2519 };
2520
2521 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2522         { .name = "mmu_cache", .rst_shift = 2 },
2523 };
2524
2525 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2526         {
2527                 .pa_start       = 0x55082000,
2528                 .pa_end         = 0x550820ff,
2529                 .flags          = ADDR_TYPE_RT,
2530         },
2531         { }
2532 };
2533
2534 /* l3_main_2 -> mmu_ipu */
2535 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2536         .master         = &omap44xx_l3_main_2_hwmod,
2537         .slave          = &omap44xx_mmu_ipu_hwmod,
2538         .clk            = "l3_div_ck",
2539         .addr           = omap44xx_mmu_ipu_addrs,
2540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2541 };
2542
2543 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2544         .name           = "mmu_ipu",
2545         .class          = &omap44xx_mmu_hwmod_class,
2546         .clkdm_name     = "ducati_clkdm",
2547         .mpu_irqs       = omap44xx_mmu_ipu_irqs,
2548         .rst_lines      = omap44xx_mmu_ipu_resets,
2549         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2550         .main_clk       = "ducati_clk_mux_ck",
2551         .prcm = {
2552                 .omap4 = {
2553                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2554                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2555                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2556                         .modulemode   = MODULEMODE_HWCTRL,
2557                 },
2558         },
2559         .dev_attr       = &mmu_ipu_dev_attr,
2560 };
2561
2562 /* mmu dsp */
2563
2564 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2565         .da_start       = 0x0,
2566         .da_end         = 0xfffff000,
2567         .nr_tlb_entries = 32,
2568 };
2569
2570 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2571 static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
2572         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
2573         { .irq = -1 }
2574 };
2575
2576 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2577         { .name = "mmu_cache", .rst_shift = 1 },
2578 };
2579
2580 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2581         {
2582                 .pa_start       = 0x4a066000,
2583                 .pa_end         = 0x4a0660ff,
2584                 .flags          = ADDR_TYPE_RT,
2585         },
2586         { }
2587 };
2588
2589 /* l4_cfg -> dsp */
2590 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2591         .master         = &omap44xx_l4_cfg_hwmod,
2592         .slave          = &omap44xx_mmu_dsp_hwmod,
2593         .clk            = "l4_div_ck",
2594         .addr           = omap44xx_mmu_dsp_addrs,
2595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2596 };
2597
2598 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2599         .name           = "mmu_dsp",
2600         .class          = &omap44xx_mmu_hwmod_class,
2601         .clkdm_name     = "tesla_clkdm",
2602         .mpu_irqs       = omap44xx_mmu_dsp_irqs,
2603         .rst_lines      = omap44xx_mmu_dsp_resets,
2604         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2605         .main_clk       = "dpll_iva_m4x2_ck",
2606         .prcm = {
2607                 .omap4 = {
2608                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2609                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2610                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2611                         .modulemode   = MODULEMODE_HWCTRL,
2612                 },
2613         },
2614         .dev_attr       = &mmu_dsp_dev_attr,
2615 };
2616
2617 /*
2618  * 'mpu' class
2619  * mpu sub-system
2620  */
2621
2622 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2623         .name   = "mpu",
2624 };
2625
2626 /* mpu */
2627 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
2628         { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
2629         { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
2630         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
2631         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
2632         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
2633         { .irq = -1 }
2634 };
2635
2636 static struct omap_hwmod omap44xx_mpu_hwmod = {
2637         .name           = "mpu",
2638         .class          = &omap44xx_mpu_hwmod_class,
2639         .clkdm_name     = "mpuss_clkdm",
2640         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2641         .mpu_irqs       = omap44xx_mpu_irqs,
2642         .main_clk       = "dpll_mpu_m2_ck",
2643         .prcm = {
2644                 .omap4 = {
2645                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2646                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2647                 },
2648         },
2649 };
2650
2651 /*
2652  * 'ocmc_ram' class
2653  * top-level core on-chip ram
2654  */
2655
2656 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2657         .name   = "ocmc_ram",
2658 };
2659
2660 /* ocmc_ram */
2661 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2662         .name           = "ocmc_ram",
2663         .class          = &omap44xx_ocmc_ram_hwmod_class,
2664         .clkdm_name     = "l3_2_clkdm",
2665         .prcm = {
2666                 .omap4 = {
2667                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2668                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2669                 },
2670         },
2671 };
2672
2673 /*
2674  * 'ocp2scp' class
2675  * bridge to transform ocp interface protocol to scp (serial control port)
2676  * protocol
2677  */
2678
2679 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2680         .rev_offs       = 0x0000,
2681         .sysc_offs      = 0x0010,
2682         .syss_offs      = 0x0014,
2683         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2684                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2685         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2686         .sysc_fields    = &omap_hwmod_sysc_type1,
2687 };
2688
2689 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2690         .name   = "ocp2scp",
2691         .sysc   = &omap44xx_ocp2scp_sysc,
2692 };
2693
2694 /* ocp2scp dev_attr */
2695 static struct resource omap44xx_usb_phy_and_pll_addrs[] = {
2696         {
2697                 .name           = "usb_phy",
2698                 .start          = 0x4a0ad080,
2699                 .end            = 0x4a0ae000,
2700                 .flags          = IORESOURCE_MEM,
2701         },
2702         {
2703                 /* XXX: Remove this once control module driver is in place */
2704                 .name           = "ctrl_dev",
2705                 .start          = 0x4a002300,
2706                 .end            = 0x4a002303,
2707                 .flags          = IORESOURCE_MEM,
2708         },
2709         { }
2710 };
2711
2712 static struct omap_ocp2scp_dev ocp2scp_dev_attr[] = {
2713         {
2714                 .drv_name       = "omap-usb2",
2715                 .res            = omap44xx_usb_phy_and_pll_addrs,
2716         },
2717         { }
2718 };
2719
2720 /* ocp2scp_usb_phy */
2721 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2722         .name           = "ocp2scp_usb_phy",
2723         .class          = &omap44xx_ocp2scp_hwmod_class,
2724         .clkdm_name     = "l3_init_clkdm",
2725         .main_clk       = "ocp2scp_usb_phy_phy_48m",
2726         .prcm = {
2727                 .omap4 = {
2728                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2729                         .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2730                         .modulemode   = MODULEMODE_HWCTRL,
2731                 },
2732         },
2733         .dev_attr       = ocp2scp_dev_attr,
2734 };
2735
2736 /*
2737  * 'prcm' class
2738  * power and reset manager (part of the prcm infrastructure) + clock manager 2
2739  * + clock manager 1 (in always on power domain) + local prm in mpu
2740  */
2741
2742 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2743         .name   = "prcm",
2744 };
2745
2746 /* prcm_mpu */
2747 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2748         .name           = "prcm_mpu",
2749         .class          = &omap44xx_prcm_hwmod_class,
2750         .clkdm_name     = "l4_wkup_clkdm",
2751         .flags          = HWMOD_NO_IDLEST,
2752         .prcm = {
2753                 .omap4 = {
2754                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2755                 },
2756         },
2757 };
2758
2759 /* cm_core_aon */
2760 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2761         .name           = "cm_core_aon",
2762         .class          = &omap44xx_prcm_hwmod_class,
2763         .flags          = HWMOD_NO_IDLEST,
2764         .prcm = {
2765                 .omap4 = {
2766                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2767                 },
2768         },
2769 };
2770
2771 /* cm_core */
2772 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2773         .name           = "cm_core",
2774         .class          = &omap44xx_prcm_hwmod_class,
2775         .flags          = HWMOD_NO_IDLEST,
2776         .prcm = {
2777                 .omap4 = {
2778                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2779                 },
2780         },
2781 };
2782
2783 /* prm */
2784 static struct omap_hwmod_irq_info omap44xx_prm_irqs[] = {
2785         { .irq = 11 + OMAP44XX_IRQ_GIC_START },
2786         { .irq = -1 }
2787 };
2788
2789 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2790         { .name = "rst_global_warm_sw", .rst_shift = 0 },
2791         { .name = "rst_global_cold_sw", .rst_shift = 1 },
2792 };
2793
2794 static struct omap_hwmod omap44xx_prm_hwmod = {
2795         .name           = "prm",
2796         .class          = &omap44xx_prcm_hwmod_class,
2797         .mpu_irqs       = omap44xx_prm_irqs,
2798         .rst_lines      = omap44xx_prm_resets,
2799         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
2800 };
2801
2802 /*
2803  * 'scrm' class
2804  * system clock and reset manager
2805  */
2806
2807 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2808         .name   = "scrm",
2809 };
2810
2811 /* scrm */
2812 static struct omap_hwmod omap44xx_scrm_hwmod = {
2813         .name           = "scrm",
2814         .class          = &omap44xx_scrm_hwmod_class,
2815         .clkdm_name     = "l4_wkup_clkdm",
2816         .prcm = {
2817                 .omap4 = {
2818                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2819                 },
2820         },
2821 };
2822
2823 /*
2824  * 'sl2if' class
2825  * shared level 2 memory interface
2826  */
2827
2828 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2829         .name   = "sl2if",
2830 };
2831
2832 /* sl2if */
2833 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2834         .name           = "sl2if",
2835         .class          = &omap44xx_sl2if_hwmod_class,
2836         .clkdm_name     = "ivahd_clkdm",
2837         .prcm = {
2838                 .omap4 = {
2839                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2840                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2841                         .modulemode   = MODULEMODE_HWCTRL,
2842                 },
2843         },
2844 };
2845
2846 /*
2847  * 'slimbus' class
2848  * bidirectional, multi-drop, multi-channel two-line serial interface between
2849  * the device and external components
2850  */
2851
2852 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2853         .rev_offs       = 0x0000,
2854         .sysc_offs      = 0x0010,
2855         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2856                            SYSC_HAS_SOFTRESET),
2857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2858                            SIDLE_SMART_WKUP),
2859         .sysc_fields    = &omap_hwmod_sysc_type2,
2860 };
2861
2862 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2863         .name   = "slimbus",
2864         .sysc   = &omap44xx_slimbus_sysc,
2865 };
2866
2867 /* slimbus1 */
2868 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs[] = {
2869         { .irq = 97 + OMAP44XX_IRQ_GIC_START },
2870         { .irq = -1 }
2871 };
2872
2873 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs[] = {
2874         { .name = "tx0", .dma_req = 84 + OMAP44XX_DMA_REQ_START },
2875         { .name = "tx1", .dma_req = 85 + OMAP44XX_DMA_REQ_START },
2876         { .name = "tx2", .dma_req = 86 + OMAP44XX_DMA_REQ_START },
2877         { .name = "tx3", .dma_req = 87 + OMAP44XX_DMA_REQ_START },
2878         { .name = "rx0", .dma_req = 88 + OMAP44XX_DMA_REQ_START },
2879         { .name = "rx1", .dma_req = 89 + OMAP44XX_DMA_REQ_START },
2880         { .name = "rx2", .dma_req = 90 + OMAP44XX_DMA_REQ_START },
2881         { .name = "rx3", .dma_req = 91 + OMAP44XX_DMA_REQ_START },
2882         { .dma_req = -1 }
2883 };
2884
2885 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2886         { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2887         { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2888         { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2889         { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2890 };
2891
2892 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2893         .name           = "slimbus1",
2894         .class          = &omap44xx_slimbus_hwmod_class,
2895         .clkdm_name     = "abe_clkdm",
2896         .mpu_irqs       = omap44xx_slimbus1_irqs,
2897         .sdma_reqs      = omap44xx_slimbus1_sdma_reqs,
2898         .prcm = {
2899                 .omap4 = {
2900                         .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2901                         .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2902                         .modulemode   = MODULEMODE_SWCTRL,
2903                 },
2904         },
2905         .opt_clks       = slimbus1_opt_clks,
2906         .opt_clks_cnt   = ARRAY_SIZE(slimbus1_opt_clks),
2907 };
2908
2909 /* slimbus2 */
2910 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs[] = {
2911         { .irq = 98 + OMAP44XX_IRQ_GIC_START },
2912         { .irq = -1 }
2913 };
2914
2915 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs[] = {
2916         { .name = "tx0", .dma_req = 92 + OMAP44XX_DMA_REQ_START },
2917         { .name = "tx1", .dma_req = 93 + OMAP44XX_DMA_REQ_START },
2918         { .name = "tx2", .dma_req = 94 + OMAP44XX_DMA_REQ_START },
2919         { .name = "tx3", .dma_req = 95 + OMAP44XX_DMA_REQ_START },
2920         { .name = "rx0", .dma_req = 96 + OMAP44XX_DMA_REQ_START },
2921         { .name = "rx1", .dma_req = 97 + OMAP44XX_DMA_REQ_START },
2922         { .name = "rx2", .dma_req = 98 + OMAP44XX_DMA_REQ_START },
2923         { .name = "rx3", .dma_req = 99 + OMAP44XX_DMA_REQ_START },
2924         { .dma_req = -1 }
2925 };
2926
2927 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2928         { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2929         { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2930         { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2931 };
2932
2933 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2934         .name           = "slimbus2",
2935         .class          = &omap44xx_slimbus_hwmod_class,
2936         .clkdm_name     = "l4_per_clkdm",
2937         .mpu_irqs       = omap44xx_slimbus2_irqs,
2938         .sdma_reqs      = omap44xx_slimbus2_sdma_reqs,
2939         .prcm = {
2940                 .omap4 = {
2941                         .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2942                         .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2943                         .modulemode   = MODULEMODE_SWCTRL,
2944                 },
2945         },
2946         .opt_clks       = slimbus2_opt_clks,
2947         .opt_clks_cnt   = ARRAY_SIZE(slimbus2_opt_clks),
2948 };
2949
2950 /*
2951  * 'smartreflex' class
2952  * smartreflex module (monitor silicon performance and outputs a measure of
2953  * performance error)
2954  */
2955
2956 /* The IP is not compliant to type1 / type2 scheme */
2957 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2958         .sidle_shift    = 24,
2959         .enwkup_shift   = 26,
2960 };
2961
2962 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2963         .sysc_offs      = 0x0038,
2964         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2965         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2966                            SIDLE_SMART_WKUP),
2967         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
2968 };
2969
2970 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2971         .name   = "smartreflex",
2972         .sysc   = &omap44xx_smartreflex_sysc,
2973         .rev    = 2,
2974 };
2975
2976 /* smartreflex_core */
2977 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2978         .sensor_voltdm_name   = "core",
2979 };
2980
2981 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
2982         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
2983         { .irq = -1 }
2984 };
2985
2986 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2987         .name           = "smartreflex_core",
2988         .class          = &omap44xx_smartreflex_hwmod_class,
2989         .clkdm_name     = "l4_ao_clkdm",
2990         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
2991
2992         .main_clk       = "smartreflex_core_fck",
2993         .prcm = {
2994                 .omap4 = {
2995                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2996                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2997                         .modulemode   = MODULEMODE_SWCTRL,
2998                 },
2999         },
3000         .dev_attr       = &smartreflex_core_dev_attr,
3001 };
3002
3003 /* smartreflex_iva */
3004 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3005         .sensor_voltdm_name     = "iva",
3006 };
3007
3008 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3009         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3010         { .irq = -1 }
3011 };
3012
3013 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3014         .name           = "smartreflex_iva",
3015         .class          = &omap44xx_smartreflex_hwmod_class,
3016         .clkdm_name     = "l4_ao_clkdm",
3017         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3018         .main_clk       = "smartreflex_iva_fck",
3019         .prcm = {
3020                 .omap4 = {
3021                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3022                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3023                         .modulemode   = MODULEMODE_SWCTRL,
3024                 },
3025         },
3026         .dev_attr       = &smartreflex_iva_dev_attr,
3027 };
3028
3029 /* smartreflex_mpu */
3030 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3031         .sensor_voltdm_name     = "mpu",
3032 };
3033
3034 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3035         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3036         { .irq = -1 }
3037 };
3038
3039 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3040         .name           = "smartreflex_mpu",
3041         .class          = &omap44xx_smartreflex_hwmod_class,
3042         .clkdm_name     = "l4_ao_clkdm",
3043         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3044         .main_clk       = "smartreflex_mpu_fck",
3045         .prcm = {
3046                 .omap4 = {
3047                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3048                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3049                         .modulemode   = MODULEMODE_SWCTRL,
3050                 },
3051         },
3052         .dev_attr       = &smartreflex_mpu_dev_attr,
3053 };
3054
3055 /*
3056  * 'spinlock' class
3057  * spinlock provides hardware assistance for synchronizing the processes
3058  * running on multiple processors
3059  */
3060
3061 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3062         .rev_offs       = 0x0000,
3063         .sysc_offs      = 0x0010,
3064         .syss_offs      = 0x0014,
3065         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3066                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3067                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3068         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3069                            SIDLE_SMART_WKUP),
3070         .sysc_fields    = &omap_hwmod_sysc_type1,
3071 };
3072
3073 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3074         .name   = "spinlock",
3075         .sysc   = &omap44xx_spinlock_sysc,
3076 };
3077
3078 /* spinlock */
3079 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3080         .name           = "spinlock",
3081         .class          = &omap44xx_spinlock_hwmod_class,
3082         .clkdm_name     = "l4_cfg_clkdm",
3083         .prcm = {
3084                 .omap4 = {
3085                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3086                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3087                 },
3088         },
3089 };
3090
3091 /*
3092  * 'timer' class
3093  * general purpose timer module with accurate 1ms tick
3094  * This class contains several variants: ['timer_1ms', 'timer']
3095  */
3096
3097 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3098         .rev_offs       = 0x0000,
3099         .sysc_offs      = 0x0010,
3100         .syss_offs      = 0x0014,
3101         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3102                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3103                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3104                            SYSS_HAS_RESET_STATUS),
3105         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3106         .sysc_fields    = &omap_hwmod_sysc_type1,
3107 };
3108
3109 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3110         .name   = "timer",
3111         .sysc   = &omap44xx_timer_1ms_sysc,
3112 };
3113
3114 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3115         .rev_offs       = 0x0000,
3116         .sysc_offs      = 0x0010,
3117         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3118                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3119         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3120                            SIDLE_SMART_WKUP),
3121         .sysc_fields    = &omap_hwmod_sysc_type2,
3122 };
3123
3124 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3125         .name   = "timer",
3126         .sysc   = &omap44xx_timer_sysc,
3127 };
3128
3129 /* always-on timers dev attribute */
3130 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3131         .timer_capability       = OMAP_TIMER_ALWON,
3132 };
3133
3134 /* pwm timers dev attribute */
3135 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3136         .timer_capability       = OMAP_TIMER_HAS_PWM,
3137 };
3138
3139 /* timers with DSP interrupt dev attribute */
3140 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
3141         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
3142 };
3143
3144 /* pwm timers with DSP interrupt dev attribute */
3145 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
3146         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
3147 };
3148
3149 /* timer1 */
3150 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3151         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3152         { .irq = -1 }
3153 };
3154
3155 static struct omap_hwmod omap44xx_timer1_hwmod = {
3156         .name           = "timer1",
3157         .class          = &omap44xx_timer_1ms_hwmod_class,
3158         .clkdm_name     = "l4_wkup_clkdm",
3159         .mpu_irqs       = omap44xx_timer1_irqs,
3160         .main_clk       = "timer1_fck",
3161         .prcm = {
3162                 .omap4 = {
3163                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3164                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3165                         .modulemode   = MODULEMODE_SWCTRL,
3166                 },
3167         },
3168         .dev_attr       = &capability_alwon_dev_attr,
3169 };
3170
3171 /* timer2 */
3172 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3173         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3174         { .irq = -1 }
3175 };
3176
3177 static struct omap_hwmod omap44xx_timer2_hwmod = {
3178         .name           = "timer2",
3179         .class          = &omap44xx_timer_1ms_hwmod_class,
3180         .clkdm_name     = "l4_per_clkdm",
3181         .mpu_irqs       = omap44xx_timer2_irqs,
3182         .main_clk       = "timer2_fck",
3183         .prcm = {
3184                 .omap4 = {
3185                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3186                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3187                         .modulemode   = MODULEMODE_SWCTRL,
3188                 },
3189         },
3190 };
3191
3192 /* timer3 */
3193 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3194         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3195         { .irq = -1 }
3196 };
3197
3198 static struct omap_hwmod omap44xx_timer3_hwmod = {
3199         .name           = "timer3",
3200         .class          = &omap44xx_timer_hwmod_class,
3201         .clkdm_name     = "l4_per_clkdm",
3202         .mpu_irqs       = omap44xx_timer3_irqs,
3203         .main_clk       = "timer3_fck",
3204         .prcm = {
3205                 .omap4 = {
3206                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3207                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3208                         .modulemode   = MODULEMODE_SWCTRL,
3209                 },
3210         },
3211 };
3212
3213 /* timer4 */
3214 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3215         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3216         { .irq = -1 }
3217 };
3218
3219 static struct omap_hwmod omap44xx_timer4_hwmod = {
3220         .name           = "timer4",
3221         .class          = &omap44xx_timer_hwmod_class,
3222         .clkdm_name     = "l4_per_clkdm",
3223         .mpu_irqs       = omap44xx_timer4_irqs,
3224         .main_clk       = "timer4_fck",
3225         .prcm = {
3226                 .omap4 = {
3227                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3228                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3229                         .modulemode   = MODULEMODE_SWCTRL,
3230                 },
3231         },
3232 };
3233
3234 /* timer5 */
3235 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3236         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3237         { .irq = -1 }
3238 };
3239
3240 static struct omap_hwmod omap44xx_timer5_hwmod = {
3241         .name           = "timer5",
3242         .class          = &omap44xx_timer_hwmod_class,
3243         .clkdm_name     = "abe_clkdm",
3244         .mpu_irqs       = omap44xx_timer5_irqs,
3245         .main_clk       = "timer5_fck",
3246         .prcm = {
3247                 .omap4 = {
3248                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3249                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3250                         .modulemode   = MODULEMODE_SWCTRL,
3251                 },
3252         },
3253         .dev_attr       = &capability_dsp_dev_attr,
3254 };
3255
3256 /* timer6 */
3257 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3258         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3259         { .irq = -1 }
3260 };
3261
3262 static struct omap_hwmod omap44xx_timer6_hwmod = {
3263         .name           = "timer6",
3264         .class          = &omap44xx_timer_hwmod_class,
3265         .clkdm_name     = "abe_clkdm",
3266         .mpu_irqs       = omap44xx_timer6_irqs,
3267
3268         .main_clk       = "timer6_fck",
3269         .prcm = {
3270                 .omap4 = {
3271                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3272                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3273                         .modulemode   = MODULEMODE_SWCTRL,
3274                 },
3275         },
3276         .dev_attr       = &capability_dsp_dev_attr,
3277 };
3278
3279 /* timer7 */
3280 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3281         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3282         { .irq = -1 }
3283 };
3284
3285 static struct omap_hwmod omap44xx_timer7_hwmod = {
3286         .name           = "timer7",
3287         .class          = &omap44xx_timer_hwmod_class,
3288         .clkdm_name     = "abe_clkdm",
3289         .mpu_irqs       = omap44xx_timer7_irqs,
3290         .main_clk       = "timer7_fck",
3291         .prcm = {
3292                 .omap4 = {
3293                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3294                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3295                         .modulemode   = MODULEMODE_SWCTRL,
3296                 },
3297         },
3298         .dev_attr       = &capability_dsp_dev_attr,
3299 };
3300
3301 /* timer8 */
3302 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3303         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3304         { .irq = -1 }
3305 };
3306
3307 static struct omap_hwmod omap44xx_timer8_hwmod = {
3308         .name           = "timer8",
3309         .class          = &omap44xx_timer_hwmod_class,
3310         .clkdm_name     = "abe_clkdm",
3311         .mpu_irqs       = omap44xx_timer8_irqs,
3312         .main_clk       = "timer8_fck",
3313         .prcm = {
3314                 .omap4 = {
3315                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
3316                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
3317                         .modulemode   = MODULEMODE_SWCTRL,
3318                 },
3319         },
3320         .dev_attr       = &capability_dsp_pwm_dev_attr,
3321 };
3322
3323 /* timer9 */
3324 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
3325         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
3326         { .irq = -1 }
3327 };
3328
3329 static struct omap_hwmod omap44xx_timer9_hwmod = {
3330         .name           = "timer9",
3331         .class          = &omap44xx_timer_hwmod_class,
3332         .clkdm_name     = "l4_per_clkdm",
3333         .mpu_irqs       = omap44xx_timer9_irqs,
3334         .main_clk       = "timer9_fck",
3335         .prcm = {
3336                 .omap4 = {
3337                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
3338                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
3339                         .modulemode   = MODULEMODE_SWCTRL,
3340                 },
3341         },
3342         .dev_attr       = &capability_pwm_dev_attr,
3343 };
3344
3345 /* timer10 */
3346 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
3347         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
3348         { .irq = -1 }
3349 };
3350
3351 static struct omap_hwmod omap44xx_timer10_hwmod = {
3352         .name           = "timer10",
3353         .class          = &omap44xx_timer_1ms_hwmod_class,
3354         .clkdm_name     = "l4_per_clkdm",
3355         .mpu_irqs       = omap44xx_timer10_irqs,
3356         .main_clk       = "timer10_fck",
3357         .prcm = {
3358                 .omap4 = {
3359                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
3360                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
3361                         .modulemode   = MODULEMODE_SWCTRL,
3362                 },
3363         },
3364         .dev_attr       = &capability_pwm_dev_attr,
3365 };
3366
3367 /* timer11 */
3368 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
3369         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
3370         { .irq = -1 }
3371 };
3372
3373 static struct omap_hwmod omap44xx_timer11_hwmod = {
3374         .name           = "timer11",
3375         .class          = &omap44xx_timer_hwmod_class,
3376         .clkdm_name     = "l4_per_clkdm",
3377         .mpu_irqs       = omap44xx_timer11_irqs,
3378         .main_clk       = "timer11_fck",
3379         .prcm = {
3380                 .omap4 = {
3381                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
3382                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
3383                         .modulemode   = MODULEMODE_SWCTRL,
3384                 },
3385         },
3386         .dev_attr       = &capability_pwm_dev_attr,
3387 };
3388
3389 /*
3390  * 'uart' class
3391  * universal asynchronous receiver/transmitter (uart)
3392  */
3393
3394 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
3395         .rev_offs       = 0x0050,
3396         .sysc_offs      = 0x0054,
3397         .syss_offs      = 0x0058,
3398         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3399                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3400                            SYSS_HAS_RESET_STATUS),
3401         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3402                            SIDLE_SMART_WKUP),
3403         .sysc_fields    = &omap_hwmod_sysc_type1,
3404 };
3405
3406 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
3407         .name   = "uart",
3408         .sysc   = &omap44xx_uart_sysc,
3409 };
3410
3411 /* uart1 */
3412 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
3413         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
3414         { .irq = -1 }
3415 };
3416
3417 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
3418         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
3419         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
3420         { .dma_req = -1 }
3421 };
3422
3423 static struct omap_hwmod omap44xx_uart1_hwmod = {
3424         .name           = "uart1",
3425         .class          = &omap44xx_uart_hwmod_class,
3426         .clkdm_name     = "l4_per_clkdm",
3427         .mpu_irqs       = omap44xx_uart1_irqs,
3428         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
3429         .main_clk       = "uart1_fck",
3430         .prcm = {
3431                 .omap4 = {
3432                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
3433                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
3434                         .modulemode   = MODULEMODE_SWCTRL,
3435                 },
3436         },
3437 };
3438
3439 /* uart2 */
3440 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
3441         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
3442         { .irq = -1 }
3443 };
3444
3445 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
3446         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
3447         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
3448         { .dma_req = -1 }
3449 };
3450
3451 static struct omap_hwmod omap44xx_uart2_hwmod = {
3452         .name           = "uart2",
3453         .class          = &omap44xx_uart_hwmod_class,
3454         .clkdm_name     = "l4_per_clkdm",
3455         .mpu_irqs       = omap44xx_uart2_irqs,
3456         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
3457         .main_clk       = "uart2_fck",
3458         .prcm = {
3459                 .omap4 = {
3460                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
3461                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
3462                         .modulemode   = MODULEMODE_SWCTRL,
3463                 },
3464         },
3465 };
3466
3467 /* uart3 */
3468 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
3469         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
3470         { .irq = -1 }
3471 };
3472
3473 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
3474         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
3475         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
3476         { .dma_req = -1 }
3477 };
3478
3479 static struct omap_hwmod omap44xx_uart3_hwmod = {
3480         .name           = "uart3",
3481         .class          = &omap44xx_uart_hwmod_class,
3482         .clkdm_name     = "l4_per_clkdm",
3483         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3484         .mpu_irqs       = omap44xx_uart3_irqs,
3485         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
3486         .main_clk       = "uart3_fck",
3487         .prcm = {
3488                 .omap4 = {
3489                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
3490                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
3491                         .modulemode   = MODULEMODE_SWCTRL,
3492                 },
3493         },
3494 };
3495
3496 /* uart4 */
3497 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
3498         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
3499         { .irq = -1 }
3500 };
3501
3502 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
3503         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
3504         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
3505         { .dma_req = -1 }
3506 };
3507
3508 static struct omap_hwmod omap44xx_uart4_hwmod = {
3509         .name           = "uart4",
3510         .class          = &omap44xx_uart_hwmod_class,
3511         .clkdm_name     = "l4_per_clkdm",
3512         .mpu_irqs       = omap44xx_uart4_irqs,
3513         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
3514         .main_clk       = "uart4_fck",
3515         .prcm = {
3516                 .omap4 = {
3517                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
3518                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
3519                         .modulemode   = MODULEMODE_SWCTRL,
3520                 },
3521         },
3522 };
3523
3524 /*
3525  * 'usb_host_fs' class
3526  * full-speed usb host controller
3527  */
3528
3529 /* The IP is not compliant to type1 / type2 scheme */
3530 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
3531         .midle_shift    = 4,
3532         .sidle_shift    = 2,
3533         .srst_shift     = 1,
3534 };
3535
3536 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
3537         .rev_offs       = 0x0000,
3538         .sysc_offs      = 0x0210,
3539         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3540                            SYSC_HAS_SOFTRESET),
3541         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3542                            SIDLE_SMART_WKUP),
3543         .sysc_fields    = &omap_hwmod_sysc_type_usb_host_fs,
3544 };
3545
3546 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
3547         .name   = "usb_host_fs",
3548         .sysc   = &omap44xx_usb_host_fs_sysc,
3549 };
3550
3551 /* usb_host_fs */
3552 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs[] = {
3553         { .name = "std", .irq = 89 + OMAP44XX_IRQ_GIC_START },
3554         { .name = "smi", .irq = 90 + OMAP44XX_IRQ_GIC_START },
3555         { .irq = -1 }
3556 };
3557
3558 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
3559         .name           = "usb_host_fs",
3560         .class          = &omap44xx_usb_host_fs_hwmod_class,
3561         .clkdm_name     = "l3_init_clkdm",
3562         .mpu_irqs       = omap44xx_usb_host_fs_irqs,
3563         .main_clk       = "usb_host_fs_fck",
3564         .prcm = {
3565                 .omap4 = {
3566                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
3567                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
3568                         .modulemode   = MODULEMODE_SWCTRL,
3569                 },
3570         },
3571 };
3572
3573 /*
3574  * 'usb_host_hs' class
3575  * high-speed multi-port usb host controller
3576  */
3577
3578 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
3579         .rev_offs       = 0x0000,
3580         .sysc_offs      = 0x0010,
3581         .syss_offs      = 0x0014,
3582         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3583                            SYSC_HAS_SOFTRESET),
3584         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3585                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3586                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3587         .sysc_fields    = &omap_hwmod_sysc_type2,
3588 };
3589
3590 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
3591         .name   = "usb_host_hs",
3592         .sysc   = &omap44xx_usb_host_hs_sysc,
3593 };
3594
3595 /* usb_host_hs */
3596 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
3597         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
3598         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
3599         { .irq = -1 }
3600 };
3601
3602 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
3603         .name           = "usb_host_hs",
3604         .class          = &omap44xx_usb_host_hs_hwmod_class,
3605         .clkdm_name     = "l3_init_clkdm",
3606         .main_clk       = "usb_host_hs_fck",
3607         .prcm = {
3608                 .omap4 = {
3609                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
3610                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
3611                         .modulemode   = MODULEMODE_SWCTRL,
3612                 },
3613         },
3614         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
3615
3616         /*
3617          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3618          * id: i660
3619          *
3620          * Description:
3621          * In the following configuration :
3622          * - USBHOST module is set to smart-idle mode
3623          * - PRCM asserts idle_req to the USBHOST module ( This typically
3624          *   happens when the system is going to a low power mode : all ports
3625          *   have been suspended, the master part of the USBHOST module has
3626          *   entered the standby state, and SW has cut the functional clocks)
3627          * - an USBHOST interrupt occurs before the module is able to answer
3628          *   idle_ack, typically a remote wakeup IRQ.
3629          * Then the USB HOST module will enter a deadlock situation where it
3630          * is no more accessible nor functional.
3631          *
3632          * Workaround:
3633          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3634          */
3635
3636         /*
3637          * Errata: USB host EHCI may stall when entering smart-standby mode
3638          * Id: i571
3639          *
3640          * Description:
3641          * When the USBHOST module is set to smart-standby mode, and when it is
3642          * ready to enter the standby state (i.e. all ports are suspended and
3643          * all attached devices are in suspend mode), then it can wrongly assert
3644          * the Mstandby signal too early while there are still some residual OCP
3645          * transactions ongoing. If this condition occurs, the internal state
3646          * machine may go to an undefined state and the USB link may be stuck
3647          * upon the next resume.
3648          *
3649          * Workaround:
3650          * Don't use smart standby; use only force standby,
3651          * hence HWMOD_SWSUP_MSTANDBY
3652          */
3653
3654         /*
3655          * During system boot; If the hwmod framework resets the module
3656          * the module will have smart idle settings; which can lead to deadlock
3657          * (above Errata Id:i660); so, dont reset the module during boot;
3658          * Use HWMOD_INIT_NO_RESET.
3659          */
3660
3661         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3662                           HWMOD_INIT_NO_RESET,
3663 };
3664
3665 /*
3666  * 'usb_otg_hs' class
3667  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3668  */
3669
3670 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3671         .rev_offs       = 0x0400,
3672         .sysc_offs      = 0x0404,
3673         .syss_offs      = 0x0408,
3674         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3675                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3676                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3677         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3678                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3679                            MSTANDBY_SMART),
3680         .sysc_fields    = &omap_hwmod_sysc_type1,
3681 };
3682
3683 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3684         .name   = "usb_otg_hs",
3685         .sysc   = &omap44xx_usb_otg_hs_sysc,
3686 };
3687
3688 /* usb_otg_hs */
3689 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
3690         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
3691         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
3692         { .irq = -1 }
3693 };
3694
3695 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3696         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3697 };
3698
3699 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3700         .name           = "usb_otg_hs",
3701         .class          = &omap44xx_usb_otg_hs_hwmod_class,
3702         .clkdm_name     = "l3_init_clkdm",
3703         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3704         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
3705         .main_clk       = "usb_otg_hs_ick",
3706         .prcm = {
3707                 .omap4 = {
3708                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3709                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3710                         .modulemode   = MODULEMODE_HWCTRL,
3711                 },
3712         },
3713         .opt_clks       = usb_otg_hs_opt_clks,
3714         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
3715 };
3716
3717 /*
3718  * 'usb_tll_hs' class
3719  * usb_tll_hs module is the adapter on the usb_host_hs ports
3720  */
3721
3722 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3723         .rev_offs       = 0x0000,
3724         .sysc_offs      = 0x0010,
3725         .syss_offs      = 0x0014,
3726         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3727                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3728                            SYSC_HAS_AUTOIDLE),
3729         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3730         .sysc_fields    = &omap_hwmod_sysc_type1,
3731 };
3732
3733 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3734         .name   = "usb_tll_hs",
3735         .sysc   = &omap44xx_usb_tll_hs_sysc,
3736 };
3737
3738 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
3739         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
3740         { .irq = -1 }
3741 };
3742
3743 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3744         .name           = "usb_tll_hs",
3745         .class          = &omap44xx_usb_tll_hs_hwmod_class,
3746         .clkdm_name     = "l3_init_clkdm",
3747         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
3748         .main_clk       = "usb_tll_hs_ick",
3749         .prcm = {
3750                 .omap4 = {
3751                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3752                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3753                         .modulemode   = MODULEMODE_HWCTRL,
3754                 },
3755         },
3756 };
3757
3758 /*
3759  * 'wd_timer' class
3760  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3761  * overflow condition
3762  */
3763
3764 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3765         .rev_offs       = 0x0000,
3766         .sysc_offs      = 0x0010,
3767         .syss_offs      = 0x0014,
3768         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3769                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3770         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3771                            SIDLE_SMART_WKUP),
3772         .sysc_fields    = &omap_hwmod_sysc_type1,
3773 };
3774
3775 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3776         .name           = "wd_timer",
3777         .sysc           = &omap44xx_wd_timer_sysc,
3778         .pre_shutdown   = &omap2_wd_timer_disable,
3779         .reset          = &omap2_wd_timer_reset,
3780 };
3781
3782 /* wd_timer2 */
3783 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
3784         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
3785         { .irq = -1 }
3786 };
3787
3788 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3789         .name           = "wd_timer2",
3790         .class          = &omap44xx_wd_timer_hwmod_class,
3791         .clkdm_name     = "l4_wkup_clkdm",
3792         .mpu_irqs       = omap44xx_wd_timer2_irqs,
3793         .main_clk       = "wd_timer2_fck",
3794         .prcm = {
3795                 .omap4 = {
3796                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3797                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3798                         .modulemode   = MODULEMODE_SWCTRL,
3799                 },
3800         },
3801 };
3802
3803 /* wd_timer3 */
3804 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
3805         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
3806         { .irq = -1 }
3807 };
3808
3809 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3810         .name           = "wd_timer3",
3811         .class          = &omap44xx_wd_timer_hwmod_class,
3812         .clkdm_name     = "abe_clkdm",
3813         .mpu_irqs       = omap44xx_wd_timer3_irqs,
3814         .main_clk       = "wd_timer3_fck",
3815         .prcm = {
3816                 .omap4 = {
3817                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3818                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3819                         .modulemode   = MODULEMODE_SWCTRL,
3820                 },
3821         },
3822 };
3823
3824
3825 /*
3826  * interfaces
3827  */
3828
3829 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs[] = {
3830         {
3831                 .pa_start       = 0x4a204000,
3832                 .pa_end         = 0x4a2040ff,
3833                 .flags          = ADDR_TYPE_RT
3834         },
3835         { }
3836 };
3837
3838 /* c2c -> c2c_target_fw */
3839 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw = {
3840         .master         = &omap44xx_c2c_hwmod,
3841         .slave          = &omap44xx_c2c_target_fw_hwmod,
3842         .clk            = "div_core_ck",
3843         .addr           = omap44xx_c2c_target_fw_addrs,
3844         .user           = OCP_USER_MPU,
3845 };
3846
3847 /* l4_cfg -> c2c_target_fw */
3848 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw = {
3849         .master         = &omap44xx_l4_cfg_hwmod,
3850         .slave          = &omap44xx_c2c_target_fw_hwmod,
3851         .clk            = "l4_div_ck",
3852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3853 };
3854
3855 /* l3_main_1 -> dmm */
3856 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3857         .master         = &omap44xx_l3_main_1_hwmod,
3858         .slave          = &omap44xx_dmm_hwmod,
3859         .clk            = "l3_div_ck",
3860         .user           = OCP_USER_SDMA,
3861 };
3862
3863 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
3864         {
3865                 .pa_start       = 0x4e000000,
3866                 .pa_end         = 0x4e0007ff,
3867                 .flags          = ADDR_TYPE_RT
3868         },
3869         { }
3870 };
3871
3872 /* mpu -> dmm */
3873 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3874         .master         = &omap44xx_mpu_hwmod,
3875         .slave          = &omap44xx_dmm_hwmod,
3876         .clk            = "l3_div_ck",
3877         .addr           = omap44xx_dmm_addrs,
3878         .user           = OCP_USER_MPU,
3879 };
3880
3881 /* c2c -> emif_fw */
3882 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw = {
3883         .master         = &omap44xx_c2c_hwmod,
3884         .slave          = &omap44xx_emif_fw_hwmod,
3885         .clk            = "div_core_ck",
3886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3887 };
3888
3889 /* dmm -> emif_fw */
3890 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
3891         .master         = &omap44xx_dmm_hwmod,
3892         .slave          = &omap44xx_emif_fw_hwmod,
3893         .clk            = "l3_div_ck",
3894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3895 };
3896
3897 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
3898         {
3899                 .pa_start       = 0x4a20c000,
3900                 .pa_end         = 0x4a20c0ff,
3901                 .flags          = ADDR_TYPE_RT
3902         },
3903         { }
3904 };
3905
3906 /* l4_cfg -> emif_fw */
3907 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
3908         .master         = &omap44xx_l4_cfg_hwmod,
3909         .slave          = &omap44xx_emif_fw_hwmod,
3910         .clk            = "l4_div_ck",
3911         .addr           = omap44xx_emif_fw_addrs,
3912         .user           = OCP_USER_MPU,
3913 };
3914
3915 /* iva -> l3_instr */
3916 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3917         .master         = &omap44xx_iva_hwmod,
3918         .slave          = &omap44xx_l3_instr_hwmod,
3919         .clk            = "l3_div_ck",
3920         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3921 };
3922
3923 /* l3_main_3 -> l3_instr */
3924 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3925         .master         = &omap44xx_l3_main_3_hwmod,
3926         .slave          = &omap44xx_l3_instr_hwmod,
3927         .clk            = "l3_div_ck",
3928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3929 };
3930
3931 /* ocp_wp_noc -> l3_instr */
3932 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3933         .master         = &omap44xx_ocp_wp_noc_hwmod,
3934         .slave          = &omap44xx_l3_instr_hwmod,
3935         .clk            = "l3_div_ck",
3936         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3937 };
3938
3939 /* dsp -> l3_main_1 */
3940 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3941         .master         = &omap44xx_dsp_hwmod,
3942         .slave          = &omap44xx_l3_main_1_hwmod,
3943         .clk            = "l3_div_ck",
3944         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3945 };
3946
3947 /* dss -> l3_main_1 */
3948 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3949         .master         = &omap44xx_dss_hwmod,
3950         .slave          = &omap44xx_l3_main_1_hwmod,
3951         .clk            = "l3_div_ck",
3952         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3953 };
3954
3955 /* l3_main_2 -> l3_main_1 */
3956 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3957         .master         = &omap44xx_l3_main_2_hwmod,
3958         .slave          = &omap44xx_l3_main_1_hwmod,
3959         .clk            = "l3_div_ck",
3960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3961 };
3962
3963 /* l4_cfg -> l3_main_1 */
3964 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3965         .master         = &omap44xx_l4_cfg_hwmod,
3966         .slave          = &omap44xx_l3_main_1_hwmod,
3967         .clk            = "l4_div_ck",
3968         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3969 };
3970
3971 /* mmc1 -> l3_main_1 */
3972 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3973         .master         = &omap44xx_mmc1_hwmod,
3974         .slave          = &omap44xx_l3_main_1_hwmod,
3975         .clk            = "l3_div_ck",
3976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3977 };
3978
3979 /* mmc2 -> l3_main_1 */
3980 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3981         .master         = &omap44xx_mmc2_hwmod,
3982         .slave          = &omap44xx_l3_main_1_hwmod,
3983         .clk            = "l3_div_ck",
3984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3985 };
3986
3987 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
3988         {
3989                 .pa_start       = 0x44000000,
3990                 .pa_end         = 0x44000fff,
3991                 .flags          = ADDR_TYPE_RT
3992         },
3993         { }
3994 };
3995
3996 /* mpu -> l3_main_1 */
3997 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3998         .master         = &omap44xx_mpu_hwmod,
3999         .slave          = &omap44xx_l3_main_1_hwmod,
4000         .clk            = "l3_div_ck",
4001         .addr           = omap44xx_l3_main_1_addrs,
4002         .user           = OCP_USER_MPU,
4003 };
4004
4005 /* c2c_target_fw -> l3_main_2 */
4006 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2 = {
4007         .master         = &omap44xx_c2c_target_fw_hwmod,
4008         .slave          = &omap44xx_l3_main_2_hwmod,
4009         .clk            = "l3_div_ck",
4010         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4011 };
4012
4013 /* debugss -> l3_main_2 */
4014 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
4015         .master         = &omap44xx_debugss_hwmod,
4016         .slave          = &omap44xx_l3_main_2_hwmod,
4017         .clk            = "dbgclk_mux_ck",
4018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4019 };
4020
4021 /* dma_system -> l3_main_2 */
4022 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
4023         .master         = &omap44xx_dma_system_hwmod,
4024         .slave          = &omap44xx_l3_main_2_hwmod,
4025         .clk            = "l3_div_ck",
4026         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4027 };
4028
4029 /* fdif -> l3_main_2 */
4030 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
4031         .master         = &omap44xx_fdif_hwmod,
4032         .slave          = &omap44xx_l3_main_2_hwmod,
4033         .clk            = "l3_div_ck",
4034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4035 };
4036
4037 /* gpu -> l3_main_2 */
4038 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
4039         .master         = &omap44xx_gpu_hwmod,
4040         .slave          = &omap44xx_l3_main_2_hwmod,
4041         .clk            = "l3_div_ck",
4042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4043 };
4044
4045 /* hsi -> l3_main_2 */
4046 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
4047         .master         = &omap44xx_hsi_hwmod,
4048         .slave          = &omap44xx_l3_main_2_hwmod,
4049         .clk            = "l3_div_ck",
4050         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4051 };
4052
4053 /* ipu -> l3_main_2 */
4054 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
4055         .master         = &omap44xx_ipu_hwmod,
4056         .slave          = &omap44xx_l3_main_2_hwmod,
4057         .clk            = "l3_div_ck",
4058         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4059 };
4060
4061 /* iss -> l3_main_2 */
4062 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
4063         .master         = &omap44xx_iss_hwmod,
4064         .slave          = &omap44xx_l3_main_2_hwmod,
4065         .clk            = "l3_div_ck",
4066         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4067 };
4068
4069 /* iva -> l3_main_2 */
4070 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
4071         .master         = &omap44xx_iva_hwmod,
4072         .slave          = &omap44xx_l3_main_2_hwmod,
4073         .clk            = "l3_div_ck",
4074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4075 };
4076
4077 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
4078         {
4079                 .pa_start       = 0x44800000,
4080                 .pa_end         = 0x44801fff,
4081                 .flags          = ADDR_TYPE_RT
4082         },
4083         { }
4084 };
4085
4086 /* l3_main_1 -> l3_main_2 */
4087 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
4088         .master         = &omap44xx_l3_main_1_hwmod,
4089         .slave          = &omap44xx_l3_main_2_hwmod,
4090         .clk            = "l3_div_ck",
4091         .addr           = omap44xx_l3_main_2_addrs,
4092         .user           = OCP_USER_MPU,
4093 };
4094
4095 /* l4_cfg -> l3_main_2 */
4096 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
4097         .master         = &omap44xx_l4_cfg_hwmod,
4098         .slave          = &omap44xx_l3_main_2_hwmod,
4099         .clk            = "l4_div_ck",
4100         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4101 };
4102
4103 /* usb_host_fs -> l3_main_2 */
4104 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
4105         .master         = &omap44xx_usb_host_fs_hwmod,
4106         .slave          = &omap44xx_l3_main_2_hwmod,
4107         .clk            = "l3_div_ck",
4108         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4109 };
4110
4111 /* usb_host_hs -> l3_main_2 */
4112 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4113         .master         = &omap44xx_usb_host_hs_hwmod,
4114         .slave          = &omap44xx_l3_main_2_hwmod,
4115         .clk            = "l3_div_ck",
4116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4117 };
4118
4119 /* usb_otg_hs -> l3_main_2 */
4120 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
4121         .master         = &omap44xx_usb_otg_hs_hwmod,
4122         .slave          = &omap44xx_l3_main_2_hwmod,
4123         .clk            = "l3_div_ck",
4124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4125 };
4126
4127 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
4128         {
4129                 .pa_start       = 0x45000000,
4130                 .pa_end         = 0x45000fff,
4131                 .flags          = ADDR_TYPE_RT
4132         },
4133         { }
4134 };
4135
4136 /* l3_main_1 -> l3_main_3 */
4137 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
4138         .master         = &omap44xx_l3_main_1_hwmod,
4139         .slave          = &omap44xx_l3_main_3_hwmod,
4140         .clk            = "l3_div_ck",
4141         .addr           = omap44xx_l3_main_3_addrs,
4142         .user           = OCP_USER_MPU,
4143 };
4144
4145 /* l3_main_2 -> l3_main_3 */
4146 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
4147         .master         = &omap44xx_l3_main_2_hwmod,
4148         .slave          = &omap44xx_l3_main_3_hwmod,
4149         .clk            = "l3_div_ck",
4150         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4151 };
4152
4153 /* l4_cfg -> l3_main_3 */
4154 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
4155         .master         = &omap44xx_l4_cfg_hwmod,
4156         .slave          = &omap44xx_l3_main_3_hwmod,
4157         .clk            = "l4_div_ck",
4158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4159 };
4160
4161 /* aess -> l4_abe */
4162 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
4163         .master         = &omap44xx_aess_hwmod,
4164         .slave          = &omap44xx_l4_abe_hwmod,
4165         .clk            = "ocp_abe_iclk",
4166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4167 };
4168
4169 /* dsp -> l4_abe */
4170 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
4171         .master         = &omap44xx_dsp_hwmod,
4172         .slave          = &omap44xx_l4_abe_hwmod,
4173         .clk            = "ocp_abe_iclk",
4174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4175 };
4176
4177 /* l3_main_1 -> l4_abe */
4178 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
4179         .master         = &omap44xx_l3_main_1_hwmod,
4180         .slave          = &omap44xx_l4_abe_hwmod,
4181         .clk            = "l3_div_ck",
4182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4183 };
4184
4185 /* mpu -> l4_abe */
4186 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
4187         .master         = &omap44xx_mpu_hwmod,
4188         .slave          = &omap44xx_l4_abe_hwmod,
4189         .clk            = "ocp_abe_iclk",
4190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4191 };
4192
4193 /* l3_main_1 -> l4_cfg */
4194 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
4195         .master         = &omap44xx_l3_main_1_hwmod,
4196         .slave          = &omap44xx_l4_cfg_hwmod,
4197         .clk            = "l3_div_ck",
4198         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4199 };
4200
4201 /* l3_main_2 -> l4_per */
4202 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
4203         .master         = &omap44xx_l3_main_2_hwmod,
4204         .slave          = &omap44xx_l4_per_hwmod,
4205         .clk            = "l3_div_ck",
4206         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4207 };
4208
4209 /* l4_cfg -> l4_wkup */
4210 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
4211         .master         = &omap44xx_l4_cfg_hwmod,
4212         .slave          = &omap44xx_l4_wkup_hwmod,
4213         .clk            = "l4_div_ck",
4214         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4215 };
4216
4217 /* mpu -> mpu_private */
4218 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
4219         .master         = &omap44xx_mpu_hwmod,
4220         .slave          = &omap44xx_mpu_private_hwmod,
4221         .clk            = "l3_div_ck",
4222         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4223 };
4224
4225 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs[] = {
4226         {
4227                 .pa_start       = 0x4a102000,
4228                 .pa_end         = 0x4a10207f,
4229                 .flags          = ADDR_TYPE_RT
4230         },
4231         { }
4232 };
4233
4234 /* l4_cfg -> ocp_wp_noc */
4235 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4236         .master         = &omap44xx_l4_cfg_hwmod,
4237         .slave          = &omap44xx_ocp_wp_noc_hwmod,
4238         .clk            = "l4_div_ck",
4239         .addr           = omap44xx_ocp_wp_noc_addrs,
4240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4241 };
4242
4243 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4244         {
4245                 .pa_start       = 0x401f1000,
4246                 .pa_end         = 0x401f13ff,
4247                 .flags          = ADDR_TYPE_RT
4248         },
4249         { }
4250 };
4251
4252 /* l4_abe -> aess */
4253 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4254         .master         = &omap44xx_l4_abe_hwmod,
4255         .slave          = &omap44xx_aess_hwmod,
4256         .clk            = "ocp_abe_iclk",
4257         .addr           = omap44xx_aess_addrs,
4258         .user           = OCP_USER_MPU,
4259 };
4260
4261 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4262         {
4263                 .pa_start       = 0x490f1000,
4264                 .pa_end         = 0x490f13ff,
4265                 .flags          = ADDR_TYPE_RT
4266         },
4267         { }
4268 };
4269
4270 /* l4_abe -> aess (dma) */
4271 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
4272         .master         = &omap44xx_l4_abe_hwmod,
4273         .slave          = &omap44xx_aess_hwmod,
4274         .clk            = "ocp_abe_iclk",
4275         .addr           = omap44xx_aess_dma_addrs,
4276         .user           = OCP_USER_SDMA,
4277 };
4278
4279 /* l3_main_2 -> c2c */
4280 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
4281         .master         = &omap44xx_l3_main_2_hwmod,
4282         .slave          = &omap44xx_c2c_hwmod,
4283         .clk            = "l3_div_ck",
4284         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4285 };
4286
4287 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
4288         {
4289                 .pa_start       = 0x4a304000,
4290                 .pa_end         = 0x4a30401f,
4291                 .flags          = ADDR_TYPE_RT
4292         },
4293         { }
4294 };
4295
4296 /* l4_wkup -> counter_32k */
4297 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
4298         .master         = &omap44xx_l4_wkup_hwmod,
4299         .slave          = &omap44xx_counter_32k_hwmod,
4300         .clk            = "l4_wkup_clk_mux_ck",
4301         .addr           = omap44xx_counter_32k_addrs,
4302         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4303 };
4304
4305 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
4306         {
4307                 .pa_start       = 0x4a002000,
4308                 .pa_end         = 0x4a0027ff,
4309                 .flags          = ADDR_TYPE_RT
4310         },
4311         { }
4312 };
4313
4314 /* l4_cfg -> ctrl_module_core */
4315 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
4316         .master         = &omap44xx_l4_cfg_hwmod,
4317         .slave          = &omap44xx_ctrl_module_core_hwmod,
4318         .clk            = "l4_div_ck",
4319         .addr           = omap44xx_ctrl_module_core_addrs,
4320         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4321 };
4322
4323 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
4324         {
4325                 .pa_start       = 0x4a100000,
4326                 .pa_end         = 0x4a1007ff,
4327                 .flags          = ADDR_TYPE_RT
4328         },
4329         { }
4330 };
4331
4332 /* l4_cfg -> ctrl_module_pad_core */
4333 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
4334         .master         = &omap44xx_l4_cfg_hwmod,
4335         .slave          = &omap44xx_ctrl_module_pad_core_hwmod,
4336         .clk            = "l4_div_ck",
4337         .addr           = omap44xx_ctrl_module_pad_core_addrs,
4338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4339 };
4340
4341 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
4342         {
4343                 .pa_start       = 0x4a30c000,
4344                 .pa_end         = 0x4a30c7ff,
4345                 .flags          = ADDR_TYPE_RT
4346         },
4347         { }
4348 };
4349
4350 /* l4_wkup -> ctrl_module_wkup */
4351 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
4352         .master         = &omap44xx_l4_wkup_hwmod,
4353         .slave          = &omap44xx_ctrl_module_wkup_hwmod,
4354         .clk            = "l4_wkup_clk_mux_ck",
4355         .addr           = omap44xx_ctrl_module_wkup_addrs,
4356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4357 };
4358
4359 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
4360         {
4361                 .pa_start       = 0x4a31e000,
4362                 .pa_end         = 0x4a31e7ff,
4363                 .flags          = ADDR_TYPE_RT
4364         },
4365         { }
4366 };
4367
4368 /* l4_wkup -> ctrl_module_pad_wkup */
4369 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
4370         .master         = &omap44xx_l4_wkup_hwmod,
4371         .slave          = &omap44xx_ctrl_module_pad_wkup_hwmod,
4372         .clk            = "l4_wkup_clk_mux_ck",
4373         .addr           = omap44xx_ctrl_module_pad_wkup_addrs,
4374         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4375 };
4376
4377 static struct omap_hwmod_addr_space omap44xx_debugss_addrs[] = {
4378         {
4379                 .pa_start       = 0x54160000,
4380                 .pa_end         = 0x54167fff,
4381                 .flags          = ADDR_TYPE_RT
4382         },
4383         { }
4384 };
4385
4386 /* l3_instr -> debugss */
4387 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
4388         .master         = &omap44xx_l3_instr_hwmod,
4389         .slave          = &omap44xx_debugss_hwmod,
4390         .clk            = "l3_div_ck",
4391         .addr           = omap44xx_debugss_addrs,
4392         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4393 };
4394
4395 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
4396         {
4397                 .pa_start       = 0x4a056000,
4398                 .pa_end         = 0x4a056fff,
4399                 .flags          = ADDR_TYPE_RT
4400         },
4401         { }
4402 };
4403
4404 /* l4_cfg -> dma_system */
4405 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
4406         .master         = &omap44xx_l4_cfg_hwmod,
4407         .slave          = &omap44xx_dma_system_hwmod,
4408         .clk            = "l4_div_ck",
4409         .addr           = omap44xx_dma_system_addrs,
4410         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4411 };
4412
4413 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
4414         {
4415                 .name           = "mpu",
4416                 .pa_start       = 0x4012e000,
4417                 .pa_end         = 0x4012e07f,
4418                 .flags          = ADDR_TYPE_RT
4419         },
4420         { }
4421 };
4422
4423 /* l4_abe -> dmic */
4424 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
4425         .master         = &omap44xx_l4_abe_hwmod,
4426         .slave          = &omap44xx_dmic_hwmod,
4427         .clk            = "ocp_abe_iclk",
4428         .addr           = omap44xx_dmic_addrs,
4429         .user           = OCP_USER_MPU,
4430 };
4431
4432 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
4433         {
4434                 .name           = "dma",
4435                 .pa_start       = 0x4902e000,
4436                 .pa_end         = 0x4902e07f,
4437                 .flags          = ADDR_TYPE_RT
4438         },
4439         { }
4440 };
4441
4442 /* l4_abe -> dmic (dma) */
4443 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
4444         .master         = &omap44xx_l4_abe_hwmod,
4445         .slave          = &omap44xx_dmic_hwmod,
4446         .clk            = "ocp_abe_iclk",
4447         .addr           = omap44xx_dmic_dma_addrs,
4448         .user           = OCP_USER_SDMA,
4449 };
4450
4451 /* dsp -> iva */
4452 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
4453         .master         = &omap44xx_dsp_hwmod,
4454         .slave          = &omap44xx_iva_hwmod,
4455         .clk            = "dpll_iva_m5x2_ck",
4456         .user           = OCP_USER_DSP,
4457 };
4458
4459 /* dsp -> sl2if */
4460 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
4461         .master         = &omap44xx_dsp_hwmod,
4462         .slave          = &omap44xx_sl2if_hwmod,
4463         .clk            = "dpll_iva_m5x2_ck",
4464         .user           = OCP_USER_DSP,
4465 };
4466
4467 /* l4_cfg -> dsp */
4468 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
4469         .master         = &omap44xx_l4_cfg_hwmod,
4470         .slave          = &omap44xx_dsp_hwmod,
4471         .clk            = "l4_div_ck",
4472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4473 };
4474
4475 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
4476         {
4477                 .pa_start       = 0x58000000,
4478                 .pa_end         = 0x5800007f,
4479                 .flags          = ADDR_TYPE_RT
4480         },
4481         { }
4482 };
4483
4484 /* l3_main_2 -> dss */
4485 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
4486         .master         = &omap44xx_l3_main_2_hwmod,
4487         .slave          = &omap44xx_dss_hwmod,
4488         .clk            = "dss_fck",
4489         .addr           = omap44xx_dss_dma_addrs,
4490         .user           = OCP_USER_SDMA,
4491 };
4492
4493 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
4494         {
4495                 .pa_start       = 0x48040000,
4496                 .pa_end         = 0x4804007f,
4497                 .flags          = ADDR_TYPE_RT
4498         },
4499         { }
4500 };
4501
4502 /* l4_per -> dss */
4503 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
4504         .master         = &omap44xx_l4_per_hwmod,
4505         .slave          = &omap44xx_dss_hwmod,
4506         .clk            = "l4_div_ck",
4507         .addr           = omap44xx_dss_addrs,
4508         .user           = OCP_USER_MPU,
4509 };
4510
4511 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
4512         {
4513                 .pa_start       = 0x58001000,
4514                 .pa_end         = 0x58001fff,
4515                 .flags          = ADDR_TYPE_RT
4516         },
4517         { }
4518 };
4519
4520 /* l3_main_2 -> dss_dispc */
4521 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
4522         .master         = &omap44xx_l3_main_2_hwmod,
4523         .slave          = &omap44xx_dss_dispc_hwmod,
4524         .clk            = "dss_fck",
4525         .addr           = omap44xx_dss_dispc_dma_addrs,
4526         .user           = OCP_USER_SDMA,
4527 };
4528
4529 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
4530         {
4531                 .pa_start       = 0x48041000,
4532                 .pa_end         = 0x48041fff,
4533                 .flags          = ADDR_TYPE_RT
4534         },
4535         { }
4536 };
4537
4538 /* l4_per -> dss_dispc */
4539 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
4540         .master         = &omap44xx_l4_per_hwmod,
4541         .slave          = &omap44xx_dss_dispc_hwmod,
4542         .clk            = "l4_div_ck",
4543         .addr           = omap44xx_dss_dispc_addrs,
4544         .user           = OCP_USER_MPU,
4545 };
4546
4547 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
4548         {
4549                 .pa_start       = 0x58004000,
4550                 .pa_end         = 0x580041ff,
4551                 .flags          = ADDR_TYPE_RT
4552         },
4553         { }
4554 };
4555
4556 /* l3_main_2 -> dss_dsi1 */
4557 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
4558         .master         = &omap44xx_l3_main_2_hwmod,
4559         .slave          = &omap44xx_dss_dsi1_hwmod,
4560         .clk            = "dss_fck",
4561         .addr           = omap44xx_dss_dsi1_dma_addrs,
4562         .user           = OCP_USER_SDMA,
4563 };
4564
4565 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
4566         {
4567                 .pa_start       = 0x48044000,
4568                 .pa_end         = 0x480441ff,
4569                 .flags          = ADDR_TYPE_RT
4570         },
4571         { }
4572 };
4573
4574 /* l4_per -> dss_dsi1 */
4575 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
4576         .master         = &omap44xx_l4_per_hwmod,
4577         .slave          = &omap44xx_dss_dsi1_hwmod,
4578         .clk            = "l4_div_ck",
4579         .addr           = omap44xx_dss_dsi1_addrs,
4580         .user           = OCP_USER_MPU,
4581 };
4582
4583 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
4584         {
4585                 .pa_start       = 0x58005000,
4586                 .pa_end         = 0x580051ff,
4587                 .flags          = ADDR_TYPE_RT
4588         },
4589         { }
4590 };
4591
4592 /* l3_main_2 -> dss_dsi2 */
4593 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
4594         .master         = &omap44xx_l3_main_2_hwmod,
4595         .slave          = &omap44xx_dss_dsi2_hwmod,
4596         .clk            = "dss_fck",
4597         .addr           = omap44xx_dss_dsi2_dma_addrs,
4598         .user           = OCP_USER_SDMA,
4599 };
4600
4601 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
4602         {
4603                 .pa_start       = 0x48045000,
4604                 .pa_end         = 0x480451ff,
4605                 .flags          = ADDR_TYPE_RT
4606         },
4607         { }
4608 };
4609
4610 /* l4_per -> dss_dsi2 */
4611 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
4612         .master         = &omap44xx_l4_per_hwmod,
4613         .slave          = &omap44xx_dss_dsi2_hwmod,
4614         .clk            = "l4_div_ck",
4615         .addr           = omap44xx_dss_dsi2_addrs,
4616         .user           = OCP_USER_MPU,
4617 };
4618
4619 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
4620         {
4621                 .pa_start       = 0x58006000,
4622                 .pa_end         = 0x58006fff,
4623                 .flags          = ADDR_TYPE_RT
4624         },
4625         { }
4626 };
4627
4628 /* l3_main_2 -> dss_hdmi */
4629 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
4630         .master         = &omap44xx_l3_main_2_hwmod,
4631         .slave          = &omap44xx_dss_hdmi_hwmod,
4632         .clk            = "dss_fck",
4633         .addr           = omap44xx_dss_hdmi_dma_addrs,
4634         .user           = OCP_USER_SDMA,
4635 };
4636
4637 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
4638         {
4639                 .pa_start       = 0x48046000,
4640                 .pa_end         = 0x48046fff,
4641                 .flags          = ADDR_TYPE_RT
4642         },
4643         { }
4644 };
4645
4646 /* l4_per -> dss_hdmi */
4647 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
4648         .master         = &omap44xx_l4_per_hwmod,
4649         .slave          = &omap44xx_dss_hdmi_hwmod,
4650         .clk            = "l4_div_ck",
4651         .addr           = omap44xx_dss_hdmi_addrs,
4652         .user           = OCP_USER_MPU,
4653 };
4654
4655 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
4656         {
4657                 .pa_start       = 0x58002000,
4658                 .pa_end         = 0x580020ff,
4659                 .flags          = ADDR_TYPE_RT
4660         },
4661         { }
4662 };
4663
4664 /* l3_main_2 -> dss_rfbi */
4665 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
4666         .master         = &omap44xx_l3_main_2_hwmod,
4667         .slave          = &omap44xx_dss_rfbi_hwmod,
4668         .clk            = "dss_fck",
4669         .addr           = omap44xx_dss_rfbi_dma_addrs,
4670         .user           = OCP_USER_SDMA,
4671 };
4672
4673 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
4674         {
4675                 .pa_start       = 0x48042000,
4676                 .pa_end         = 0x480420ff,
4677                 .flags          = ADDR_TYPE_RT
4678         },
4679         { }
4680 };
4681
4682 /* l4_per -> dss_rfbi */
4683 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
4684         .master         = &omap44xx_l4_per_hwmod,
4685         .slave          = &omap44xx_dss_rfbi_hwmod,
4686         .clk            = "l4_div_ck",
4687         .addr           = omap44xx_dss_rfbi_addrs,
4688         .user           = OCP_USER_MPU,
4689 };
4690
4691 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
4692         {
4693                 .pa_start       = 0x58003000,
4694                 .pa_end         = 0x580030ff,
4695                 .flags          = ADDR_TYPE_RT
4696         },
4697         { }
4698 };
4699
4700 /* l3_main_2 -> dss_venc */
4701 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
4702         .master         = &omap44xx_l3_main_2_hwmod,
4703         .slave          = &omap44xx_dss_venc_hwmod,
4704         .clk            = "dss_fck",
4705         .addr           = omap44xx_dss_venc_dma_addrs,
4706         .user           = OCP_USER_SDMA,
4707 };
4708
4709 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
4710         {
4711                 .pa_start       = 0x48043000,
4712                 .pa_end         = 0x480430ff,
4713                 .flags          = ADDR_TYPE_RT
4714         },
4715         { }
4716 };
4717
4718 /* l4_per -> dss_venc */
4719 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
4720         .master         = &omap44xx_l4_per_hwmod,
4721         .slave          = &omap44xx_dss_venc_hwmod,
4722         .clk            = "l4_div_ck",
4723         .addr           = omap44xx_dss_venc_addrs,
4724         .user           = OCP_USER_MPU,
4725 };
4726
4727 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
4728         {
4729                 .pa_start       = 0x48078000,
4730                 .pa_end         = 0x48078fff,
4731                 .flags          = ADDR_TYPE_RT
4732         },
4733         { }
4734 };
4735
4736 /* l4_per -> elm */
4737 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
4738         .master         = &omap44xx_l4_per_hwmod,
4739         .slave          = &omap44xx_elm_hwmod,
4740         .clk            = "l4_div_ck",
4741         .addr           = omap44xx_elm_addrs,
4742         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4743 };
4744
4745 static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = {
4746         {
4747                 .pa_start       = 0x4c000000,
4748                 .pa_end         = 0x4c0000ff,
4749                 .flags          = ADDR_TYPE_RT
4750         },
4751         { }
4752 };
4753
4754 /* emif_fw -> emif1 */
4755 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = {
4756         .master         = &omap44xx_emif_fw_hwmod,
4757         .slave          = &omap44xx_emif1_hwmod,
4758         .clk            = "l3_div_ck",
4759         .addr           = omap44xx_emif1_addrs,
4760         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4761 };
4762
4763 static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = {
4764         {
4765                 .pa_start       = 0x4d000000,
4766                 .pa_end         = 0x4d0000ff,
4767                 .flags          = ADDR_TYPE_RT
4768         },
4769         { }
4770 };
4771
4772 /* emif_fw -> emif2 */
4773 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = {
4774         .master         = &omap44xx_emif_fw_hwmod,
4775         .slave          = &omap44xx_emif2_hwmod,
4776         .clk            = "l3_div_ck",
4777         .addr           = omap44xx_emif2_addrs,
4778         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4779 };
4780
4781 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
4782         {
4783                 .pa_start       = 0x4a10a000,
4784                 .pa_end         = 0x4a10a1ff,
4785                 .flags          = ADDR_TYPE_RT
4786         },
4787         { }
4788 };
4789
4790 /* l4_cfg -> fdif */
4791 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
4792         .master         = &omap44xx_l4_cfg_hwmod,
4793         .slave          = &omap44xx_fdif_hwmod,
4794         .clk            = "l4_div_ck",
4795         .addr           = omap44xx_fdif_addrs,
4796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4797 };
4798
4799 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
4800         {
4801                 .pa_start       = 0x4a310000,
4802                 .pa_end         = 0x4a3101ff,
4803                 .flags          = ADDR_TYPE_RT
4804         },
4805         { }
4806 };
4807
4808 /* l4_wkup -> gpio1 */
4809 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
4810         .master         = &omap44xx_l4_wkup_hwmod,
4811         .slave          = &omap44xx_gpio1_hwmod,
4812         .clk            = "l4_wkup_clk_mux_ck",
4813         .addr           = omap44xx_gpio1_addrs,
4814         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4815 };
4816
4817 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
4818         {
4819                 .pa_start       = 0x48055000,
4820                 .pa_end         = 0x480551ff,
4821                 .flags          = ADDR_TYPE_RT
4822         },
4823         { }
4824 };
4825
4826 /* l4_per -> gpio2 */
4827 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
4828         .master         = &omap44xx_l4_per_hwmod,
4829         .slave          = &omap44xx_gpio2_hwmod,
4830         .clk            = "l4_div_ck",
4831         .addr           = omap44xx_gpio2_addrs,
4832         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4833 };
4834
4835 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
4836         {
4837                 .pa_start       = 0x48057000,
4838                 .pa_end         = 0x480571ff,
4839                 .flags          = ADDR_TYPE_RT
4840         },
4841         { }
4842 };
4843
4844 /* l4_per -> gpio3 */
4845 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
4846         .master         = &omap44xx_l4_per_hwmod,
4847         .slave          = &omap44xx_gpio3_hwmod,
4848         .clk            = "l4_div_ck",
4849         .addr           = omap44xx_gpio3_addrs,
4850         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4851 };
4852
4853 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
4854         {
4855                 .pa_start       = 0x48059000,
4856                 .pa_end         = 0x480591ff,
4857                 .flags          = ADDR_TYPE_RT
4858         },
4859         { }
4860 };
4861
4862 /* l4_per -> gpio4 */
4863 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
4864         .master         = &omap44xx_l4_per_hwmod,
4865         .slave          = &omap44xx_gpio4_hwmod,
4866         .clk            = "l4_div_ck",
4867         .addr           = omap44xx_gpio4_addrs,
4868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4869 };
4870
4871 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
4872         {
4873                 .pa_start       = 0x4805b000,
4874                 .pa_end         = 0x4805b1ff,
4875                 .flags          = ADDR_TYPE_RT
4876         },
4877         { }
4878 };
4879
4880 /* l4_per -> gpio5 */
4881 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4882         .master         = &omap44xx_l4_per_hwmod,
4883         .slave          = &omap44xx_gpio5_hwmod,
4884         .clk            = "l4_div_ck",
4885         .addr           = omap44xx_gpio5_addrs,
4886         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4887 };
4888
4889 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
4890         {
4891                 .pa_start       = 0x4805d000,
4892                 .pa_end         = 0x4805d1ff,
4893                 .flags          = ADDR_TYPE_RT
4894         },
4895         { }
4896 };
4897
4898 /* l4_per -> gpio6 */
4899 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4900         .master         = &omap44xx_l4_per_hwmod,
4901         .slave          = &omap44xx_gpio6_hwmod,
4902         .clk            = "l4_div_ck",
4903         .addr           = omap44xx_gpio6_addrs,
4904         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4905 };
4906
4907 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = {
4908         {
4909                 .pa_start       = 0x50000000,
4910                 .pa_end         = 0x500003ff,
4911                 .flags          = ADDR_TYPE_RT
4912         },
4913         { }
4914 };
4915
4916 /* l3_main_2 -> gpmc */
4917 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4918         .master         = &omap44xx_l3_main_2_hwmod,
4919         .slave          = &omap44xx_gpmc_hwmod,
4920         .clk            = "l3_div_ck",
4921         .addr           = omap44xx_gpmc_addrs,
4922         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4923 };
4924
4925 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4926         {
4927                 .pa_start       = 0x56000000,
4928                 .pa_end         = 0x5600ffff,
4929                 .flags          = ADDR_TYPE_RT
4930         },
4931         { }
4932 };
4933
4934 /* l3_main_2 -> gpu */
4935 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4936         .master         = &omap44xx_l3_main_2_hwmod,
4937         .slave          = &omap44xx_gpu_hwmod,
4938         .clk            = "l3_div_ck",
4939         .addr           = omap44xx_gpu_addrs,
4940         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4941 };
4942
4943 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4944         {
4945                 .pa_start       = 0x480b2000,
4946                 .pa_end         = 0x480b201f,
4947                 .flags          = ADDR_TYPE_RT
4948         },
4949         { }
4950 };
4951
4952 /* l4_per -> hdq1w */
4953 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4954         .master         = &omap44xx_l4_per_hwmod,
4955         .slave          = &omap44xx_hdq1w_hwmod,
4956         .clk            = "l4_div_ck",
4957         .addr           = omap44xx_hdq1w_addrs,
4958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4959 };
4960
4961 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4962         {
4963                 .pa_start       = 0x4a058000,
4964                 .pa_end         = 0x4a05bfff,
4965                 .flags          = ADDR_TYPE_RT
4966         },
4967         { }
4968 };
4969
4970 /* l4_cfg -> hsi */
4971 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4972         .master         = &omap44xx_l4_cfg_hwmod,
4973         .slave          = &omap44xx_hsi_hwmod,
4974         .clk            = "l4_div_ck",
4975         .addr           = omap44xx_hsi_addrs,
4976         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4977 };
4978
4979 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
4980         {
4981                 .pa_start       = 0x48070000,
4982                 .pa_end         = 0x480700ff,
4983                 .flags          = ADDR_TYPE_RT
4984         },
4985         { }
4986 };
4987
4988 /* l4_per -> i2c1 */
4989 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4990         .master         = &omap44xx_l4_per_hwmod,
4991         .slave          = &omap44xx_i2c1_hwmod,
4992         .clk            = "l4_div_ck",
4993         .addr           = omap44xx_i2c1_addrs,
4994         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4995 };
4996
4997 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
4998         {
4999                 .pa_start       = 0x48072000,
5000                 .pa_end         = 0x480720ff,
5001                 .flags          = ADDR_TYPE_RT
5002         },
5003         { }
5004 };
5005
5006 /* l4_per -> i2c2 */
5007 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
5008         .master         = &omap44xx_l4_per_hwmod,
5009         .slave          = &omap44xx_i2c2_hwmod,
5010         .clk            = "l4_div_ck",
5011         .addr           = omap44xx_i2c2_addrs,
5012         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5013 };
5014
5015 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
5016         {
5017                 .pa_start       = 0x48060000,
5018                 .pa_end         = 0x480600ff,
5019                 .flags          = ADDR_TYPE_RT
5020         },
5021         { }
5022 };
5023
5024 /* l4_per -> i2c3 */
5025 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
5026         .master         = &omap44xx_l4_per_hwmod,
5027         .slave          = &omap44xx_i2c3_hwmod,
5028         .clk            = "l4_div_ck",
5029         .addr           = omap44xx_i2c3_addrs,
5030         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5031 };
5032
5033 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
5034         {
5035                 .pa_start       = 0x48350000,
5036                 .pa_end         = 0x483500ff,
5037                 .flags          = ADDR_TYPE_RT
5038         },
5039         { }
5040 };
5041
5042 /* l4_per -> i2c4 */
5043 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
5044         .master         = &omap44xx_l4_per_hwmod,
5045         .slave          = &omap44xx_i2c4_hwmod,
5046         .clk            = "l4_div_ck",
5047         .addr           = omap44xx_i2c4_addrs,
5048         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5049 };
5050
5051 /* l3_main_2 -> ipu */
5052 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
5053         .master         = &omap44xx_l3_main_2_hwmod,
5054         .slave          = &omap44xx_ipu_hwmod,
5055         .clk            = "l3_div_ck",
5056         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5057 };
5058
5059 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
5060         {
5061                 .pa_start       = 0x52000000,
5062                 .pa_end         = 0x520000ff,
5063                 .flags          = ADDR_TYPE_RT
5064         },
5065         { }
5066 };
5067
5068 /* l3_main_2 -> iss */
5069 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
5070         .master         = &omap44xx_l3_main_2_hwmod,
5071         .slave          = &omap44xx_iss_hwmod,
5072         .clk            = "l3_div_ck",
5073         .addr           = omap44xx_iss_addrs,
5074         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5075 };
5076
5077 /* iva -> sl2if */
5078 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
5079         .master         = &omap44xx_iva_hwmod,
5080         .slave          = &omap44xx_sl2if_hwmod,
5081         .clk            = "dpll_iva_m5x2_ck",
5082         .user           = OCP_USER_IVA,
5083 };
5084
5085 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
5086         {
5087                 .pa_start       = 0x5a000000,
5088                 .pa_end         = 0x5a07ffff,
5089                 .flags          = ADDR_TYPE_RT
5090         },
5091         { }
5092 };
5093
5094 /* l3_main_2 -> iva */
5095 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
5096         .master         = &omap44xx_l3_main_2_hwmod,
5097         .slave          = &omap44xx_iva_hwmod,
5098         .clk            = "l3_div_ck",
5099         .addr           = omap44xx_iva_addrs,
5100         .user           = OCP_USER_MPU,
5101 };
5102
5103 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
5104         {
5105                 .pa_start       = 0x4a31c000,
5106                 .pa_end         = 0x4a31c07f,
5107                 .flags          = ADDR_TYPE_RT
5108         },
5109         { }
5110 };
5111
5112 /* l4_wkup -> kbd */
5113 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
5114         .master         = &omap44xx_l4_wkup_hwmod,
5115         .slave          = &omap44xx_kbd_hwmod,
5116         .clk            = "l4_wkup_clk_mux_ck",
5117         .addr           = omap44xx_kbd_addrs,
5118         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5119 };
5120
5121 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
5122         {
5123                 .pa_start       = 0x4a0f4000,
5124                 .pa_end         = 0x4a0f41ff,
5125                 .flags          = ADDR_TYPE_RT
5126         },
5127         { }
5128 };
5129
5130 /* l4_cfg -> mailbox */
5131 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
5132         .master         = &omap44xx_l4_cfg_hwmod,
5133         .slave          = &omap44xx_mailbox_hwmod,
5134         .clk            = "l4_div_ck",
5135         .addr           = omap44xx_mailbox_addrs,
5136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5137 };
5138
5139 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
5140         {
5141                 .pa_start       = 0x40128000,
5142                 .pa_end         = 0x401283ff,
5143                 .flags          = ADDR_TYPE_RT
5144         },
5145         { }
5146 };
5147
5148 /* l4_abe -> mcasp */
5149 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
5150         .master         = &omap44xx_l4_abe_hwmod,
5151         .slave          = &omap44xx_mcasp_hwmod,
5152         .clk            = "ocp_abe_iclk",
5153         .addr           = omap44xx_mcasp_addrs,
5154         .user           = OCP_USER_MPU,
5155 };
5156
5157 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
5158         {
5159                 .pa_start       = 0x49028000,
5160                 .pa_end         = 0x490283ff,
5161                 .flags          = ADDR_TYPE_RT
5162         },
5163         { }
5164 };
5165
5166 /* l4_abe -> mcasp (dma) */
5167 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
5168         .master         = &omap44xx_l4_abe_hwmod,
5169         .slave          = &omap44xx_mcasp_hwmod,
5170         .clk            = "ocp_abe_iclk",
5171         .addr           = omap44xx_mcasp_dma_addrs,
5172         .user           = OCP_USER_SDMA,
5173 };
5174
5175 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
5176         {
5177                 .name           = "mpu",
5178                 .pa_start       = 0x40122000,
5179                 .pa_end         = 0x401220ff,
5180                 .flags          = ADDR_TYPE_RT
5181         },
5182         { }
5183 };
5184
5185 /* l4_abe -> mcbsp1 */
5186 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
5187         .master         = &omap44xx_l4_abe_hwmod,
5188         .slave          = &omap44xx_mcbsp1_hwmod,
5189         .clk            = "ocp_abe_iclk",
5190         .addr           = omap44xx_mcbsp1_addrs,
5191         .user           = OCP_USER_MPU,
5192 };
5193
5194 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
5195         {
5196                 .name           = "dma",
5197                 .pa_start       = 0x49022000,
5198                 .pa_end         = 0x490220ff,
5199                 .flags          = ADDR_TYPE_RT
5200         },
5201         { }
5202 };
5203
5204 /* l4_abe -> mcbsp1 (dma) */
5205 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
5206         .master         = &omap44xx_l4_abe_hwmod,
5207         .slave          = &omap44xx_mcbsp1_hwmod,
5208         .clk            = "ocp_abe_iclk",
5209         .addr           = omap44xx_mcbsp1_dma_addrs,
5210         .user           = OCP_USER_SDMA,
5211 };
5212
5213 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
5214         {
5215                 .name           = "mpu",
5216                 .pa_start       = 0x40124000,
5217                 .pa_end         = 0x401240ff,
5218                 .flags          = ADDR_TYPE_RT
5219         },
5220         { }
5221 };
5222
5223 /* l4_abe -> mcbsp2 */
5224 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
5225         .master         = &omap44xx_l4_abe_hwmod,
5226         .slave          = &omap44xx_mcbsp2_hwmod,
5227         .clk            = "ocp_abe_iclk",
5228         .addr           = omap44xx_mcbsp2_addrs,
5229         .user           = OCP_USER_MPU,
5230 };
5231
5232 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
5233         {
5234                 .name           = "dma",
5235                 .pa_start       = 0x49024000,
5236                 .pa_end         = 0x490240ff,
5237                 .flags          = ADDR_TYPE_RT
5238         },
5239         { }
5240 };
5241
5242 /* l4_abe -> mcbsp2 (dma) */
5243 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
5244         .master         = &omap44xx_l4_abe_hwmod,
5245         .slave          = &omap44xx_mcbsp2_hwmod,
5246         .clk            = "ocp_abe_iclk",
5247         .addr           = omap44xx_mcbsp2_dma_addrs,
5248         .user           = OCP_USER_SDMA,
5249 };
5250
5251 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
5252         {
5253                 .name           = "mpu",
5254                 .pa_start       = 0x40126000,
5255                 .pa_end         = 0x401260ff,
5256                 .flags          = ADDR_TYPE_RT
5257         },
5258         { }
5259 };
5260
5261 /* l4_abe -> mcbsp3 */
5262 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
5263         .master         = &omap44xx_l4_abe_hwmod,
5264         .slave          = &omap44xx_mcbsp3_hwmod,
5265         .clk            = "ocp_abe_iclk",
5266         .addr           = omap44xx_mcbsp3_addrs,
5267         .user           = OCP_USER_MPU,
5268 };
5269
5270 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
5271         {
5272                 .name           = "dma",
5273                 .pa_start       = 0x49026000,
5274                 .pa_end         = 0x490260ff,
5275                 .flags          = ADDR_TYPE_RT
5276         },
5277         { }
5278 };
5279
5280 /* l4_abe -> mcbsp3 (dma) */
5281 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
5282         .master         = &omap44xx_l4_abe_hwmod,
5283         .slave          = &omap44xx_mcbsp3_hwmod,
5284         .clk            = "ocp_abe_iclk",
5285         .addr           = omap44xx_mcbsp3_dma_addrs,
5286         .user           = OCP_USER_SDMA,
5287 };
5288
5289 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
5290         {
5291                 .pa_start       = 0x48096000,
5292                 .pa_end         = 0x480960ff,
5293                 .flags          = ADDR_TYPE_RT
5294         },
5295         { }
5296 };
5297
5298 /* l4_per -> mcbsp4 */
5299 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
5300         .master         = &omap44xx_l4_per_hwmod,
5301         .slave          = &omap44xx_mcbsp4_hwmod,
5302         .clk            = "l4_div_ck",
5303         .addr           = omap44xx_mcbsp4_addrs,
5304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5305 };
5306
5307 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
5308         {
5309                 .name           = "mpu",
5310                 .pa_start       = 0x40132000,
5311                 .pa_end         = 0x4013207f,
5312                 .flags          = ADDR_TYPE_RT
5313         },
5314         { }
5315 };
5316
5317 /* l4_abe -> mcpdm */
5318 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
5319         .master         = &omap44xx_l4_abe_hwmod,
5320         .slave          = &omap44xx_mcpdm_hwmod,
5321         .clk            = "ocp_abe_iclk",
5322         .addr           = omap44xx_mcpdm_addrs,
5323         .user           = OCP_USER_MPU,
5324 };
5325
5326 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
5327         {
5328                 .name           = "dma",
5329                 .pa_start       = 0x49032000,
5330                 .pa_end         = 0x4903207f,
5331                 .flags          = ADDR_TYPE_RT
5332         },
5333         { }
5334 };
5335
5336 /* l4_abe -> mcpdm (dma) */
5337 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
5338         .master         = &omap44xx_l4_abe_hwmod,
5339         .slave          = &omap44xx_mcpdm_hwmod,
5340         .clk            = "ocp_abe_iclk",
5341         .addr           = omap44xx_mcpdm_dma_addrs,
5342         .user           = OCP_USER_SDMA,
5343 };
5344
5345 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
5346         {
5347                 .pa_start       = 0x48098000,
5348                 .pa_end         = 0x480981ff,
5349                 .flags          = ADDR_TYPE_RT
5350         },
5351         { }
5352 };
5353
5354 /* l4_per -> mcspi1 */
5355 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
5356         .master         = &omap44xx_l4_per_hwmod,
5357         .slave          = &omap44xx_mcspi1_hwmod,
5358         .clk            = "l4_div_ck",
5359         .addr           = omap44xx_mcspi1_addrs,
5360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5361 };
5362
5363 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
5364         {
5365                 .pa_start       = 0x4809a000,
5366                 .pa_end         = 0x4809a1ff,
5367                 .flags          = ADDR_TYPE_RT
5368         },
5369         { }
5370 };
5371
5372 /* l4_per -> mcspi2 */
5373 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
5374         .master         = &omap44xx_l4_per_hwmod,
5375         .slave          = &omap44xx_mcspi2_hwmod,
5376         .clk            = "l4_div_ck",
5377         .addr           = omap44xx_mcspi2_addrs,
5378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5379 };
5380
5381 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
5382         {
5383                 .pa_start       = 0x480b8000,
5384                 .pa_end         = 0x480b81ff,
5385                 .flags          = ADDR_TYPE_RT
5386         },
5387         { }
5388 };
5389
5390 /* l4_per -> mcspi3 */
5391 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
5392         .master         = &omap44xx_l4_per_hwmod,
5393         .slave          = &omap44xx_mcspi3_hwmod,
5394         .clk            = "l4_div_ck",
5395         .addr           = omap44xx_mcspi3_addrs,
5396         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5397 };
5398
5399 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
5400         {
5401                 .pa_start       = 0x480ba000,
5402                 .pa_end         = 0x480ba1ff,
5403                 .flags          = ADDR_TYPE_RT
5404         },
5405         { }
5406 };
5407
5408 /* l4_per -> mcspi4 */
5409 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
5410         .master         = &omap44xx_l4_per_hwmod,
5411         .slave          = &omap44xx_mcspi4_hwmod,
5412         .clk            = "l4_div_ck",
5413         .addr           = omap44xx_mcspi4_addrs,
5414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5415 };
5416
5417 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
5418         {
5419                 .pa_start       = 0x4809c000,
5420                 .pa_end         = 0x4809c3ff,
5421                 .flags          = ADDR_TYPE_RT
5422         },
5423         { }
5424 };
5425
5426 /* l4_per -> mmc1 */
5427 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
5428         .master         = &omap44xx_l4_per_hwmod,
5429         .slave          = &omap44xx_mmc1_hwmod,
5430         .clk            = "l4_div_ck",
5431         .addr           = omap44xx_mmc1_addrs,
5432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5433 };
5434
5435 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
5436         {
5437                 .pa_start       = 0x480b4000,
5438                 .pa_end         = 0x480b43ff,
5439                 .flags          = ADDR_TYPE_RT
5440         },
5441         { }
5442 };
5443
5444 /* l4_per -> mmc2 */
5445 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
5446         .master         = &omap44xx_l4_per_hwmod,
5447         .slave          = &omap44xx_mmc2_hwmod,
5448         .clk            = "l4_div_ck",
5449         .addr           = omap44xx_mmc2_addrs,
5450         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5451 };
5452
5453 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
5454         {
5455                 .pa_start       = 0x480ad000,
5456                 .pa_end         = 0x480ad3ff,
5457                 .flags          = ADDR_TYPE_RT
5458         },
5459         { }
5460 };
5461
5462 /* l4_per -> mmc3 */
5463 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
5464         .master         = &omap44xx_l4_per_hwmod,
5465         .slave          = &omap44xx_mmc3_hwmod,
5466         .clk            = "l4_div_ck",
5467         .addr           = omap44xx_mmc3_addrs,
5468         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5469 };
5470
5471 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
5472         {
5473                 .pa_start       = 0x480d1000,
5474                 .pa_end         = 0x480d13ff,
5475                 .flags          = ADDR_TYPE_RT
5476         },
5477         { }
5478 };
5479
5480 /* l4_per -> mmc4 */
5481 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
5482         .master         = &omap44xx_l4_per_hwmod,
5483         .slave          = &omap44xx_mmc4_hwmod,
5484         .clk            = "l4_div_ck",
5485         .addr           = omap44xx_mmc4_addrs,
5486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5487 };
5488
5489 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
5490         {
5491                 .pa_start       = 0x480d5000,
5492                 .pa_end         = 0x480d53ff,
5493                 .flags          = ADDR_TYPE_RT
5494         },
5495         { }
5496 };
5497
5498 /* l4_per -> mmc5 */
5499 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
5500         .master         = &omap44xx_l4_per_hwmod,
5501         .slave          = &omap44xx_mmc5_hwmod,
5502         .clk            = "l4_div_ck",
5503         .addr           = omap44xx_mmc5_addrs,
5504         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5505 };
5506
5507 /* l3_main_2 -> ocmc_ram */
5508 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
5509         .master         = &omap44xx_l3_main_2_hwmod,
5510         .slave          = &omap44xx_ocmc_ram_hwmod,
5511         .clk            = "l3_div_ck",
5512         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5513 };
5514
5515 static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
5516         {
5517                 .pa_start       = 0x4a0ad000,
5518                 .pa_end         = 0x4a0ad01f,
5519                 .flags          = ADDR_TYPE_RT
5520         },
5521         { }
5522 };
5523
5524 /* l4_cfg -> ocp2scp_usb_phy */
5525 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
5526         .master         = &omap44xx_l4_cfg_hwmod,
5527         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
5528         .clk            = "l4_div_ck",
5529         .addr           = omap44xx_ocp2scp_usb_phy_addrs,
5530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5531 };
5532
5533 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs[] = {
5534         {
5535                 .pa_start       = 0x48243000,
5536                 .pa_end         = 0x48243fff,
5537                 .flags          = ADDR_TYPE_RT
5538         },
5539         { }
5540 };
5541
5542 /* mpu_private -> prcm_mpu */
5543 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
5544         .master         = &omap44xx_mpu_private_hwmod,
5545         .slave          = &omap44xx_prcm_mpu_hwmod,
5546         .clk            = "l3_div_ck",
5547         .addr           = omap44xx_prcm_mpu_addrs,
5548         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5549 };
5550
5551 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs[] = {
5552         {
5553                 .pa_start       = 0x4a004000,
5554                 .pa_end         = 0x4a004fff,
5555                 .flags          = ADDR_TYPE_RT
5556         },
5557         { }
5558 };
5559
5560 /* l4_wkup -> cm_core_aon */
5561 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
5562         .master         = &omap44xx_l4_wkup_hwmod,
5563         .slave          = &omap44xx_cm_core_aon_hwmod,
5564         .clk            = "l4_wkup_clk_mux_ck",
5565         .addr           = omap44xx_cm_core_aon_addrs,
5566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5567 };
5568
5569 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs[] = {
5570         {
5571                 .pa_start       = 0x4a008000,
5572                 .pa_end         = 0x4a009fff,
5573                 .flags          = ADDR_TYPE_RT
5574         },
5575         { }
5576 };
5577
5578 /* l4_cfg -> cm_core */
5579 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
5580         .master         = &omap44xx_l4_cfg_hwmod,
5581         .slave          = &omap44xx_cm_core_hwmod,
5582         .clk            = "l4_div_ck",
5583         .addr           = omap44xx_cm_core_addrs,
5584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5585 };
5586
5587 static struct omap_hwmod_addr_space omap44xx_prm_addrs[] = {
5588         {
5589                 .pa_start       = 0x4a306000,
5590                 .pa_end         = 0x4a307fff,
5591                 .flags          = ADDR_TYPE_RT
5592         },
5593         { }
5594 };
5595
5596 /* l4_wkup -> prm */
5597 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
5598         .master         = &omap44xx_l4_wkup_hwmod,
5599         .slave          = &omap44xx_prm_hwmod,
5600         .clk            = "l4_wkup_clk_mux_ck",
5601         .addr           = omap44xx_prm_addrs,
5602         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5603 };
5604
5605 static struct omap_hwmod_addr_space omap44xx_scrm_addrs[] = {
5606         {
5607                 .pa_start       = 0x4a30a000,
5608                 .pa_end         = 0x4a30a7ff,
5609                 .flags          = ADDR_TYPE_RT
5610         },
5611         { }
5612 };
5613
5614 /* l4_wkup -> scrm */
5615 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
5616         .master         = &omap44xx_l4_wkup_hwmod,
5617         .slave          = &omap44xx_scrm_hwmod,
5618         .clk            = "l4_wkup_clk_mux_ck",
5619         .addr           = omap44xx_scrm_addrs,
5620         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5621 };
5622
5623 /* l3_main_2 -> sl2if */
5624 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
5625         .master         = &omap44xx_l3_main_2_hwmod,
5626         .slave          = &omap44xx_sl2if_hwmod,
5627         .clk            = "l3_div_ck",
5628         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5629 };
5630
5631 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
5632         {
5633                 .pa_start       = 0x4012c000,
5634                 .pa_end         = 0x4012c3ff,
5635                 .flags          = ADDR_TYPE_RT
5636         },
5637         { }
5638 };
5639
5640 /* l4_abe -> slimbus1 */
5641 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
5642         .master         = &omap44xx_l4_abe_hwmod,
5643         .slave          = &omap44xx_slimbus1_hwmod,
5644         .clk            = "ocp_abe_iclk",
5645         .addr           = omap44xx_slimbus1_addrs,
5646         .user           = OCP_USER_MPU,
5647 };
5648
5649 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
5650         {
5651                 .pa_start       = 0x4902c000,
5652                 .pa_end         = 0x4902c3ff,
5653                 .flags          = ADDR_TYPE_RT
5654         },
5655         { }
5656 };
5657
5658 /* l4_abe -> slimbus1 (dma) */
5659 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
5660         .master         = &omap44xx_l4_abe_hwmod,
5661         .slave          = &omap44xx_slimbus1_hwmod,
5662         .clk            = "ocp_abe_iclk",
5663         .addr           = omap44xx_slimbus1_dma_addrs,
5664         .user           = OCP_USER_SDMA,
5665 };
5666
5667 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
5668         {
5669                 .pa_start       = 0x48076000,
5670                 .pa_end         = 0x480763ff,
5671                 .flags          = ADDR_TYPE_RT
5672         },
5673         { }
5674 };
5675
5676 /* l4_per -> slimbus2 */
5677 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
5678         .master         = &omap44xx_l4_per_hwmod,
5679         .slave          = &omap44xx_slimbus2_hwmod,
5680         .clk            = "l4_div_ck",
5681         .addr           = omap44xx_slimbus2_addrs,
5682         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5683 };
5684
5685 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
5686         {
5687                 .pa_start       = 0x4a0dd000,
5688                 .pa_end         = 0x4a0dd03f,
5689                 .flags          = ADDR_TYPE_RT
5690         },
5691         { }
5692 };
5693
5694 /* l4_cfg -> smartreflex_core */
5695 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
5696         .master         = &omap44xx_l4_cfg_hwmod,
5697         .slave          = &omap44xx_smartreflex_core_hwmod,
5698         .clk            = "l4_div_ck",
5699         .addr           = omap44xx_smartreflex_core_addrs,
5700         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5701 };
5702
5703 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
5704         {
5705                 .pa_start       = 0x4a0db000,
5706                 .pa_end         = 0x4a0db03f,
5707                 .flags          = ADDR_TYPE_RT
5708         },
5709         { }
5710 };
5711
5712 /* l4_cfg -> smartreflex_iva */
5713 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
5714         .master         = &omap44xx_l4_cfg_hwmod,
5715         .slave          = &omap44xx_smartreflex_iva_hwmod,
5716         .clk            = "l4_div_ck",
5717         .addr           = omap44xx_smartreflex_iva_addrs,
5718         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5719 };
5720
5721 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
5722         {
5723                 .pa_start       = 0x4a0d9000,
5724                 .pa_end         = 0x4a0d903f,
5725                 .flags          = ADDR_TYPE_RT
5726         },
5727         { }
5728 };
5729
5730 /* l4_cfg -> smartreflex_mpu */
5731 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
5732         .master         = &omap44xx_l4_cfg_hwmod,
5733         .slave          = &omap44xx_smartreflex_mpu_hwmod,
5734         .clk            = "l4_div_ck",
5735         .addr           = omap44xx_smartreflex_mpu_addrs,
5736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5737 };
5738
5739 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
5740         {
5741                 .pa_start       = 0x4a0f6000,
5742                 .pa_end         = 0x4a0f6fff,
5743                 .flags          = ADDR_TYPE_RT
5744         },
5745         { }
5746 };
5747
5748 /* l4_cfg -> spinlock */
5749 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
5750         .master         = &omap44xx_l4_cfg_hwmod,
5751         .slave          = &omap44xx_spinlock_hwmod,
5752         .clk            = "l4_div_ck",
5753         .addr           = omap44xx_spinlock_addrs,
5754         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5755 };
5756
5757 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
5758         {
5759                 .pa_start       = 0x4a318000,
5760                 .pa_end         = 0x4a31807f,
5761                 .flags          = ADDR_TYPE_RT
5762         },
5763         { }
5764 };
5765
5766 /* l4_wkup -> timer1 */
5767 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
5768         .master         = &omap44xx_l4_wkup_hwmod,
5769         .slave          = &omap44xx_timer1_hwmod,
5770         .clk            = "l4_wkup_clk_mux_ck",
5771         .addr           = omap44xx_timer1_addrs,
5772         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5773 };
5774
5775 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
5776         {
5777                 .pa_start       = 0x48032000,
5778                 .pa_end         = 0x4803207f,
5779                 .flags          = ADDR_TYPE_RT
5780         },
5781         { }
5782 };
5783
5784 /* l4_per -> timer2 */
5785 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
5786         .master         = &omap44xx_l4_per_hwmod,
5787         .slave          = &omap44xx_timer2_hwmod,
5788         .clk            = "l4_div_ck",
5789         .addr           = omap44xx_timer2_addrs,
5790         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5791 };
5792
5793 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
5794         {
5795                 .pa_start       = 0x48034000,
5796                 .pa_end         = 0x4803407f,
5797                 .flags          = ADDR_TYPE_RT
5798         },
5799         { }
5800 };
5801
5802 /* l4_per -> timer3 */
5803 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
5804         .master         = &omap44xx_l4_per_hwmod,
5805         .slave          = &omap44xx_timer3_hwmod,
5806         .clk            = "l4_div_ck",
5807         .addr           = omap44xx_timer3_addrs,
5808         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5809 };
5810
5811 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
5812         {
5813                 .pa_start       = 0x48036000,
5814                 .pa_end         = 0x4803607f,
5815                 .flags          = ADDR_TYPE_RT
5816         },
5817         { }
5818 };
5819
5820 /* l4_per -> timer4 */
5821 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
5822         .master         = &omap44xx_l4_per_hwmod,
5823         .slave          = &omap44xx_timer4_hwmod,
5824         .clk            = "l4_div_ck",
5825         .addr           = omap44xx_timer4_addrs,
5826         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5827 };
5828
5829 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
5830         {
5831                 .pa_start       = 0x40138000,
5832                 .pa_end         = 0x4013807f,
5833                 .flags          = ADDR_TYPE_RT
5834         },
5835         { }
5836 };
5837
5838 /* l4_abe -> timer5 */
5839 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
5840         .master         = &omap44xx_l4_abe_hwmod,
5841         .slave          = &omap44xx_timer5_hwmod,
5842         .clk            = "ocp_abe_iclk",
5843         .addr           = omap44xx_timer5_addrs,
5844         .user           = OCP_USER_MPU,
5845 };
5846
5847 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
5848         {
5849                 .pa_start       = 0x49038000,
5850                 .pa_end         = 0x4903807f,
5851                 .flags          = ADDR_TYPE_RT
5852         },
5853         { }
5854 };
5855
5856 /* l4_abe -> timer5 (dma) */
5857 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
5858         .master         = &omap44xx_l4_abe_hwmod,
5859         .slave          = &omap44xx_timer5_hwmod,
5860         .clk            = "ocp_abe_iclk",
5861         .addr           = omap44xx_timer5_dma_addrs,
5862         .user           = OCP_USER_SDMA,
5863 };
5864
5865 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
5866         {
5867                 .pa_start       = 0x4013a000,
5868                 .pa_end         = 0x4013a07f,
5869                 .flags          = ADDR_TYPE_RT
5870         },
5871         { }
5872 };
5873
5874 /* l4_abe -> timer6 */
5875 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
5876         .master         = &omap44xx_l4_abe_hwmod,
5877         .slave          = &omap44xx_timer6_hwmod,
5878         .clk            = "ocp_abe_iclk",
5879         .addr           = omap44xx_timer6_addrs,
5880         .user           = OCP_USER_MPU,
5881 };
5882
5883 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
5884         {
5885                 .pa_start       = 0x4903a000,
5886                 .pa_end         = 0x4903a07f,
5887                 .flags          = ADDR_TYPE_RT
5888         },
5889         { }
5890 };
5891
5892 /* l4_abe -> timer6 (dma) */
5893 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
5894         .master         = &omap44xx_l4_abe_hwmod,
5895         .slave          = &omap44xx_timer6_hwmod,
5896         .clk            = "ocp_abe_iclk",
5897         .addr           = omap44xx_timer6_dma_addrs,
5898         .user           = OCP_USER_SDMA,
5899 };
5900
5901 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
5902         {
5903                 .pa_start       = 0x4013c000,
5904                 .pa_end         = 0x4013c07f,
5905                 .flags          = ADDR_TYPE_RT
5906         },
5907         { }
5908 };
5909
5910 /* l4_abe -> timer7 */
5911 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
5912         .master         = &omap44xx_l4_abe_hwmod,
5913         .slave          = &omap44xx_timer7_hwmod,
5914         .clk            = "ocp_abe_iclk",
5915         .addr           = omap44xx_timer7_addrs,
5916         .user           = OCP_USER_MPU,
5917 };
5918
5919 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
5920         {
5921                 .pa_start       = 0x4903c000,
5922                 .pa_end         = 0x4903c07f,
5923                 .flags          = ADDR_TYPE_RT
5924         },
5925         { }
5926 };
5927
5928 /* l4_abe -> timer7 (dma) */
5929 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
5930         .master         = &omap44xx_l4_abe_hwmod,
5931         .slave          = &omap44xx_timer7_hwmod,
5932         .clk            = "ocp_abe_iclk",
5933         .addr           = omap44xx_timer7_dma_addrs,
5934         .user           = OCP_USER_SDMA,
5935 };
5936
5937 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
5938         {
5939                 .pa_start       = 0x4013e000,
5940                 .pa_end         = 0x4013e07f,
5941                 .flags          = ADDR_TYPE_RT
5942         },
5943         { }
5944 };
5945
5946 /* l4_abe -> timer8 */
5947 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
5948         .master         = &omap44xx_l4_abe_hwmod,
5949         .slave          = &omap44xx_timer8_hwmod,
5950         .clk            = "ocp_abe_iclk",
5951         .addr           = omap44xx_timer8_addrs,
5952         .user           = OCP_USER_MPU,
5953 };
5954
5955 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
5956         {
5957                 .pa_start       = 0x4903e000,
5958                 .pa_end         = 0x4903e07f,
5959                 .flags          = ADDR_TYPE_RT
5960         },
5961         { }
5962 };
5963
5964 /* l4_abe -> timer8 (dma) */
5965 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
5966         .master         = &omap44xx_l4_abe_hwmod,
5967         .slave          = &omap44xx_timer8_hwmod,
5968         .clk            = "ocp_abe_iclk",
5969         .addr           = omap44xx_timer8_dma_addrs,
5970         .user           = OCP_USER_SDMA,
5971 };
5972
5973 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
5974         {
5975                 .pa_start       = 0x4803e000,
5976                 .pa_end         = 0x4803e07f,
5977                 .flags          = ADDR_TYPE_RT
5978         },
5979         { }
5980 };
5981
5982 /* l4_per -> timer9 */
5983 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
5984         .master         = &omap44xx_l4_per_hwmod,
5985         .slave          = &omap44xx_timer9_hwmod,
5986         .clk            = "l4_div_ck",
5987         .addr           = omap44xx_timer9_addrs,
5988         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5989 };
5990
5991 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
5992         {
5993                 .pa_start       = 0x48086000,
5994                 .pa_end         = 0x4808607f,
5995                 .flags          = ADDR_TYPE_RT
5996         },
5997         { }
5998 };
5999
6000 /* l4_per -> timer10 */
6001 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
6002         .master         = &omap44xx_l4_per_hwmod,
6003         .slave          = &omap44xx_timer10_hwmod,
6004         .clk            = "l4_div_ck",
6005         .addr           = omap44xx_timer10_addrs,
6006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6007 };
6008
6009 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
6010         {
6011                 .pa_start       = 0x48088000,
6012                 .pa_end         = 0x4808807f,
6013                 .flags          = ADDR_TYPE_RT
6014         },
6015         { }
6016 };
6017
6018 /* l4_per -> timer11 */
6019 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
6020         .master         = &omap44xx_l4_per_hwmod,
6021         .slave          = &omap44xx_timer11_hwmod,
6022         .clk            = "l4_div_ck",
6023         .addr           = omap44xx_timer11_addrs,
6024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6025 };
6026
6027 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
6028         {
6029                 .pa_start       = 0x4806a000,
6030                 .pa_end         = 0x4806a0ff,
6031                 .flags          = ADDR_TYPE_RT
6032         },
6033         { }
6034 };
6035
6036 /* l4_per -> uart1 */
6037 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
6038         .master         = &omap44xx_l4_per_hwmod,
6039         .slave          = &omap44xx_uart1_hwmod,
6040         .clk            = "l4_div_ck",
6041         .addr           = omap44xx_uart1_addrs,
6042         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6043 };
6044
6045 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
6046         {
6047                 .pa_start       = 0x4806c000,
6048                 .pa_end         = 0x4806c0ff,
6049                 .flags          = ADDR_TYPE_RT
6050         },
6051         { }
6052 };
6053
6054 /* l4_per -> uart2 */
6055 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
6056         .master         = &omap44xx_l4_per_hwmod,
6057         .slave          = &omap44xx_uart2_hwmod,
6058         .clk            = "l4_div_ck",
6059         .addr           = omap44xx_uart2_addrs,
6060         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6061 };
6062
6063 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
6064         {
6065                 .pa_start       = 0x48020000,
6066                 .pa_end         = 0x480200ff,
6067                 .flags          = ADDR_TYPE_RT
6068         },
6069         { }
6070 };
6071
6072 /* l4_per -> uart3 */
6073 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
6074         .master         = &omap44xx_l4_per_hwmod,
6075         .slave          = &omap44xx_uart3_hwmod,
6076         .clk            = "l4_div_ck",
6077         .addr           = omap44xx_uart3_addrs,
6078         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6079 };
6080
6081 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
6082         {
6083                 .pa_start       = 0x4806e000,
6084                 .pa_end         = 0x4806e0ff,
6085                 .flags          = ADDR_TYPE_RT
6086         },
6087         { }
6088 };
6089
6090 /* l4_per -> uart4 */
6091 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
6092         .master         = &omap44xx_l4_per_hwmod,
6093         .slave          = &omap44xx_uart4_hwmod,
6094         .clk            = "l4_div_ck",
6095         .addr           = omap44xx_uart4_addrs,
6096         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6097 };
6098
6099 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs[] = {
6100         {
6101                 .pa_start       = 0x4a0a9000,
6102                 .pa_end         = 0x4a0a93ff,
6103                 .flags          = ADDR_TYPE_RT
6104         },
6105         { }
6106 };
6107
6108 /* l4_cfg -> usb_host_fs */
6109 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
6110         .master         = &omap44xx_l4_cfg_hwmod,
6111         .slave          = &omap44xx_usb_host_fs_hwmod,
6112         .clk            = "l4_div_ck",
6113         .addr           = omap44xx_usb_host_fs_addrs,
6114         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6115 };
6116
6117 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
6118         {
6119                 .name           = "uhh",
6120                 .pa_start       = 0x4a064000,
6121                 .pa_end         = 0x4a0647ff,
6122                 .flags          = ADDR_TYPE_RT
6123         },
6124         {
6125                 .name           = "ohci",
6126                 .pa_start       = 0x4a064800,
6127                 .pa_end         = 0x4a064bff,
6128         },
6129         {
6130                 .name           = "ehci",
6131                 .pa_start       = 0x4a064c00,
6132                 .pa_end         = 0x4a064fff,
6133         },
6134         {}
6135 };
6136
6137 /* l4_cfg -> usb_host_hs */
6138 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
6139         .master         = &omap44xx_l4_cfg_hwmod,
6140         .slave          = &omap44xx_usb_host_hs_hwmod,
6141         .clk            = "l4_div_ck",
6142         .addr           = omap44xx_usb_host_hs_addrs,
6143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6144 };
6145
6146 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
6147         {
6148                 .pa_start       = 0x4a0ab000,
6149                 .pa_end         = 0x4a0ab7ff,
6150                 .flags          = ADDR_TYPE_RT
6151         },
6152         {
6153                 /* XXX: Remove this once control module driver is in place */
6154                 .pa_start       = 0x4a00233c,
6155                 .pa_end         = 0x4a00233f,
6156                 .flags          = ADDR_TYPE_RT
6157         },
6158         { }
6159 };
6160
6161 /* l4_cfg -> usb_otg_hs */
6162 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
6163         .master         = &omap44xx_l4_cfg_hwmod,
6164         .slave          = &omap44xx_usb_otg_hs_hwmod,
6165         .clk            = "l4_div_ck",
6166         .addr           = omap44xx_usb_otg_hs_addrs,
6167         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6168 };
6169
6170 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
6171         {
6172                 .name           = "tll",
6173                 .pa_start       = 0x4a062000,
6174                 .pa_end         = 0x4a063fff,
6175                 .flags          = ADDR_TYPE_RT
6176         },
6177         {}
6178 };
6179
6180 /* l4_cfg -> usb_tll_hs */
6181 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
6182         .master         = &omap44xx_l4_cfg_hwmod,
6183         .slave          = &omap44xx_usb_tll_hs_hwmod,
6184         .clk            = "l4_div_ck",
6185         .addr           = omap44xx_usb_tll_hs_addrs,
6186         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6187 };
6188
6189 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
6190         {
6191                 .pa_start       = 0x4a314000,
6192                 .pa_end         = 0x4a31407f,
6193                 .flags          = ADDR_TYPE_RT
6194         },
6195         { }
6196 };
6197
6198 /* l4_wkup -> wd_timer2 */
6199 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
6200         .master         = &omap44xx_l4_wkup_hwmod,
6201         .slave          = &omap44xx_wd_timer2_hwmod,
6202         .clk            = "l4_wkup_clk_mux_ck",
6203         .addr           = omap44xx_wd_timer2_addrs,
6204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
6205 };
6206
6207 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
6208         {
6209                 .pa_start       = 0x40130000,
6210                 .pa_end         = 0x4013007f,
6211                 .flags          = ADDR_TYPE_RT
6212         },
6213         { }
6214 };
6215
6216 /* l4_abe -> wd_timer3 */
6217 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
6218         .master         = &omap44xx_l4_abe_hwmod,
6219         .slave          = &omap44xx_wd_timer3_hwmod,
6220         .clk            = "ocp_abe_iclk",
6221         .addr           = omap44xx_wd_timer3_addrs,
6222         .user           = OCP_USER_MPU,
6223 };
6224
6225 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
6226         {
6227                 .pa_start       = 0x49030000,
6228                 .pa_end         = 0x4903007f,
6229                 .flags          = ADDR_TYPE_RT
6230         },
6231         { }
6232 };
6233
6234 /* l4_abe -> wd_timer3 (dma) */
6235 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
6236         .master         = &omap44xx_l4_abe_hwmod,
6237         .slave          = &omap44xx_wd_timer3_hwmod,
6238         .clk            = "ocp_abe_iclk",
6239         .addr           = omap44xx_wd_timer3_dma_addrs,
6240         .user           = OCP_USER_SDMA,
6241 };
6242
6243 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6244         &omap44xx_c2c__c2c_target_fw,
6245         &omap44xx_l4_cfg__c2c_target_fw,
6246         &omap44xx_l3_main_1__dmm,
6247         &omap44xx_mpu__dmm,
6248         &omap44xx_c2c__emif_fw,
6249         &omap44xx_dmm__emif_fw,
6250         &omap44xx_l4_cfg__emif_fw,
6251         &omap44xx_iva__l3_instr,
6252         &omap44xx_l3_main_3__l3_instr,
6253         &omap44xx_ocp_wp_noc__l3_instr,
6254         &omap44xx_dsp__l3_main_1,
6255         &omap44xx_dss__l3_main_1,
6256         &omap44xx_l3_main_2__l3_main_1,
6257         &omap44xx_l4_cfg__l3_main_1,
6258         &omap44xx_mmc1__l3_main_1,
6259         &omap44xx_mmc2__l3_main_1,
6260         &omap44xx_mpu__l3_main_1,
6261         &omap44xx_c2c_target_fw__l3_main_2,
6262         &omap44xx_debugss__l3_main_2,
6263         &omap44xx_dma_system__l3_main_2,
6264         &omap44xx_fdif__l3_main_2,
6265         &omap44xx_gpu__l3_main_2,
6266         &omap44xx_hsi__l3_main_2,
6267         &omap44xx_ipu__l3_main_2,
6268         &omap44xx_iss__l3_main_2,
6269         &omap44xx_iva__l3_main_2,
6270         &omap44xx_l3_main_1__l3_main_2,
6271         &omap44xx_l4_cfg__l3_main_2,
6272         /* &omap44xx_usb_host_fs__l3_main_2, */
6273         &omap44xx_usb_host_hs__l3_main_2,
6274         &omap44xx_usb_otg_hs__l3_main_2,
6275         &omap44xx_l3_main_1__l3_main_3,
6276         &omap44xx_l3_main_2__l3_main_3,
6277         &omap44xx_l4_cfg__l3_main_3,
6278         /* &omap44xx_aess__l4_abe, */
6279         &omap44xx_dsp__l4_abe,
6280         &omap44xx_l3_main_1__l4_abe,
6281         &omap44xx_mpu__l4_abe,
6282         &omap44xx_l3_main_1__l4_cfg,
6283         &omap44xx_l3_main_2__l4_per,
6284         &omap44xx_l4_cfg__l4_wkup,
6285         &omap44xx_mpu__mpu_private,
6286         &omap44xx_l4_cfg__ocp_wp_noc,
6287         /* &omap44xx_l4_abe__aess, */
6288         /* &omap44xx_l4_abe__aess_dma, */
6289         &omap44xx_l3_main_2__c2c,
6290         &omap44xx_l4_wkup__counter_32k,
6291         &omap44xx_l4_cfg__ctrl_module_core,
6292         &omap44xx_l4_cfg__ctrl_module_pad_core,
6293         &omap44xx_l4_wkup__ctrl_module_wkup,
6294         &omap44xx_l4_wkup__ctrl_module_pad_wkup,
6295         &omap44xx_l3_instr__debugss,
6296         &omap44xx_l4_cfg__dma_system,
6297         &omap44xx_l4_abe__dmic,
6298         &omap44xx_l4_abe__dmic_dma,
6299         &omap44xx_dsp__iva,
6300         /* &omap44xx_dsp__sl2if, */
6301         &omap44xx_l4_cfg__dsp,
6302         &omap44xx_l3_main_2__dss,
6303         &omap44xx_l4_per__dss,
6304         &omap44xx_l3_main_2__dss_dispc,
6305         &omap44xx_l4_per__dss_dispc,
6306         &omap44xx_l3_main_2__dss_dsi1,
6307         &omap44xx_l4_per__dss_dsi1,
6308         &omap44xx_l3_main_2__dss_dsi2,
6309         &omap44xx_l4_per__dss_dsi2,
6310         &omap44xx_l3_main_2__dss_hdmi,
6311         &omap44xx_l4_per__dss_hdmi,
6312