Merge tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[linux-3.10.git] / arch / arm / mach-omap2 / omap_hwmod_2xxx_ipblock_data.c
1 /*
2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
3  *
4  * Copyright (C) 2011 Nokia Corporation
5  * Paul Walmsley
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11
12 #include <linux/platform_data/gpio-omap.h>
13 #include <linux/omap-dma.h>
14 #include <plat/dmtimer.h>
15 #include <linux/platform_data/spi-omap2-mcspi.h>
16
17 #include "omap_hwmod.h"
18 #include "omap_hwmod_common_data.h"
19 #include "cm-regbits-24xx.h"
20 #include "prm-regbits-24xx.h"
21 #include "wd_timer.h"
22
23 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
24         { .irq = 48 + OMAP_INTC_START, },
25         { .irq = -1 },
26 };
27
28 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
29         { .name = "dispc", .dma_req = 5 },
30         { .dma_req = -1 }
31 };
32
33 /*
34  * 'dispc' class
35  * display controller
36  */
37
38 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
39         .rev_offs       = 0x0000,
40         .sysc_offs      = 0x0010,
41         .syss_offs      = 0x0014,
42         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
43                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
44         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
45                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
46         .sysc_fields    = &omap_hwmod_sysc_type1,
47 };
48
49 struct omap_hwmod_class omap2_dispc_hwmod_class = {
50         .name   = "dispc",
51         .sysc   = &omap2_dispc_sysc,
52 };
53
54 /* OMAP2xxx Timer Common */
55 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
56         .rev_offs       = 0x0000,
57         .sysc_offs      = 0x0010,
58         .syss_offs      = 0x0014,
59         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
60                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
61                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
62         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
63         .clockact       = CLOCKACT_TEST_ICLK,
64         .sysc_fields    = &omap_hwmod_sysc_type1,
65 };
66
67 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
68         .name   = "timer",
69         .sysc   = &omap2xxx_timer_sysc,
70 };
71
72 /*
73  * 'wd_timer' class
74  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
75  * overflow condition
76  */
77
78 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
79         .rev_offs       = 0x0000,
80         .sysc_offs      = 0x0010,
81         .syss_offs      = 0x0014,
82         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
83                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
84         .sysc_fields    = &omap_hwmod_sysc_type1,
85 };
86
87 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
88         .name           = "wd_timer",
89         .sysc           = &omap2xxx_wd_timer_sysc,
90         .pre_shutdown   = &omap2_wd_timer_disable,
91         .reset          = &omap2_wd_timer_reset,
92 };
93
94 /*
95  * 'gpio' class
96  * general purpose io module
97  */
98 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
99         .rev_offs       = 0x0000,
100         .sysc_offs      = 0x0010,
101         .syss_offs      = 0x0014,
102         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
103                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
104                            SYSS_HAS_RESET_STATUS),
105         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
106         .sysc_fields    = &omap_hwmod_sysc_type1,
107 };
108
109 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
110         .name = "gpio",
111         .sysc = &omap2xxx_gpio_sysc,
112         .rev = 0,
113 };
114
115 /* system dma */
116 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
117         .rev_offs       = 0x0000,
118         .sysc_offs      = 0x002c,
119         .syss_offs      = 0x0028,
120         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
121                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
122                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
123         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
124         .sysc_fields    = &omap_hwmod_sysc_type1,
125 };
126
127 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
128         .name   = "dma",
129         .sysc   = &omap2xxx_dma_sysc,
130 };
131
132 /*
133  * 'mailbox' class
134  * mailbox module allowing communication between the on-chip processors
135  * using a queued mailbox-interrupt mechanism.
136  */
137
138 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
139         .rev_offs       = 0x000,
140         .sysc_offs      = 0x010,
141         .syss_offs      = 0x014,
142         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
143                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
144         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
145         .sysc_fields    = &omap_hwmod_sysc_type1,
146 };
147
148 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
149         .name   = "mailbox",
150         .sysc   = &omap2xxx_mailbox_sysc,
151 };
152
153 /*
154  * 'mcspi' class
155  * multichannel serial port interface (mcspi) / master/slave synchronous serial
156  * bus
157  */
158
159 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
160         .rev_offs       = 0x0000,
161         .sysc_offs      = 0x0010,
162         .syss_offs      = 0x0014,
163         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
164                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
165                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
166         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
167         .sysc_fields    = &omap_hwmod_sysc_type1,
168 };
169
170 struct omap_hwmod_class omap2xxx_mcspi_class = {
171         .name   = "mcspi",
172         .sysc   = &omap2xxx_mcspi_sysc,
173         .rev    = OMAP2_MCSPI_REV,
174 };
175
176 /*
177  * 'gpmc' class
178  * general purpose memory controller
179  */
180
181 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
182         .rev_offs       = 0x0000,
183         .sysc_offs      = 0x0010,
184         .syss_offs      = 0x0014,
185         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
186                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
187         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
188         .sysc_fields    = &omap_hwmod_sysc_type1,
189 };
190
191 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
192         .name   = "gpmc",
193         .sysc   = &omap2xxx_gpmc_sysc,
194 };
195
196 /*
197  * IP blocks
198  */
199
200 /* L3 */
201 struct omap_hwmod omap2xxx_l3_main_hwmod = {
202         .name           = "l3_main",
203         .class          = &l3_hwmod_class,
204         .flags          = HWMOD_NO_IDLEST,
205 };
206
207 /* L4 CORE */
208 struct omap_hwmod omap2xxx_l4_core_hwmod = {
209         .name           = "l4_core",
210         .class          = &l4_hwmod_class,
211         .flags          = HWMOD_NO_IDLEST,
212 };
213
214 /* L4 WKUP */
215 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
216         .name           = "l4_wkup",
217         .class          = &l4_hwmod_class,
218         .flags          = HWMOD_NO_IDLEST,
219 };
220
221 /* MPU */
222 static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
223         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
224         { .irq = -1 }
225 };
226
227 struct omap_hwmod omap2xxx_mpu_hwmod = {
228         .name           = "mpu",
229         .mpu_irqs       = omap2xxx_mpu_irqs,
230         .class          = &mpu_hwmod_class,
231         .main_clk       = "mpu_ck",
232 };
233
234 /* IVA2 */
235 struct omap_hwmod omap2xxx_iva_hwmod = {
236         .name           = "iva",
237         .class          = &iva_hwmod_class,
238 };
239
240 /* always-on timers dev attribute */
241 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
242         .timer_capability       = OMAP_TIMER_ALWON,
243 };
244
245 /* pwm timers dev attribute */
246 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
247         .timer_capability       = OMAP_TIMER_HAS_PWM,
248 };
249
250 /* timers with DSP interrupt dev attribute */
251 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
252         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
253 };
254
255 /* timer1 */
256
257 struct omap_hwmod omap2xxx_timer1_hwmod = {
258         .name           = "timer1",
259         .mpu_irqs       = omap2_timer1_mpu_irqs,
260         .main_clk       = "gpt1_fck",
261         .prcm           = {
262                 .omap2 = {
263                         .prcm_reg_id = 1,
264                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
265                         .module_offs = WKUP_MOD,
266                         .idlest_reg_id = 1,
267                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
268                 },
269         },
270         .dev_attr       = &capability_alwon_dev_attr,
271         .class          = &omap2xxx_timer_hwmod_class,
272         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
273 };
274
275 /* timer2 */
276
277 struct omap_hwmod omap2xxx_timer2_hwmod = {
278         .name           = "timer2",
279         .mpu_irqs       = omap2_timer2_mpu_irqs,
280         .main_clk       = "gpt2_fck",
281         .prcm           = {
282                 .omap2 = {
283                         .prcm_reg_id = 1,
284                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
285                         .module_offs = CORE_MOD,
286                         .idlest_reg_id = 1,
287                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
288                 },
289         },
290         .class          = &omap2xxx_timer_hwmod_class,
291         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
292 };
293
294 /* timer3 */
295
296 struct omap_hwmod omap2xxx_timer3_hwmod = {
297         .name           = "timer3",
298         .mpu_irqs       = omap2_timer3_mpu_irqs,
299         .main_clk       = "gpt3_fck",
300         .prcm           = {
301                 .omap2 = {
302                         .prcm_reg_id = 1,
303                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
304                         .module_offs = CORE_MOD,
305                         .idlest_reg_id = 1,
306                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
307                 },
308         },
309         .class          = &omap2xxx_timer_hwmod_class,
310         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
311 };
312
313 /* timer4 */
314
315 struct omap_hwmod omap2xxx_timer4_hwmod = {
316         .name           = "timer4",
317         .mpu_irqs       = omap2_timer4_mpu_irqs,
318         .main_clk       = "gpt4_fck",
319         .prcm           = {
320                 .omap2 = {
321                         .prcm_reg_id = 1,
322                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
323                         .module_offs = CORE_MOD,
324                         .idlest_reg_id = 1,
325                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
326                 },
327         },
328         .class          = &omap2xxx_timer_hwmod_class,
329         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
330 };
331
332 /* timer5 */
333
334 struct omap_hwmod omap2xxx_timer5_hwmod = {
335         .name           = "timer5",
336         .mpu_irqs       = omap2_timer5_mpu_irqs,
337         .main_clk       = "gpt5_fck",
338         .prcm           = {
339                 .omap2 = {
340                         .prcm_reg_id = 1,
341                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
342                         .module_offs = CORE_MOD,
343                         .idlest_reg_id = 1,
344                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
345                 },
346         },
347         .dev_attr       = &capability_dsp_dev_attr,
348         .class          = &omap2xxx_timer_hwmod_class,
349         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
350 };
351
352 /* timer6 */
353
354 struct omap_hwmod omap2xxx_timer6_hwmod = {
355         .name           = "timer6",
356         .mpu_irqs       = omap2_timer6_mpu_irqs,
357         .main_clk       = "gpt6_fck",
358         .prcm           = {
359                 .omap2 = {
360                         .prcm_reg_id = 1,
361                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
362                         .module_offs = CORE_MOD,
363                         .idlest_reg_id = 1,
364                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
365                 },
366         },
367         .dev_attr       = &capability_dsp_dev_attr,
368         .class          = &omap2xxx_timer_hwmod_class,
369         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
370 };
371
372 /* timer7 */
373
374 struct omap_hwmod omap2xxx_timer7_hwmod = {
375         .name           = "timer7",
376         .mpu_irqs       = omap2_timer7_mpu_irqs,
377         .main_clk       = "gpt7_fck",
378         .prcm           = {
379                 .omap2 = {
380                         .prcm_reg_id = 1,
381                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
382                         .module_offs = CORE_MOD,
383                         .idlest_reg_id = 1,
384                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
385                 },
386         },
387         .dev_attr       = &capability_dsp_dev_attr,
388         .class          = &omap2xxx_timer_hwmod_class,
389         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
390 };
391
392 /* timer8 */
393
394 struct omap_hwmod omap2xxx_timer8_hwmod = {
395         .name           = "timer8",
396         .mpu_irqs       = omap2_timer8_mpu_irqs,
397         .main_clk       = "gpt8_fck",
398         .prcm           = {
399                 .omap2 = {
400                         .prcm_reg_id = 1,
401                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
402                         .module_offs = CORE_MOD,
403                         .idlest_reg_id = 1,
404                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
405                 },
406         },
407         .dev_attr       = &capability_dsp_dev_attr,
408         .class          = &omap2xxx_timer_hwmod_class,
409         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
410 };
411
412 /* timer9 */
413
414 struct omap_hwmod omap2xxx_timer9_hwmod = {
415         .name           = "timer9",
416         .mpu_irqs       = omap2_timer9_mpu_irqs,
417         .main_clk       = "gpt9_fck",
418         .prcm           = {
419                 .omap2 = {
420                         .prcm_reg_id = 1,
421                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
422                         .module_offs = CORE_MOD,
423                         .idlest_reg_id = 1,
424                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
425                 },
426         },
427         .dev_attr       = &capability_pwm_dev_attr,
428         .class          = &omap2xxx_timer_hwmod_class,
429         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
430 };
431
432 /* timer10 */
433
434 struct omap_hwmod omap2xxx_timer10_hwmod = {
435         .name           = "timer10",
436         .mpu_irqs       = omap2_timer10_mpu_irqs,
437         .main_clk       = "gpt10_fck",
438         .prcm           = {
439                 .omap2 = {
440                         .prcm_reg_id = 1,
441                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
442                         .module_offs = CORE_MOD,
443                         .idlest_reg_id = 1,
444                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
445                 },
446         },
447         .dev_attr       = &capability_pwm_dev_attr,
448         .class          = &omap2xxx_timer_hwmod_class,
449         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
450 };
451
452 /* timer11 */
453
454 struct omap_hwmod omap2xxx_timer11_hwmod = {
455         .name           = "timer11",
456         .mpu_irqs       = omap2_timer11_mpu_irqs,
457         .main_clk       = "gpt11_fck",
458         .prcm           = {
459                 .omap2 = {
460                         .prcm_reg_id = 1,
461                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
462                         .module_offs = CORE_MOD,
463                         .idlest_reg_id = 1,
464                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
465                 },
466         },
467         .dev_attr       = &capability_pwm_dev_attr,
468         .class          = &omap2xxx_timer_hwmod_class,
469         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
470 };
471
472 /* timer12 */
473
474 struct omap_hwmod omap2xxx_timer12_hwmod = {
475         .name           = "timer12",
476         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
477         .main_clk       = "gpt12_fck",
478         .prcm           = {
479                 .omap2 = {
480                         .prcm_reg_id = 1,
481                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
482                         .module_offs = CORE_MOD,
483                         .idlest_reg_id = 1,
484                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
485                 },
486         },
487         .dev_attr       = &capability_pwm_dev_attr,
488         .class          = &omap2xxx_timer_hwmod_class,
489         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
490 };
491
492 /* wd_timer2 */
493 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
494         .name           = "wd_timer2",
495         .class          = &omap2xxx_wd_timer_hwmod_class,
496         .main_clk       = "mpu_wdt_fck",
497         .prcm           = {
498                 .omap2 = {
499                         .prcm_reg_id = 1,
500                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
501                         .module_offs = WKUP_MOD,
502                         .idlest_reg_id = 1,
503                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
504                 },
505         },
506 };
507
508 /* UART1 */
509
510 struct omap_hwmod omap2xxx_uart1_hwmod = {
511         .name           = "uart1",
512         .mpu_irqs       = omap2_uart1_mpu_irqs,
513         .sdma_reqs      = omap2_uart1_sdma_reqs,
514         .main_clk       = "uart1_fck",
515         .prcm           = {
516                 .omap2 = {
517                         .module_offs = CORE_MOD,
518                         .prcm_reg_id = 1,
519                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
520                         .idlest_reg_id = 1,
521                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
522                 },
523         },
524         .class          = &omap2_uart_class,
525 };
526
527 /* UART2 */
528
529 struct omap_hwmod omap2xxx_uart2_hwmod = {
530         .name           = "uart2",
531         .mpu_irqs       = omap2_uart2_mpu_irqs,
532         .sdma_reqs      = omap2_uart2_sdma_reqs,
533         .main_clk       = "uart2_fck",
534         .prcm           = {
535                 .omap2 = {
536                         .module_offs = CORE_MOD,
537                         .prcm_reg_id = 1,
538                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
539                         .idlest_reg_id = 1,
540                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
541                 },
542         },
543         .class          = &omap2_uart_class,
544 };
545
546 /* UART3 */
547
548 struct omap_hwmod omap2xxx_uart3_hwmod = {
549         .name           = "uart3",
550         .mpu_irqs       = omap2_uart3_mpu_irqs,
551         .sdma_reqs      = omap2_uart3_sdma_reqs,
552         .main_clk       = "uart3_fck",
553         .prcm           = {
554                 .omap2 = {
555                         .module_offs = CORE_MOD,
556                         .prcm_reg_id = 2,
557                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
558                         .idlest_reg_id = 2,
559                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
560                 },
561         },
562         .class          = &omap2_uart_class,
563 };
564
565 /* dss */
566
567 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
568         /*
569          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
570          * driver does not use these clocks.
571          */
572         { .role = "tv_clk", .clk = "dss_54m_fck" },
573         { .role = "sys_clk", .clk = "dss2_fck" },
574 };
575
576 struct omap_hwmod omap2xxx_dss_core_hwmod = {
577         .name           = "dss_core",
578         .class          = &omap2_dss_hwmod_class,
579         .main_clk       = "dss1_fck", /* instead of dss_fck */
580         .sdma_reqs      = omap2xxx_dss_sdma_chs,
581         .prcm           = {
582                 .omap2 = {
583                         .prcm_reg_id = 1,
584                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
585                         .module_offs = CORE_MOD,
586                         .idlest_reg_id = 1,
587                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
588                 },
589         },
590         .opt_clks       = dss_opt_clks,
591         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
592         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
593 };
594
595 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
596         .name           = "dss_dispc",
597         .class          = &omap2_dispc_hwmod_class,
598         .mpu_irqs       = omap2_dispc_irqs,
599         .main_clk       = "dss1_fck",
600         .prcm           = {
601                 .omap2 = {
602                         .prcm_reg_id = 1,
603                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
604                         .module_offs = CORE_MOD,
605                         .idlest_reg_id = 1,
606                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
607                 },
608         },
609         .flags          = HWMOD_NO_IDLEST,
610         .dev_attr       = &omap2_3_dss_dispc_dev_attr
611 };
612
613 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
614         { .role = "ick", .clk = "dss_ick" },
615 };
616
617 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
618         .name           = "dss_rfbi",
619         .class          = &omap2_rfbi_hwmod_class,
620         .main_clk       = "dss1_fck",
621         .prcm           = {
622                 .omap2 = {
623                         .prcm_reg_id = 1,
624                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
625                         .module_offs = CORE_MOD,
626                 },
627         },
628         .opt_clks       = dss_rfbi_opt_clks,
629         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
630         .flags          = HWMOD_NO_IDLEST,
631 };
632
633 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
634         .name           = "dss_venc",
635         .class          = &omap2_venc_hwmod_class,
636         .main_clk       = "dss_54m_fck",
637         .prcm           = {
638                 .omap2 = {
639                         .prcm_reg_id = 1,
640                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
641                         .module_offs = CORE_MOD,
642                 },
643         },
644         .flags          = HWMOD_NO_IDLEST,
645 };
646
647 /* gpio dev_attr */
648 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
649         .bank_width = 32,
650         .dbck_flag = false,
651 };
652
653 /* gpio1 */
654 struct omap_hwmod omap2xxx_gpio1_hwmod = {
655         .name           = "gpio1",
656         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
657         .mpu_irqs       = omap2_gpio1_irqs,
658         .main_clk       = "gpios_fck",
659         .prcm           = {
660                 .omap2 = {
661                         .prcm_reg_id = 1,
662                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
663                         .module_offs = WKUP_MOD,
664                         .idlest_reg_id = 1,
665                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
666                 },
667         },
668         .class          = &omap2xxx_gpio_hwmod_class,
669         .dev_attr       = &omap2xxx_gpio_dev_attr,
670 };
671
672 /* gpio2 */
673 struct omap_hwmod omap2xxx_gpio2_hwmod = {
674         .name           = "gpio2",
675         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
676         .mpu_irqs       = omap2_gpio2_irqs,
677         .main_clk       = "gpios_fck",
678         .prcm           = {
679                 .omap2 = {
680                         .prcm_reg_id = 1,
681                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
682                         .module_offs = WKUP_MOD,
683                         .idlest_reg_id = 1,
684                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
685                 },
686         },
687         .class          = &omap2xxx_gpio_hwmod_class,
688         .dev_attr       = &omap2xxx_gpio_dev_attr,
689 };
690
691 /* gpio3 */
692 struct omap_hwmod omap2xxx_gpio3_hwmod = {
693         .name           = "gpio3",
694         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
695         .mpu_irqs       = omap2_gpio3_irqs,
696         .main_clk       = "gpios_fck",
697         .prcm           = {
698                 .omap2 = {
699                         .prcm_reg_id = 1,
700                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
701                         .module_offs = WKUP_MOD,
702                         .idlest_reg_id = 1,
703                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
704                 },
705         },
706         .class          = &omap2xxx_gpio_hwmod_class,
707         .dev_attr       = &omap2xxx_gpio_dev_attr,
708 };
709
710 /* gpio4 */
711 struct omap_hwmod omap2xxx_gpio4_hwmod = {
712         .name           = "gpio4",
713         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
714         .mpu_irqs       = omap2_gpio4_irqs,
715         .main_clk       = "gpios_fck",
716         .prcm           = {
717                 .omap2 = {
718                         .prcm_reg_id = 1,
719                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
720                         .module_offs = WKUP_MOD,
721                         .idlest_reg_id = 1,
722                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
723                 },
724         },
725         .class          = &omap2xxx_gpio_hwmod_class,
726         .dev_attr       = &omap2xxx_gpio_dev_attr,
727 };
728
729 /* mcspi1 */
730 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
731         .num_chipselect = 4,
732 };
733
734 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
735         .name           = "mcspi1",
736         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
737         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
738         .main_clk       = "mcspi1_fck",
739         .prcm           = {
740                 .omap2 = {
741                         .module_offs = CORE_MOD,
742                         .prcm_reg_id = 1,
743                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
744                         .idlest_reg_id = 1,
745                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
746                 },
747         },
748         .class          = &omap2xxx_mcspi_class,
749         .dev_attr       = &omap_mcspi1_dev_attr,
750 };
751
752 /* mcspi2 */
753 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
754         .num_chipselect = 2,
755 };
756
757 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
758         .name           = "mcspi2",
759         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
760         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
761         .main_clk       = "mcspi2_fck",
762         .prcm           = {
763                 .omap2 = {
764                         .module_offs = CORE_MOD,
765                         .prcm_reg_id = 1,
766                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
767                         .idlest_reg_id = 1,
768                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
769                 },
770         },
771         .class          = &omap2xxx_mcspi_class,
772         .dev_attr       = &omap_mcspi2_dev_attr,
773 };
774
775 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
776         .name   = "counter",
777 };
778
779 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
780         .name           = "counter_32k",
781         .main_clk       = "func_32k_ck",
782         .prcm           = {
783                 .omap2  = {
784                         .module_offs = WKUP_MOD,
785                         .prcm_reg_id = 1,
786                         .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
787                         .idlest_reg_id = 1,
788                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
789                 },
790         },
791         .class          = &omap2xxx_counter_hwmod_class,
792 };
793
794 /* gpmc */
795 static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
796         { .irq = 20 },
797         { .irq = -1 }
798 };
799
800 struct omap_hwmod omap2xxx_gpmc_hwmod = {
801         .name           = "gpmc",
802         .class          = &omap2xxx_gpmc_hwmod_class,
803         .mpu_irqs       = omap2xxx_gpmc_irqs,
804         .main_clk       = "gpmc_fck",
805         /*
806          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
807          * block.  It is not being added due to any known bugs with
808          * resetting the GPMC IP block, but rather because any timings
809          * set by the bootloader are not being correctly programmed by
810          * the kernel from the board file or DT data.
811          * HWMOD_INIT_NO_RESET should be removed ASAP.
812          */
813         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
814                            HWMOD_NO_IDLEST),
815         .prcm           = {
816                 .omap2  = {
817                         .prcm_reg_id = 3,
818                         .module_bit = OMAP24XX_EN_GPMC_MASK,
819                         .module_offs = CORE_MOD,
820                 },
821         },
822 };
823
824 /* RNG */
825
826 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
827         .rev_offs       = 0x3c,
828         .sysc_offs      = 0x40,
829         .syss_offs      = 0x44,
830         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
831                            SYSS_HAS_RESET_STATUS),
832         .sysc_fields    = &omap_hwmod_sysc_type1,
833 };
834
835 static struct omap_hwmod_class omap2_rng_hwmod_class = {
836         .name           = "rng",
837         .sysc           = &omap2_rng_sysc,
838 };
839
840 static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
841         { .irq = 52 },
842         { .irq = -1 }
843 };
844
845 struct omap_hwmod omap2xxx_rng_hwmod = {
846         .name           = "rng",
847         .mpu_irqs       = omap2_rng_mpu_irqs,
848         .main_clk       = "l4_ck",
849         .prcm           = {
850                 .omap2 = {
851                         .module_offs = CORE_MOD,
852                         .prcm_reg_id = 4,
853                         .module_bit = OMAP24XX_EN_RNG_SHIFT,
854                         .idlest_reg_id = 4,
855                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
856                 },
857         },
858         /*
859          * XXX The first read from the SYSSTATUS register of the RNG
860          * after the SYSCONFIG SOFTRESET bit is set triggers an
861          * imprecise external abort.  It's unclear why this happens.
862          * Until this is analyzed, skip the IP block reset.
863          */
864         .flags          = HWMOD_INIT_NO_RESET,
865         .class          = &omap2_rng_hwmod_class,
866 };
867
868 /* SHAM */
869
870 static struct omap_hwmod_class_sysconfig omap2_sham_sysc = {
871         .rev_offs       = 0x5c,
872         .sysc_offs      = 0x60,
873         .syss_offs      = 0x64,
874         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
875                            SYSS_HAS_RESET_STATUS),
876         .sysc_fields    = &omap_hwmod_sysc_type1,
877 };
878
879 static struct omap_hwmod_class omap2xxx_sham_class = {
880         .name   = "sham",
881         .sysc   = &omap2_sham_sysc,
882 };
883
884 static struct omap_hwmod_irq_info omap2_sham_mpu_irqs[] = {
885         { .irq = 51 + OMAP_INTC_START, },
886         { .irq = -1 }
887 };
888
889 static struct omap_hwmod_dma_info omap2_sham_sdma_chs[] = {
890         { .name = "rx", .dma_req = 13 },
891         { .dma_req = -1 }
892 };
893
894 struct omap_hwmod omap2xxx_sham_hwmod = {
895         .name           = "sham",
896         .mpu_irqs       = omap2_sham_mpu_irqs,
897         .sdma_reqs      = omap2_sham_sdma_chs,
898         .main_clk       = "l4_ck",
899         .prcm           = {
900                 .omap2 = {
901                         .module_offs = CORE_MOD,
902                         .prcm_reg_id = 4,
903                         .module_bit = OMAP24XX_EN_SHA_SHIFT,
904                         .idlest_reg_id = 4,
905                         .idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
906                 },
907         },
908         .class          = &omap2xxx_sham_class,
909 };
910
911 /* AES */
912
913 static struct omap_hwmod_class_sysconfig omap2_aes_sysc = {
914         .rev_offs       = 0x44,
915         .sysc_offs      = 0x48,
916         .syss_offs      = 0x4c,
917         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
918                            SYSS_HAS_RESET_STATUS),
919         .sysc_fields    = &omap_hwmod_sysc_type1,
920 };
921
922 static struct omap_hwmod_class omap2xxx_aes_class = {
923         .name   = "aes",
924         .sysc   = &omap2_aes_sysc,
925 };
926
927 static struct omap_hwmod_dma_info omap2_aes_sdma_chs[] = {
928         { .name = "tx", .dma_req = 9 },
929         { .name = "rx", .dma_req = 10 },
930         { .dma_req = -1 }
931 };
932
933 struct omap_hwmod omap2xxx_aes_hwmod = {
934         .name           = "aes",
935         .sdma_reqs      = omap2_aes_sdma_chs,
936         .main_clk       = "l4_ck",
937         .prcm           = {
938                 .omap2 = {
939                         .module_offs = CORE_MOD,
940                         .prcm_reg_id = 4,
941                         .module_bit = OMAP24XX_EN_AES_SHIFT,
942                         .idlest_reg_id = 4,
943                         .idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
944                 },
945         },
946         .class          = &omap2xxx_aes_class,
947 };