omap: Use separate init_irq functions to avoid cpu_is_omap tests early
[linux-3.10.git] / arch / arm / mach-omap2 / irq.c
1 /*
2  * linux/arch/arm/mach-omap2/irq.c
3  *
4  * Interrupt handler for OMAP2 boards.
5  *
6  * Copyright (C) 2005 Nokia Corporation
7  * Author: Paul Mundt <paul.mundt@nokia.com>
8  *
9  * This file is subject to the terms and conditions of the GNU General Public
10  * License. See the file "COPYING" in the main directory of this archive
11  * for more details.
12  */
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <mach/hardware.h>
18 #include <asm/mach/irq.h>
19
20
21 /* selected INTC register offsets */
22
23 #define INTC_REVISION           0x0000
24 #define INTC_SYSCONFIG          0x0010
25 #define INTC_SYSSTATUS          0x0014
26 #define INTC_SIR                0x0040
27 #define INTC_CONTROL            0x0048
28 #define INTC_PROTECTION         0x004C
29 #define INTC_IDLE               0x0050
30 #define INTC_THRESHOLD          0x0068
31 #define INTC_MIR0               0x0084
32 #define INTC_MIR_CLEAR0         0x0088
33 #define INTC_MIR_SET0           0x008c
34 #define INTC_PENDING_IRQ0       0x0098
35 /* Number of IRQ state bits in each MIR register */
36 #define IRQ_BITS_PER_REG        32
37
38 /*
39  * OMAP2 has a number of different interrupt controllers, each interrupt
40  * controller is identified as its own "bank". Register definitions are
41  * fairly consistent for each bank, but not all registers are implemented
42  * for each bank.. when in doubt, consult the TRM.
43  */
44 static struct omap_irq_bank {
45         void __iomem *base_reg;
46         unsigned int nr_irqs;
47 } __attribute__ ((aligned(4))) irq_banks[] = {
48         {
49                 /* MPU INTC */
50                 .nr_irqs        = 96,
51         },
52 };
53
54 /* Structure to save interrupt controller context */
55 struct omap3_intc_regs {
56         u32 sysconfig;
57         u32 protection;
58         u32 idle;
59         u32 threshold;
60         u32 ilr[INTCPS_NR_IRQS];
61         u32 mir[INTCPS_NR_MIR_REGS];
62 };
63
64 /* INTC bank register get/set */
65
66 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
67 {
68         __raw_writel(val, bank->base_reg + reg);
69 }
70
71 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
72 {
73         return __raw_readl(bank->base_reg + reg);
74 }
75
76 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
77 static void omap_ack_irq(struct irq_data *d)
78 {
79         intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
80 }
81
82 static void omap_mask_ack_irq(struct irq_data *d)
83 {
84         irq_gc_mask_disable_reg(d);
85         omap_ack_irq(d);
86 }
87
88 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
89 {
90         unsigned long tmp;
91
92         tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
93         printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
94                          "(revision %ld.%ld) with %d interrupts\n",
95                          bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
96
97         tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
98         tmp |= 1 << 1;  /* soft reset */
99         intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
100
101         while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
102                 /* Wait for reset to complete */;
103
104         /* Enable autoidle */
105         intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
106 }
107
108 int omap_irq_pending(void)
109 {
110         int i;
111
112         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
113                 struct omap_irq_bank *bank = irq_banks + i;
114                 int irq;
115
116                 for (irq = 0; irq < bank->nr_irqs; irq += 32)
117                         if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
118                                                ((irq >> 5) << 5)))
119                                 return 1;
120         }
121         return 0;
122 }
123
124 static __init void
125 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
126 {
127         struct irq_chip_generic *gc;
128         struct irq_chip_type *ct;
129
130         gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
131                                         handle_level_irq);
132         ct = gc->chip_types;
133         ct->chip.irq_ack = omap_mask_ack_irq;
134         ct->chip.irq_mask = irq_gc_mask_disable_reg;
135         ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
136
137         ct->regs.ack = INTC_CONTROL;
138         ct->regs.enable = INTC_MIR_CLEAR0;
139         ct->regs.disable = INTC_MIR_SET0;
140         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
141                                 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
142 }
143
144 static void __init omap_init_irq(u32 base, int nr_irqs)
145 {
146         unsigned long nr_of_irqs = 0;
147         unsigned int nr_banks = 0;
148         int i, j;
149
150         omap_irq_base = ioremap(base, SZ_4K);
151         if (WARN_ON(!omap_irq_base))
152                 return;
153
154         for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
155                 struct omap_irq_bank *bank = irq_banks + i;
156
157                 bank->nr_irqs = nr_irqs;
158
159                 /* Static mapping, never released */
160                 bank->base_reg = ioremap(base, SZ_4K);
161                 if (!bank->base_reg) {
162                         printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
163                         continue;
164                 }
165
166                 omap_irq_bank_init_one(bank);
167
168                 for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
169                         omap_alloc_gc(bank->base_reg + j, i, 32);
170
171                 nr_of_irqs += bank->nr_irqs;
172                 nr_banks++;
173         }
174
175         printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
176                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
177 }
178
179 void __init omap2_init_irq(void)
180 {
181         omap_init_irq(OMAP24XX_IC_BASE, 96);
182 }
183
184 void __init omap3_init_irq(void)
185 {
186         omap_init_irq(OMAP34XX_IC_BASE, 96);
187 }
188
189 void __init ti816x_init_irq(void)
190 {
191         omap_init_irq(OMAP34XX_IC_BASE, 128);
192 }
193
194 #ifdef CONFIG_ARCH_OMAP3
195 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
196
197 void omap_intc_save_context(void)
198 {
199         int ind = 0, i = 0;
200         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
201                 struct omap_irq_bank *bank = irq_banks + ind;
202                 intc_context[ind].sysconfig =
203                         intc_bank_read_reg(bank, INTC_SYSCONFIG);
204                 intc_context[ind].protection =
205                         intc_bank_read_reg(bank, INTC_PROTECTION);
206                 intc_context[ind].idle =
207                         intc_bank_read_reg(bank, INTC_IDLE);
208                 intc_context[ind].threshold =
209                         intc_bank_read_reg(bank, INTC_THRESHOLD);
210                 for (i = 0; i < INTCPS_NR_IRQS; i++)
211                         intc_context[ind].ilr[i] =
212                                 intc_bank_read_reg(bank, (0x100 + 0x4*i));
213                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
214                         intc_context[ind].mir[i] =
215                                 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
216                                 (0x20 * i));
217         }
218 }
219
220 void omap_intc_restore_context(void)
221 {
222         int ind = 0, i = 0;
223
224         for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
225                 struct omap_irq_bank *bank = irq_banks + ind;
226                 intc_bank_write_reg(intc_context[ind].sysconfig,
227                                         bank, INTC_SYSCONFIG);
228                 intc_bank_write_reg(intc_context[ind].sysconfig,
229                                         bank, INTC_SYSCONFIG);
230                 intc_bank_write_reg(intc_context[ind].protection,
231                                         bank, INTC_PROTECTION);
232                 intc_bank_write_reg(intc_context[ind].idle,
233                                         bank, INTC_IDLE);
234                 intc_bank_write_reg(intc_context[ind].threshold,
235                                         bank, INTC_THRESHOLD);
236                 for (i = 0; i < INTCPS_NR_IRQS; i++)
237                         intc_bank_write_reg(intc_context[ind].ilr[i],
238                                 bank, (0x100 + 0x4*i));
239                 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
240                         intc_bank_write_reg(intc_context[ind].mir[i],
241                                  &irq_banks[0], INTC_MIR0 + (0x20 * i));
242         }
243         /* MIRs are saved and restore with other PRCM registers */
244 }
245
246 void omap3_intc_suspend(void)
247 {
248         /* A pending interrupt would prevent OMAP from entering suspend */
249         omap_ack_irq(0);
250 }
251
252 void omap3_intc_prepare_idle(void)
253 {
254         /*
255          * Disable autoidle as it can stall interrupt controller,
256          * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
257          */
258         intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
259 }
260
261 void omap3_intc_resume_idle(void)
262 {
263         /* Re-enable autoidle */
264         intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
265 }
266 #endif /* CONFIG_ARCH_OMAP3 */