Merge tag 'dt-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[linux-3.10.git] / arch / arm / mach-omap2 / cm1_44xx.h
1 /*
2  * OMAP44xx CM1 instance offset macros
3  *
4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley (paul@pwsan.com)
8  * Rajendra Nayak (rnayak@ti.com)
9  * Benoit Cousson (b-cousson@ti.com)
10  *
11  * This file is automatically generated from the OMAP hardware databases.
12  * We respectfully ask that any modifications to this file be coordinated
13  * with the public linux-omap@vger.kernel.org mailing list and the
14  * authors above to ensure that the autogeneration scripts are kept
15  * up-to-date with the file contents.
16  *
17  * This program is free software; you can redistribute it and/or modify
18  * it under the terms of the GNU General Public License version 2 as
19  * published by the Free Software Foundation.
20  *
21  * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX",
22  *     or "OMAP4430".
23  */
24
25 #ifndef __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
26 #define __ARCH_ARM_MACH_OMAP2_CM1_44XX_H
27
28 /* CM1 base address */
29 #define OMAP4430_CM1_BASE               0x4a004000
30
31 #define OMAP44XX_CM1_REGADDR(inst, reg)                         \
32         OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
33
34 /* CM1 instances */
35 #define OMAP4430_CM1_OCP_SOCKET_INST    0x0000
36 #define OMAP4430_CM1_CKGEN_INST         0x0100
37 #define OMAP4430_CM1_MPU_INST           0x0300
38 #define OMAP4430_CM1_TESLA_INST         0x0400
39 #define OMAP4430_CM1_ABE_INST           0x0500
40 #define OMAP4430_CM1_RESTORE_INST       0x0e00
41 #define OMAP4430_CM1_INSTR_INST         0x0f00
42
43 /* CM1 clockdomain register offsets (from instance start) */
44 #define OMAP4430_CM1_MPU_MPU_CDOFFS     0x0000
45 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
46 #define OMAP4430_CM1_ABE_ABE_CDOFFS     0x0000
47
48 /* CM1 */
49
50 /* CM1.OCP_SOCKET_CM1 register offsets */
51 #define OMAP4_REVISION_CM1_OFFSET                       0x0000
52 #define OMAP4430_REVISION_CM1                           OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000)
53 #define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET           0x0040
54 #define OMAP4430_CM_CM1_PROFILING_CLKCTRL               OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040)
55
56 /* CM1.CKGEN_CM1 register offsets */
57 #define OMAP4_CM_CLKSEL_CORE_OFFSET                     0x0000
58 #define OMAP4430_CM_CLKSEL_CORE                         OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000)
59 #define OMAP4_CM_CLKSEL_ABE_OFFSET                      0x0008
60 #define OMAP4430_CM_CLKSEL_ABE                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008)
61 #define OMAP4_CM_DLL_CTRL_OFFSET                        0x0010
62 #define OMAP4430_CM_DLL_CTRL                            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010)
63 #define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET               0x0020
64 #define OMAP4430_CM_CLKMODE_DPLL_CORE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020)
65 #define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET                0x0024
66 #define OMAP4430_CM_IDLEST_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024)
67 #define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET              0x0028
68 #define OMAP4430_CM_AUTOIDLE_DPLL_CORE                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028)
69 #define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET                0x002c
70 #define OMAP4430_CM_CLKSEL_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c)
71 #define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET                0x0030
72 #define OMAP4430_CM_DIV_M2_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030)
73 #define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET                0x0034
74 #define OMAP4430_CM_DIV_M3_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034)
75 #define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET                0x0038
76 #define OMAP4430_CM_DIV_M4_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038)
77 #define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET                0x003c
78 #define OMAP4430_CM_DIV_M5_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c)
79 #define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET                0x0040
80 #define OMAP4430_CM_DIV_M6_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040)
81 #define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET                0x0044
82 #define OMAP4430_CM_DIV_M7_DPLL_CORE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
83 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET        0x0048
84 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
85 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET        0x004c
86 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE            OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
87 #define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET          0x0050
88 #define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE              OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
89 #define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET                0x0060
90 #define OMAP4430_CM_CLKMODE_DPLL_MPU                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060)
91 #define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET                 0x0064
92 #define OMAP4430_CM_IDLEST_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064)
93 #define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET               0x0068
94 #define OMAP4430_CM_AUTOIDLE_DPLL_MPU                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068)
95 #define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET                 0x006c
96 #define OMAP4430_CM_CLKSEL_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c)
97 #define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET                 0x0070
98 #define OMAP4430_CM_DIV_M2_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
99 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET         0x0088
100 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
101 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET         0x008c
102 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
103 #define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET                 0x009c
104 #define OMAP4430_CM_BYPCLK_DPLL_MPU                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
105 #define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET                0x00a0
106 #define OMAP4430_CM_CLKMODE_DPLL_IVA                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0)
107 #define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET                 0x00a4
108 #define OMAP4430_CM_IDLEST_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4)
109 #define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET               0x00a8
110 #define OMAP4430_CM_AUTOIDLE_DPLL_IVA                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8)
111 #define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET                 0x00ac
112 #define OMAP4430_CM_CLKSEL_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac)
113 #define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET                 0x00b8
114 #define OMAP4430_CM_DIV_M4_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8)
115 #define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET                 0x00bc
116 #define OMAP4430_CM_DIV_M5_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
117 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET         0x00c8
118 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
119 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET         0x00cc
120 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
121 #define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET                 0x00dc
122 #define OMAP4430_CM_BYPCLK_DPLL_IVA                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
123 #define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET                0x00e0
124 #define OMAP4430_CM_CLKMODE_DPLL_ABE                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0)
125 #define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET                 0x00e4
126 #define OMAP4430_CM_IDLEST_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4)
127 #define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET               0x00e8
128 #define OMAP4430_CM_AUTOIDLE_DPLL_ABE                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8)
129 #define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET                 0x00ec
130 #define OMAP4430_CM_CLKSEL_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec)
131 #define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET                 0x00f0
132 #define OMAP4430_CM_DIV_M2_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0)
133 #define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET                 0x00f4
134 #define OMAP4430_CM_DIV_M3_DPLL_ABE                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
135 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET         0x0108
136 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
137 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET         0x010c
138 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE             OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
139 #define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET             0x0120
140 #define OMAP4430_CM_CLKMODE_DPLL_DDRPHY                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
141 #define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET              0x0124
142 #define OMAP4430_CM_IDLEST_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124)
143 #define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET            0x0128
144 #define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128)
145 #define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET              0x012c
146 #define OMAP4430_CM_CLKSEL_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c)
147 #define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET              0x0130
148 #define OMAP4430_CM_DIV_M2_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130)
149 #define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET              0x0138
150 #define OMAP4430_CM_DIV_M4_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138)
151 #define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET              0x013c
152 #define OMAP4430_CM_DIV_M5_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c)
153 #define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET              0x0140
154 #define OMAP4430_CM_DIV_M6_DPLL_DDRPHY                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
155 #define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET      0x0148
156 #define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
157 #define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET      0x014c
158 #define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
159 #define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET             0x0160
160 #define OMAP4430_CM_SHADOW_FREQ_CONFIG1                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
161 #define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET             0x0164
162 #define OMAP4430_CM_SHADOW_FREQ_CONFIG2                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164)
163 #define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET                 0x0170
164 #define OMAP4430_CM_DYN_DEP_PRESCAL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170)
165 #define OMAP4_CM_RESTORE_ST_OFFSET                      0x0180
166 #define OMAP4430_CM_RESTORE_ST                          OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180)
167
168 /* CM1.MPU_CM1 register offsets */
169 #define OMAP4_CM_MPU_CLKSTCTRL_OFFSET                   0x0000
170 #define OMAP4430_CM_MPU_CLKSTCTRL                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000)
171 #define OMAP4_CM_MPU_STATICDEP_OFFSET                   0x0004
172 #define OMAP4430_CM_MPU_STATICDEP                       OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004)
173 #define OMAP4_CM_MPU_DYNAMICDEP_OFFSET                  0x0008
174 #define OMAP4430_CM_MPU_DYNAMICDEP                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008)
175 #define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET                 0x0020
176 #define OMAP4430_CM_MPU_MPU_CLKCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020)
177
178 /* CM1.TESLA_CM1 register offsets */
179 #define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET                 0x0000
180 #define OMAP4430_CM_TESLA_CLKSTCTRL                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000)
181 #define OMAP4_CM_TESLA_STATICDEP_OFFSET                 0x0004
182 #define OMAP4430_CM_TESLA_STATICDEP                     OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004)
183 #define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET                0x0008
184 #define OMAP4430_CM_TESLA_DYNAMICDEP                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008)
185 #define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET             0x0020
186 #define OMAP4430_CM_TESLA_TESLA_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020)
187
188 /* CM1.ABE_CM1 register offsets */
189 #define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET                  0x0000
190 #define OMAP4430_CM1_ABE_CLKSTCTRL                      OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000)
191 #define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET              0x0020
192 #define OMAP4430_CM1_ABE_L4ABE_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020)
193 #define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET               0x0028
194 #define OMAP4430_CM1_ABE_AESS_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028)
195 #define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET                0x0030
196 #define OMAP4430_CM1_ABE_PDM_CLKCTRL                    OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030)
197 #define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET               0x0038
198 #define OMAP4430_CM1_ABE_DMIC_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038)
199 #define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET              0x0040
200 #define OMAP4430_CM1_ABE_MCASP_CLKCTRL                  OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040)
201 #define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET             0x0048
202 #define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048)
203 #define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET             0x0050
204 #define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050)
205 #define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET             0x0058
206 #define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058)
207 #define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET            0x0060
208 #define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL                OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060)
209 #define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET             0x0068
210 #define OMAP4430_CM1_ABE_TIMER5_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068)
211 #define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET             0x0070
212 #define OMAP4430_CM1_ABE_TIMER6_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070)
213 #define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET             0x0078
214 #define OMAP4430_CM1_ABE_TIMER7_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078)
215 #define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET             0x0080
216 #define OMAP4430_CM1_ABE_TIMER8_CLKCTRL                 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080)
217 #define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET               0x0088
218 #define OMAP4430_CM1_ABE_WDT3_CLKCTRL                   OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
219
220 /* Function prototypes */
221 extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
222 extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
223 extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
224
225 #endif