OMAP clock: drop .id field; ensure each clock has a unique name
[linux-3.10.git] / arch / arm / mach-omap2 / clock3xxx_data.c
1 /*
2  * OMAP3 clock data
3  *
4  * Copyright (C) 2007-2010 Texas Instruments, Inc.
5  * Copyright (C) 2007-2010 Nokia Corporation
6  *
7  * Written by Paul Walmsley
8  * With many device clock fixes by Kevin Hilman and Jouni Högander
9  * DPLL bypass clock support added by Roman Tereshonkov
10  *
11  */
12
13 /*
14  * Virtual clocks are introduced as convenient tools.
15  * They are sources for other clocks and not supposed
16  * to be requested from drivers directly.
17  */
18
19 #include <linux/kernel.h>
20 #include <linux/clk.h>
21 #include <linux/list.h>
22
23 #include <plat/control.h>
24 #include <plat/clkdev_omap.h>
25
26 #include "clock.h"
27 #include "clock3xxx.h"
28 #include "clock34xx.h"
29 #include "clock36xx.h"
30 #include "clock3517.h"
31
32 #include "cm.h"
33 #include "cm-regbits-34xx.h"
34 #include "prm.h"
35 #include "prm-regbits-34xx.h"
36
37 /*
38  * clocks
39  */
40
41 #define OMAP_CM_REGADDR         OMAP34XX_CM_REGADDR
42
43 /* Maximum DPLL multiplier, divider values for OMAP3 */
44 #define OMAP3_MAX_DPLL_MULT             2047
45 #define OMAP3630_MAX_JTYPE_DPLL_MULT    4095
46 #define OMAP3_MAX_DPLL_DIV              128
47
48 /*
49  * DPLL1 supplies clock to the MPU.
50  * DPLL2 supplies clock to the IVA2.
51  * DPLL3 supplies CORE domain clocks.
52  * DPLL4 supplies peripheral clocks.
53  * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
54  */
55
56 /* Forward declarations for DPLL bypass clocks */
57 static struct clk dpll1_fck;
58 static struct clk dpll2_fck;
59
60 /* PRM CLOCKS */
61
62 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
63 static struct clk omap_32k_fck = {
64         .name           = "omap_32k_fck",
65         .ops            = &clkops_null,
66         .rate           = 32768,
67         .flags          = RATE_FIXED,
68 };
69
70 static struct clk secure_32k_fck = {
71         .name           = "secure_32k_fck",
72         .ops            = &clkops_null,
73         .rate           = 32768,
74         .flags          = RATE_FIXED,
75 };
76
77 /* Virtual source clocks for osc_sys_ck */
78 static struct clk virt_12m_ck = {
79         .name           = "virt_12m_ck",
80         .ops            = &clkops_null,
81         .rate           = 12000000,
82         .flags          = RATE_FIXED,
83 };
84
85 static struct clk virt_13m_ck = {
86         .name           = "virt_13m_ck",
87         .ops            = &clkops_null,
88         .rate           = 13000000,
89         .flags          = RATE_FIXED,
90 };
91
92 static struct clk virt_16_8m_ck = {
93         .name           = "virt_16_8m_ck",
94         .ops            = &clkops_null,
95         .rate           = 16800000,
96         .flags          = RATE_FIXED,
97 };
98
99 static struct clk virt_19_2m_ck = {
100         .name           = "virt_19_2m_ck",
101         .ops            = &clkops_null,
102         .rate           = 19200000,
103         .flags          = RATE_FIXED,
104 };
105
106 static struct clk virt_26m_ck = {
107         .name           = "virt_26m_ck",
108         .ops            = &clkops_null,
109         .rate           = 26000000,
110         .flags          = RATE_FIXED,
111 };
112
113 static struct clk virt_38_4m_ck = {
114         .name           = "virt_38_4m_ck",
115         .ops            = &clkops_null,
116         .rate           = 38400000,
117         .flags          = RATE_FIXED,
118 };
119
120 static const struct clksel_rate osc_sys_12m_rates[] = {
121         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
122         { .div = 0 }
123 };
124
125 static const struct clksel_rate osc_sys_13m_rates[] = {
126         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
127         { .div = 0 }
128 };
129
130 static const struct clksel_rate osc_sys_16_8m_rates[] = {
131         { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
132         { .div = 0 }
133 };
134
135 static const struct clksel_rate osc_sys_19_2m_rates[] = {
136         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
137         { .div = 0 }
138 };
139
140 static const struct clksel_rate osc_sys_26m_rates[] = {
141         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
142         { .div = 0 }
143 };
144
145 static const struct clksel_rate osc_sys_38_4m_rates[] = {
146         { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
147         { .div = 0 }
148 };
149
150 static const struct clksel osc_sys_clksel[] = {
151         { .parent = &virt_12m_ck,   .rates = osc_sys_12m_rates },
152         { .parent = &virt_13m_ck,   .rates = osc_sys_13m_rates },
153         { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
154         { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
155         { .parent = &virt_26m_ck,   .rates = osc_sys_26m_rates },
156         { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
157         { .parent = NULL },
158 };
159
160 /* Oscillator clock */
161 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
162 static struct clk osc_sys_ck = {
163         .name           = "osc_sys_ck",
164         .ops            = &clkops_null,
165         .init           = &omap2_init_clksel_parent,
166         .clksel_reg     = OMAP3430_PRM_CLKSEL,
167         .clksel_mask    = OMAP3430_SYS_CLKIN_SEL_MASK,
168         .clksel         = osc_sys_clksel,
169         /* REVISIT: deal with autoextclkmode? */
170         .flags          = RATE_FIXED,
171         .recalc         = &omap2_clksel_recalc,
172 };
173
174 static const struct clksel_rate div2_rates[] = {
175         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
176         { .div = 2, .val = 2, .flags = RATE_IN_343X },
177         { .div = 0 }
178 };
179
180 static const struct clksel sys_clksel[] = {
181         { .parent = &osc_sys_ck, .rates = div2_rates },
182         { .parent = NULL }
183 };
184
185 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
186 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
187 static struct clk sys_ck = {
188         .name           = "sys_ck",
189         .ops            = &clkops_null,
190         .parent         = &osc_sys_ck,
191         .init           = &omap2_init_clksel_parent,
192         .clksel_reg     = OMAP3430_PRM_CLKSRC_CTRL,
193         .clksel_mask    = OMAP_SYSCLKDIV_MASK,
194         .clksel         = sys_clksel,
195         .recalc         = &omap2_clksel_recalc,
196 };
197
198 static struct clk sys_altclk = {
199         .name           = "sys_altclk",
200         .ops            = &clkops_null,
201 };
202
203 /* Optional external clock input for some McBSPs */
204 static struct clk mcbsp_clks = {
205         .name           = "mcbsp_clks",
206         .ops            = &clkops_null,
207 };
208
209 /* PRM EXTERNAL CLOCK OUTPUT */
210
211 static struct clk sys_clkout1 = {
212         .name           = "sys_clkout1",
213         .ops            = &clkops_omap2_dflt,
214         .parent         = &osc_sys_ck,
215         .enable_reg     = OMAP3430_PRM_CLKOUT_CTRL,
216         .enable_bit     = OMAP3430_CLKOUT_EN_SHIFT,
217         .recalc         = &followparent_recalc,
218 };
219
220 /* DPLLS */
221
222 /* CM CLOCKS */
223
224 static const struct clksel_rate div16_dpll_rates[] = {
225         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
226         { .div = 2, .val = 2, .flags = RATE_IN_343X },
227         { .div = 3, .val = 3, .flags = RATE_IN_343X },
228         { .div = 4, .val = 4, .flags = RATE_IN_343X },
229         { .div = 5, .val = 5, .flags = RATE_IN_343X },
230         { .div = 6, .val = 6, .flags = RATE_IN_343X },
231         { .div = 7, .val = 7, .flags = RATE_IN_343X },
232         { .div = 8, .val = 8, .flags = RATE_IN_343X },
233         { .div = 9, .val = 9, .flags = RATE_IN_343X },
234         { .div = 10, .val = 10, .flags = RATE_IN_343X },
235         { .div = 11, .val = 11, .flags = RATE_IN_343X },
236         { .div = 12, .val = 12, .flags = RATE_IN_343X },
237         { .div = 13, .val = 13, .flags = RATE_IN_343X },
238         { .div = 14, .val = 14, .flags = RATE_IN_343X },
239         { .div = 15, .val = 15, .flags = RATE_IN_343X },
240         { .div = 16, .val = 16, .flags = RATE_IN_343X },
241         { .div = 0 }
242 };
243
244 static const struct clksel_rate div32_dpll4_rates_3630[] = {
245         { .div = 1, .val = 1, .flags = RATE_IN_36XX | DEFAULT_RATE },
246         { .div = 2, .val = 2, .flags = RATE_IN_36XX },
247         { .div = 3, .val = 3, .flags = RATE_IN_36XX },
248         { .div = 4, .val = 4, .flags = RATE_IN_36XX },
249         { .div = 5, .val = 5, .flags = RATE_IN_36XX },
250         { .div = 6, .val = 6, .flags = RATE_IN_36XX },
251         { .div = 7, .val = 7, .flags = RATE_IN_36XX },
252         { .div = 8, .val = 8, .flags = RATE_IN_36XX },
253         { .div = 9, .val = 9, .flags = RATE_IN_36XX },
254         { .div = 10, .val = 10, .flags = RATE_IN_36XX },
255         { .div = 11, .val = 11, .flags = RATE_IN_36XX },
256         { .div = 12, .val = 12, .flags = RATE_IN_36XX },
257         { .div = 13, .val = 13, .flags = RATE_IN_36XX },
258         { .div = 14, .val = 14, .flags = RATE_IN_36XX },
259         { .div = 15, .val = 15, .flags = RATE_IN_36XX },
260         { .div = 16, .val = 16, .flags = RATE_IN_36XX },
261         { .div = 17, .val = 17, .flags = RATE_IN_36XX },
262         { .div = 18, .val = 18, .flags = RATE_IN_36XX },
263         { .div = 19, .val = 19, .flags = RATE_IN_36XX },
264         { .div = 20, .val = 20, .flags = RATE_IN_36XX },
265         { .div = 21, .val = 21, .flags = RATE_IN_36XX },
266         { .div = 22, .val = 22, .flags = RATE_IN_36XX },
267         { .div = 23, .val = 23, .flags = RATE_IN_36XX },
268         { .div = 24, .val = 24, .flags = RATE_IN_36XX },
269         { .div = 25, .val = 25, .flags = RATE_IN_36XX },
270         { .div = 26, .val = 26, .flags = RATE_IN_36XX },
271         { .div = 27, .val = 27, .flags = RATE_IN_36XX },
272         { .div = 28, .val = 28, .flags = RATE_IN_36XX },
273         { .div = 29, .val = 29, .flags = RATE_IN_36XX },
274         { .div = 30, .val = 30, .flags = RATE_IN_36XX },
275         { .div = 31, .val = 31, .flags = RATE_IN_36XX },
276         { .div = 32, .val = 32, .flags = RATE_IN_36XX },
277         { .div = 0 }
278 };
279
280 /* DPLL1 */
281 /* MPU clock source */
282 /* Type: DPLL */
283 static struct dpll_data dpll1_dd = {
284         .mult_div1_reg  = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
285         .mult_mask      = OMAP3430_MPU_DPLL_MULT_MASK,
286         .div1_mask      = OMAP3430_MPU_DPLL_DIV_MASK,
287         .clk_bypass     = &dpll1_fck,
288         .clk_ref        = &sys_ck,
289         .freqsel_mask   = OMAP3430_MPU_DPLL_FREQSEL_MASK,
290         .control_reg    = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
291         .enable_mask    = OMAP3430_EN_MPU_DPLL_MASK,
292         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
293         .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
294         .recal_en_bit   = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
295         .recal_st_bit   = OMAP3430_MPU_DPLL_ST_SHIFT,
296         .autoidle_reg   = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
297         .autoidle_mask  = OMAP3430_AUTO_MPU_DPLL_MASK,
298         .idlest_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
299         .idlest_mask    = OMAP3430_ST_MPU_CLK_MASK,
300         .max_multiplier = OMAP3_MAX_DPLL_MULT,
301         .min_divider    = 1,
302         .max_divider    = OMAP3_MAX_DPLL_DIV,
303         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
304 };
305
306 static struct clk dpll1_ck = {
307         .name           = "dpll1_ck",
308         .ops            = &clkops_null,
309         .parent         = &sys_ck,
310         .dpll_data      = &dpll1_dd,
311         .round_rate     = &omap2_dpll_round_rate,
312         .set_rate       = &omap3_noncore_dpll_set_rate,
313         .clkdm_name     = "dpll1_clkdm",
314         .recalc         = &omap3_dpll_recalc,
315 };
316
317 /*
318  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
319  * DPLL isn't bypassed.
320  */
321 static struct clk dpll1_x2_ck = {
322         .name           = "dpll1_x2_ck",
323         .ops            = &clkops_null,
324         .parent         = &dpll1_ck,
325         .clkdm_name     = "dpll1_clkdm",
326         .recalc         = &omap3_clkoutx2_recalc,
327 };
328
329 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
330 static const struct clksel div16_dpll1_x2m2_clksel[] = {
331         { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
332         { .parent = NULL }
333 };
334
335 /*
336  * Does not exist in the TRM - needed to separate the M2 divider from
337  * bypass selection in mpu_ck
338  */
339 static struct clk dpll1_x2m2_ck = {
340         .name           = "dpll1_x2m2_ck",
341         .ops            = &clkops_null,
342         .parent         = &dpll1_x2_ck,
343         .init           = &omap2_init_clksel_parent,
344         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
345         .clksel_mask    = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
346         .clksel         = div16_dpll1_x2m2_clksel,
347         .clkdm_name     = "dpll1_clkdm",
348         .recalc         = &omap2_clksel_recalc,
349 };
350
351 /* DPLL2 */
352 /* IVA2 clock source */
353 /* Type: DPLL */
354
355 static struct dpll_data dpll2_dd = {
356         .mult_div1_reg  = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
357         .mult_mask      = OMAP3430_IVA2_DPLL_MULT_MASK,
358         .div1_mask      = OMAP3430_IVA2_DPLL_DIV_MASK,
359         .clk_bypass     = &dpll2_fck,
360         .clk_ref        = &sys_ck,
361         .freqsel_mask   = OMAP3430_IVA2_DPLL_FREQSEL_MASK,
362         .control_reg    = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
363         .enable_mask    = OMAP3430_EN_IVA2_DPLL_MASK,
364         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
365                                 (1 << DPLL_LOW_POWER_BYPASS),
366         .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
367         .recal_en_bit   = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
368         .recal_st_bit   = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
369         .autoidle_reg   = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
370         .autoidle_mask  = OMAP3430_AUTO_IVA2_DPLL_MASK,
371         .idlest_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
372         .idlest_mask    = OMAP3430_ST_IVA2_CLK_MASK,
373         .max_multiplier = OMAP3_MAX_DPLL_MULT,
374         .min_divider    = 1,
375         .max_divider    = OMAP3_MAX_DPLL_DIV,
376         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
377 };
378
379 static struct clk dpll2_ck = {
380         .name           = "dpll2_ck",
381         .ops            = &clkops_omap3_noncore_dpll_ops,
382         .parent         = &sys_ck,
383         .dpll_data      = &dpll2_dd,
384         .round_rate     = &omap2_dpll_round_rate,
385         .set_rate       = &omap3_noncore_dpll_set_rate,
386         .clkdm_name     = "dpll2_clkdm",
387         .recalc         = &omap3_dpll_recalc,
388 };
389
390 static const struct clksel div16_dpll2_m2x2_clksel[] = {
391         { .parent = &dpll2_ck, .rates = div16_dpll_rates },
392         { .parent = NULL }
393 };
394
395 /*
396  * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
397  * or CLKOUTX2. CLKOUT seems most plausible.
398  */
399 static struct clk dpll2_m2_ck = {
400         .name           = "dpll2_m2_ck",
401         .ops            = &clkops_null,
402         .parent         = &dpll2_ck,
403         .init           = &omap2_init_clksel_parent,
404         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
405                                           OMAP3430_CM_CLKSEL2_PLL),
406         .clksel_mask    = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
407         .clksel         = div16_dpll2_m2x2_clksel,
408         .clkdm_name     = "dpll2_clkdm",
409         .recalc         = &omap2_clksel_recalc,
410 };
411
412 /*
413  * DPLL3
414  * Source clock for all interfaces and for some device fclks
415  * REVISIT: Also supports fast relock bypass - not included below
416  */
417 static struct dpll_data dpll3_dd = {
418         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
419         .mult_mask      = OMAP3430_CORE_DPLL_MULT_MASK,
420         .div1_mask      = OMAP3430_CORE_DPLL_DIV_MASK,
421         .clk_bypass     = &sys_ck,
422         .clk_ref        = &sys_ck,
423         .freqsel_mask   = OMAP3430_CORE_DPLL_FREQSEL_MASK,
424         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
425         .enable_mask    = OMAP3430_EN_CORE_DPLL_MASK,
426         .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
427         .recal_en_bit   = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
428         .recal_st_bit   = OMAP3430_CORE_DPLL_ST_SHIFT,
429         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
430         .autoidle_mask  = OMAP3430_AUTO_CORE_DPLL_MASK,
431         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
432         .idlest_mask    = OMAP3430_ST_CORE_CLK_MASK,
433         .max_multiplier = OMAP3_MAX_DPLL_MULT,
434         .min_divider    = 1,
435         .max_divider    = OMAP3_MAX_DPLL_DIV,
436         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
437 };
438
439 static struct clk dpll3_ck = {
440         .name           = "dpll3_ck",
441         .ops            = &clkops_null,
442         .parent         = &sys_ck,
443         .dpll_data      = &dpll3_dd,
444         .round_rate     = &omap2_dpll_round_rate,
445         .clkdm_name     = "dpll3_clkdm",
446         .recalc         = &omap3_dpll_recalc,
447 };
448
449 /*
450  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
451  * DPLL isn't bypassed
452  */
453 static struct clk dpll3_x2_ck = {
454         .name           = "dpll3_x2_ck",
455         .ops            = &clkops_null,
456         .parent         = &dpll3_ck,
457         .clkdm_name     = "dpll3_clkdm",
458         .recalc         = &omap3_clkoutx2_recalc,
459 };
460
461 static const struct clksel_rate div31_dpll3_rates[] = {
462         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
463         { .div = 2, .val = 2, .flags = RATE_IN_343X },
464         { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
465         { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
466         { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
467         { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
468         { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
469         { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
470         { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
471         { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
472         { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
473         { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
474         { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
475         { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
476         { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
477         { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
478         { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
479         { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
480         { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
481         { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
482         { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
483         { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
484         { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
485         { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
486         { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
487         { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
488         { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
489         { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
490         { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
491         { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
492         { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
493         { .div = 0 },
494 };
495
496 static const struct clksel div31_dpll3m2_clksel[] = {
497         { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
498         { .parent = NULL }
499 };
500
501 /* DPLL3 output M2 - primary control point for CORE speed */
502 static struct clk dpll3_m2_ck = {
503         .name           = "dpll3_m2_ck",
504         .ops            = &clkops_null,
505         .parent         = &dpll3_ck,
506         .init           = &omap2_init_clksel_parent,
507         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
508         .clksel_mask    = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
509         .clksel         = div31_dpll3m2_clksel,
510         .clkdm_name     = "dpll3_clkdm",
511         .round_rate     = &omap2_clksel_round_rate,
512         .set_rate       = &omap3_core_dpll_m2_set_rate,
513         .recalc         = &omap2_clksel_recalc,
514 };
515
516 static struct clk core_ck = {
517         .name           = "core_ck",
518         .ops            = &clkops_null,
519         .parent         = &dpll3_m2_ck,
520         .recalc         = &followparent_recalc,
521 };
522
523 static struct clk dpll3_m2x2_ck = {
524         .name           = "dpll3_m2x2_ck",
525         .ops            = &clkops_null,
526         .parent         = &dpll3_m2_ck,
527         .clkdm_name     = "dpll3_clkdm",
528         .recalc         = &omap3_clkoutx2_recalc,
529 };
530
531 /* The PWRDN bit is apparently only available on 3430ES2 and above */
532 static const struct clksel div16_dpll3_clksel[] = {
533         { .parent = &dpll3_ck, .rates = div16_dpll_rates },
534         { .parent = NULL }
535 };
536
537 /* This virtual clock is the source for dpll3_m3x2_ck */
538 static struct clk dpll3_m3_ck = {
539         .name           = "dpll3_m3_ck",
540         .ops            = &clkops_null,
541         .parent         = &dpll3_ck,
542         .init           = &omap2_init_clksel_parent,
543         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
544         .clksel_mask    = OMAP3430_DIV_DPLL3_MASK,
545         .clksel         = div16_dpll3_clksel,
546         .clkdm_name     = "dpll3_clkdm",
547         .recalc         = &omap2_clksel_recalc,
548 };
549
550 /* The PWRDN bit is apparently only available on 3430ES2 and above */
551 static struct clk dpll3_m3x2_ck = {
552         .name           = "dpll3_m3x2_ck",
553         .ops            = &clkops_omap2_dflt_wait,
554         .parent         = &dpll3_m3_ck,
555         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
556         .enable_bit     = OMAP3430_PWRDN_EMU_CORE_SHIFT,
557         .flags          = INVERT_ENABLE,
558         .clkdm_name     = "dpll3_clkdm",
559         .recalc         = &omap3_clkoutx2_recalc,
560 };
561
562 static struct clk emu_core_alwon_ck = {
563         .name           = "emu_core_alwon_ck",
564         .ops            = &clkops_null,
565         .parent         = &dpll3_m3x2_ck,
566         .clkdm_name     = "dpll3_clkdm",
567         .recalc         = &followparent_recalc,
568 };
569
570 /* DPLL4 */
571 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
572 /* Type: DPLL */
573 static struct dpll_data dpll4_dd;
574 static struct dpll_data dpll4_dd_34xx __initdata = {
575         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
576         .mult_mask      = OMAP3430_PERIPH_DPLL_MULT_MASK,
577         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
578         .clk_bypass     = &sys_ck,
579         .clk_ref        = &sys_ck,
580         .freqsel_mask   = OMAP3430_PERIPH_DPLL_FREQSEL_MASK,
581         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
582         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
583         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
584         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
585         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
586         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
587         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
588         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
589         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
590         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
591         .max_multiplier = OMAP3_MAX_DPLL_MULT,
592         .min_divider    = 1,
593         .max_divider    = OMAP3_MAX_DPLL_DIV,
594         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
595 };
596
597 static struct dpll_data dpll4_dd_3630 __initdata = {
598         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
599         .mult_mask      = OMAP3630_PERIPH_DPLL_MULT_MASK,
600         .div1_mask      = OMAP3430_PERIPH_DPLL_DIV_MASK,
601         .clk_bypass     = &sys_ck,
602         .clk_ref        = &sys_ck,
603         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
604         .enable_mask    = OMAP3430_EN_PERIPH_DPLL_MASK,
605         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
606         .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
607         .recal_en_bit   = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
608         .recal_st_bit   = OMAP3430_PERIPH_DPLL_ST_SHIFT,
609         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
610         .autoidle_mask  = OMAP3430_AUTO_PERIPH_DPLL_MASK,
611         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
612         .idlest_mask    = OMAP3430_ST_PERIPH_CLK_MASK,
613         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
614         .min_divider    = 1,
615         .max_divider    = OMAP3_MAX_DPLL_DIV,
616         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
617         .flags          = DPLL_J_TYPE
618 };
619
620 static struct clk dpll4_ck = {
621         .name           = "dpll4_ck",
622         .ops            = &clkops_omap3_noncore_dpll_ops,
623         .parent         = &sys_ck,
624         .dpll_data      = &dpll4_dd,
625         .round_rate     = &omap2_dpll_round_rate,
626         .set_rate       = &omap3_dpll4_set_rate,
627         .clkdm_name     = "dpll4_clkdm",
628         .recalc         = &omap3_dpll_recalc,
629 };
630
631 /*
632  * This virtual clock provides the CLKOUTX2 output from the DPLL if the
633  * DPLL isn't bypassed --
634  * XXX does this serve any downstream clocks?
635  */
636 static struct clk dpll4_x2_ck = {
637         .name           = "dpll4_x2_ck",
638         .ops            = &clkops_null,
639         .parent         = &dpll4_ck,
640         .clkdm_name     = "dpll4_clkdm",
641         .recalc         = &omap3_clkoutx2_recalc,
642 };
643
644 static const struct clksel div16_dpll4_clksel[] = {
645         { .parent = &dpll4_ck, .rates = div16_dpll_rates },
646         { .parent = NULL }
647 };
648
649 static const struct clksel div32_dpll4_clksel[] = {
650         { .parent = &dpll4_ck, .rates = div32_dpll4_rates_3630 },
651         { .parent = NULL }
652 };
653
654 /* This virtual clock is the source for dpll4_m2x2_ck */
655 static struct clk dpll4_m2_ck;
656
657 static struct clk dpll4_m2_ck_34xx __initdata = {
658         .name           = "dpll4_m2_ck",
659         .ops            = &clkops_null,
660         .parent         = &dpll4_ck,
661         .init           = &omap2_init_clksel_parent,
662         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
663         .clksel_mask    = OMAP3430_DIV_96M_MASK,
664         .clksel         = div16_dpll4_clksel,
665         .clkdm_name     = "dpll4_clkdm",
666         .recalc         = &omap2_clksel_recalc,
667 };
668
669 static struct clk dpll4_m2_ck_3630 __initdata  = {
670         .name           = "dpll4_m2_ck",
671         .ops            = &clkops_null,
672         .parent         = &dpll4_ck,
673         .init           = &omap2_init_clksel_parent,
674         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
675         .clksel_mask    = OMAP3630_DIV_96M_MASK,
676         .clksel         = div32_dpll4_clksel,
677         .clkdm_name     = "dpll4_clkdm",
678         .recalc         = &omap2_clksel_recalc,
679 };
680
681 /* The PWRDN bit is apparently only available on 3430ES2 and above */
682 static struct clk dpll4_m2x2_ck = {
683         .name           = "dpll4_m2x2_ck",
684         .ops            = &clkops_omap2_dflt_wait,
685         .parent         = &dpll4_m2_ck,
686         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
687         .enable_bit     = OMAP3430_PWRDN_96M_SHIFT,
688         .flags          = INVERT_ENABLE,
689         .clkdm_name     = "dpll4_clkdm",
690         .recalc         = &omap3_clkoutx2_recalc,
691 };
692
693 /*
694  * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as
695  * PRM_96M_ALWON_(F)CLK.  Two clocks then emerge from the PRM:
696  * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and
697  * CM_96K_(F)CLK.
698  */
699
700 /* Adding 192MHz Clock node needed by SGX */
701 static struct clk omap_192m_alwon_fck = {
702         .name           = "omap_192m_alwon_fck",
703         .ops            = &clkops_null,
704         .parent         = &dpll4_m2x2_ck,
705         .recalc         = &followparent_recalc,
706 };
707
708 static const struct clksel_rate omap_96m_alwon_fck_rates[] = {
709         { .div = 1, .val = 1, .flags = RATE_IN_36XX },
710         { .div = 2, .val = 2, .flags = RATE_IN_36XX | DEFAULT_RATE },
711         { .div = 0 }
712 };
713
714 static const struct clksel omap_96m_alwon_fck_clksel[] = {
715         { .parent = &omap_192m_alwon_fck, .rates = omap_96m_alwon_fck_rates },
716         { .parent = NULL }
717 };
718
719 static const struct clksel_rate omap_96m_dpll_rates[] = {
720         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
721         { .div = 0 }
722 };
723
724 static const struct clksel_rate omap_96m_sys_rates[] = {
725         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
726         { .div = 0 }
727 };
728
729 static struct clk omap_96m_alwon_fck = {
730         .name           = "omap_96m_alwon_fck",
731         .ops            = &clkops_null,
732         .parent         = &dpll4_m2x2_ck,
733         .recalc         = &followparent_recalc,
734 };
735
736 static struct clk omap_96m_alwon_fck_3630 = {
737         .name           = "omap_96m_alwon_fck",
738         .parent         = &omap_192m_alwon_fck,
739         .init           = &omap2_init_clksel_parent,
740         .ops            = &clkops_null,
741         .recalc         = &omap2_clksel_recalc,
742         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
743         .clksel_mask    = OMAP3630_CLKSEL_96M_MASK,
744         .clksel         = omap_96m_alwon_fck_clksel
745 };
746
747 static struct clk cm_96m_fck = {
748         .name           = "cm_96m_fck",
749         .ops            = &clkops_null,
750         .parent         = &omap_96m_alwon_fck,
751         .recalc         = &followparent_recalc,
752 };
753
754 static const struct clksel omap_96m_fck_clksel[] = {
755         { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates },
756         { .parent = &sys_ck,     .rates = omap_96m_sys_rates },
757         { .parent = NULL }
758 };
759
760 static struct clk omap_96m_fck = {
761         .name           = "omap_96m_fck",
762         .ops            = &clkops_null,
763         .parent         = &sys_ck,
764         .init           = &omap2_init_clksel_parent,
765         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
766         .clksel_mask    = OMAP3430_SOURCE_96M_MASK,
767         .clksel         = omap_96m_fck_clksel,
768         .recalc         = &omap2_clksel_recalc,
769 };
770
771 /* This virtual clock is the source for dpll4_m3x2_ck */
772 static struct clk dpll4_m3_ck;
773
774 static struct clk dpll4_m3_ck_34xx __initdata = {
775         .name           = "dpll4_m3_ck",
776         .ops            = &clkops_null,
777         .parent         = &dpll4_ck,
778         .init           = &omap2_init_clksel_parent,
779         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
780         .clksel_mask    = OMAP3430_CLKSEL_TV_MASK,
781         .clksel         = div16_dpll4_clksel,
782         .clkdm_name     = "dpll4_clkdm",
783         .recalc         = &omap2_clksel_recalc,
784 };
785
786 static struct clk dpll4_m3_ck_3630 __initdata = {
787         .name           = "dpll4_m3_ck",
788         .ops            = &clkops_null,
789         .parent         = &dpll4_ck,
790         .init           = &omap2_init_clksel_parent,
791         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
792         .clksel_mask    = OMAP3630_CLKSEL_TV_MASK,
793         .clksel         = div32_dpll4_clksel,
794         .clkdm_name     = "dpll4_clkdm",
795         .recalc         = &omap2_clksel_recalc,
796 };
797
798 /* The PWRDN bit is apparently only available on 3430ES2 and above */
799 static struct clk dpll4_m3x2_ck = {
800         .name           = "dpll4_m3x2_ck",
801         .ops            = &clkops_omap2_dflt_wait,
802         .parent         = &dpll4_m3_ck,
803         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
804         .enable_bit     = OMAP3430_PWRDN_TV_SHIFT,
805         .flags          = INVERT_ENABLE,
806         .clkdm_name     = "dpll4_clkdm",
807         .recalc         = &omap3_clkoutx2_recalc,
808 };
809
810 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
811         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
812         { .div = 0 }
813 };
814
815 static const struct clksel_rate omap_54m_alt_rates[] = {
816         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
817         { .div = 0 }
818 };
819
820 static const struct clksel omap_54m_clksel[] = {
821         { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates },
822         { .parent = &sys_altclk,    .rates = omap_54m_alt_rates },
823         { .parent = NULL }
824 };
825
826 static struct clk omap_54m_fck = {
827         .name           = "omap_54m_fck",
828         .ops            = &clkops_null,
829         .init           = &omap2_init_clksel_parent,
830         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
831         .clksel_mask    = OMAP3430_SOURCE_54M_MASK,
832         .clksel         = omap_54m_clksel,
833         .recalc         = &omap2_clksel_recalc,
834 };
835
836 static const struct clksel_rate omap_48m_cm96m_rates[] = {
837         { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
838         { .div = 0 }
839 };
840
841 static const struct clksel_rate omap_48m_alt_rates[] = {
842         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
843         { .div = 0 }
844 };
845
846 static const struct clksel omap_48m_clksel[] = {
847         { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates },
848         { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
849         { .parent = NULL }
850 };
851
852 static struct clk omap_48m_fck = {
853         .name           = "omap_48m_fck",
854         .ops            = &clkops_null,
855         .init           = &omap2_init_clksel_parent,
856         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
857         .clksel_mask    = OMAP3430_SOURCE_48M_MASK,
858         .clksel         = omap_48m_clksel,
859         .recalc         = &omap2_clksel_recalc,
860 };
861
862 static struct clk omap_12m_fck = {
863         .name           = "omap_12m_fck",
864         .ops            = &clkops_null,
865         .parent         = &omap_48m_fck,
866         .fixed_div      = 4,
867         .recalc         = &omap_fixed_divisor_recalc,
868 };
869
870 /* This virstual clock is the source for dpll4_m4x2_ck */
871 static struct clk dpll4_m4_ck;
872
873 static struct clk dpll4_m4_ck_34xx __initdata = {
874         .name           = "dpll4_m4_ck",
875         .ops            = &clkops_null,
876         .parent         = &dpll4_ck,
877         .init           = &omap2_init_clksel_parent,
878         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
879         .clksel_mask    = OMAP3430_CLKSEL_DSS1_MASK,
880         .clksel         = div16_dpll4_clksel,
881         .clkdm_name     = "dpll4_clkdm",
882         .recalc         = &omap2_clksel_recalc,
883         .set_rate       = &omap2_clksel_set_rate,
884         .round_rate     = &omap2_clksel_round_rate,
885 };
886
887 static struct clk dpll4_m4_ck_3630 __initdata = {
888         .name           = "dpll4_m4_ck",
889         .ops            = &clkops_null,
890         .parent         = &dpll4_ck,
891         .init           = &omap2_init_clksel_parent,
892         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
893         .clksel_mask    = OMAP3630_CLKSEL_DSS1_MASK,
894         .clksel         = div32_dpll4_clksel,
895         .clkdm_name     = "dpll4_clkdm",
896         .recalc         = &omap2_clksel_recalc,
897         .set_rate       = &omap2_clksel_set_rate,
898         .round_rate     = &omap2_clksel_round_rate,
899 };
900
901 /* The PWRDN bit is apparently only available on 3430ES2 and above */
902 static struct clk dpll4_m4x2_ck = {
903         .name           = "dpll4_m4x2_ck",
904         .ops            = &clkops_omap2_dflt_wait,
905         .parent         = &dpll4_m4_ck,
906         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
907         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
908         .flags          = INVERT_ENABLE,
909         .clkdm_name     = "dpll4_clkdm",
910         .recalc         = &omap3_clkoutx2_recalc,
911 };
912
913 /* This virtual clock is the source for dpll4_m5x2_ck */
914 static struct clk dpll4_m5_ck;
915
916 static struct clk dpll4_m5_ck_34xx __initdata = {
917         .name           = "dpll4_m5_ck",
918         .ops            = &clkops_null,
919         .parent         = &dpll4_ck,
920         .init           = &omap2_init_clksel_parent,
921         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
922         .clksel_mask    = OMAP3430_CLKSEL_CAM_MASK,
923         .clksel         = div16_dpll4_clksel,
924         .clkdm_name     = "dpll4_clkdm",
925         .set_rate       = &omap2_clksel_set_rate,
926         .round_rate     = &omap2_clksel_round_rate,
927         .recalc         = &omap2_clksel_recalc,
928 };
929
930 static struct clk dpll4_m5_ck_3630 __initdata = {
931         .name           = "dpll4_m5_ck",
932         .ops            = &clkops_null,
933         .parent         = &dpll4_ck,
934         .init           = &omap2_init_clksel_parent,
935         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
936         .clksel_mask    = OMAP3630_CLKSEL_CAM_MASK,
937         .clksel         = div32_dpll4_clksel,
938         .clkdm_name     = "dpll4_clkdm",
939         .recalc         = &omap2_clksel_recalc,
940 };
941
942 /* The PWRDN bit is apparently only available on 3430ES2 and above */
943 static struct clk dpll4_m5x2_ck = {
944         .name           = "dpll4_m5x2_ck",
945         .ops            = &clkops_omap2_dflt_wait,
946         .parent         = &dpll4_m5_ck,
947         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
948         .enable_bit     = OMAP3430_PWRDN_CAM_SHIFT,
949         .flags          = INVERT_ENABLE,
950         .clkdm_name     = "dpll4_clkdm",
951         .recalc         = &omap3_clkoutx2_recalc,
952 };
953
954 /* This virtual clock is the source for dpll4_m6x2_ck */
955 static struct clk dpll4_m6_ck;
956
957 static struct clk dpll4_m6_ck_34xx __initdata = {
958         .name           = "dpll4_m6_ck",
959         .ops            = &clkops_null,
960         .parent         = &dpll4_ck,
961         .init           = &omap2_init_clksel_parent,
962         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
963         .clksel_mask    = OMAP3430_DIV_DPLL4_MASK,
964         .clksel         = div16_dpll4_clksel,
965         .clkdm_name     = "dpll4_clkdm",
966         .recalc         = &omap2_clksel_recalc,
967 };
968
969 static struct clk dpll4_m6_ck_3630 __initdata = {
970         .name           = "dpll4_m6_ck",
971         .ops            = &clkops_null,
972         .parent         = &dpll4_ck,
973         .init           = &omap2_init_clksel_parent,
974         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
975         .clksel_mask    = OMAP3630_DIV_DPLL4_MASK,
976         .clksel         = div32_dpll4_clksel,
977         .clkdm_name     = "dpll4_clkdm",
978         .recalc         = &omap2_clksel_recalc,
979 };
980
981 /* The PWRDN bit is apparently only available on 3430ES2 and above */
982 static struct clk dpll4_m6x2_ck = {
983         .name           = "dpll4_m6x2_ck",
984         .ops            = &clkops_omap2_dflt_wait,
985         .parent         = &dpll4_m6_ck,
986         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
987         .enable_bit     = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
988         .flags          = INVERT_ENABLE,
989         .clkdm_name     = "dpll4_clkdm",
990         .recalc         = &omap3_clkoutx2_recalc,
991 };
992
993 static struct clk emu_per_alwon_ck = {
994         .name           = "emu_per_alwon_ck",
995         .ops            = &clkops_null,
996         .parent         = &dpll4_m6x2_ck,
997         .clkdm_name     = "dpll4_clkdm",
998         .recalc         = &followparent_recalc,
999 };
1000
1001 /* DPLL5 */
1002 /* Supplies 120MHz clock, USIM source clock */
1003 /* Type: DPLL */
1004 /* 3430ES2 only */
1005 static struct dpll_data dpll5_dd = {
1006         .mult_div1_reg  = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
1007         .mult_mask      = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
1008         .div1_mask      = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
1009         .clk_bypass     = &sys_ck,
1010         .clk_ref        = &sys_ck,
1011         .freqsel_mask   = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK,
1012         .control_reg    = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
1013         .enable_mask    = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
1014         .modes          = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
1015         .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
1016         .recal_en_bit   = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
1017         .recal_st_bit   = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
1018         .autoidle_reg   = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
1019         .autoidle_mask  = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
1020         .idlest_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
1021         .idlest_mask    = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
1022         .max_multiplier = OMAP3_MAX_DPLL_MULT,
1023         .min_divider    = 1,
1024         .max_divider    = OMAP3_MAX_DPLL_DIV,
1025         .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
1026 };
1027
1028 static struct clk dpll5_ck = {
1029         .name           = "dpll5_ck",
1030         .ops            = &clkops_omap3_noncore_dpll_ops,
1031         .parent         = &sys_ck,
1032         .dpll_data      = &dpll5_dd,
1033         .round_rate     = &omap2_dpll_round_rate,
1034         .set_rate       = &omap3_noncore_dpll_set_rate,
1035         .clkdm_name     = "dpll5_clkdm",
1036         .recalc         = &omap3_dpll_recalc,
1037 };
1038
1039 static const struct clksel div16_dpll5_clksel[] = {
1040         { .parent = &dpll5_ck, .rates = div16_dpll_rates },
1041         { .parent = NULL }
1042 };
1043
1044 static struct clk dpll5_m2_ck = {
1045         .name           = "dpll5_m2_ck",
1046         .ops            = &clkops_null,
1047         .parent         = &dpll5_ck,
1048         .init           = &omap2_init_clksel_parent,
1049         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
1050         .clksel_mask    = OMAP3430ES2_DIV_120M_MASK,
1051         .clksel         = div16_dpll5_clksel,
1052         .clkdm_name     = "dpll5_clkdm",
1053         .recalc         = &omap2_clksel_recalc,
1054 };
1055
1056 /* CM EXTERNAL CLOCK OUTPUTS */
1057
1058 static const struct clksel_rate clkout2_src_core_rates[] = {
1059         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1060         { .div = 0 }
1061 };
1062
1063 static const struct clksel_rate clkout2_src_sys_rates[] = {
1064         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1065         { .div = 0 }
1066 };
1067
1068 static const struct clksel_rate clkout2_src_96m_rates[] = {
1069         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
1070         { .div = 0 }
1071 };
1072
1073 static const struct clksel_rate clkout2_src_54m_rates[] = {
1074         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1075         { .div = 0 }
1076 };
1077
1078 static const struct clksel clkout2_src_clksel[] = {
1079         { .parent = &core_ck,           .rates = clkout2_src_core_rates },
1080         { .parent = &sys_ck,            .rates = clkout2_src_sys_rates },
1081         { .parent = &cm_96m_fck,        .rates = clkout2_src_96m_rates },
1082         { .parent = &omap_54m_fck,      .rates = clkout2_src_54m_rates },
1083         { .parent = NULL }
1084 };
1085
1086 static struct clk clkout2_src_ck = {
1087         .name           = "clkout2_src_ck",
1088         .ops            = &clkops_omap2_dflt,
1089         .init           = &omap2_init_clksel_parent,
1090         .enable_reg     = OMAP3430_CM_CLKOUT_CTRL,
1091         .enable_bit     = OMAP3430_CLKOUT2_EN_SHIFT,
1092         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1093         .clksel_mask    = OMAP3430_CLKOUT2SOURCE_MASK,
1094         .clksel         = clkout2_src_clksel,
1095         .clkdm_name     = "core_clkdm",
1096         .recalc         = &omap2_clksel_recalc,
1097 };
1098
1099 static const struct clksel_rate sys_clkout2_rates[] = {
1100         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1101         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1102         { .div = 4, .val = 2, .flags = RATE_IN_343X },
1103         { .div = 8, .val = 3, .flags = RATE_IN_343X },
1104         { .div = 16, .val = 4, .flags = RATE_IN_343X },
1105         { .div = 0 },
1106 };
1107
1108 static const struct clksel sys_clkout2_clksel[] = {
1109         { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
1110         { .parent = NULL },
1111 };
1112
1113 static struct clk sys_clkout2 = {
1114         .name           = "sys_clkout2",
1115         .ops            = &clkops_null,
1116         .init           = &omap2_init_clksel_parent,
1117         .clksel_reg     = OMAP3430_CM_CLKOUT_CTRL,
1118         .clksel_mask    = OMAP3430_CLKOUT2_DIV_MASK,
1119         .clksel         = sys_clkout2_clksel,
1120         .recalc         = &omap2_clksel_recalc,
1121 };
1122
1123 /* CM OUTPUT CLOCKS */
1124
1125 static struct clk corex2_fck = {
1126         .name           = "corex2_fck",
1127         .ops            = &clkops_null,
1128         .parent         = &dpll3_m2x2_ck,
1129         .recalc         = &followparent_recalc,
1130 };
1131
1132 /* DPLL power domain clock controls */
1133
1134 static const struct clksel_rate div4_rates[] = {
1135         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1136         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1137         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1138         { .div = 0 }
1139 };
1140
1141 static const struct clksel div4_core_clksel[] = {
1142         { .parent = &core_ck, .rates = div4_rates },
1143         { .parent = NULL }
1144 };
1145
1146 /*
1147  * REVISIT: Are these in DPLL power domain or CM power domain? docs
1148  * may be inconsistent here?
1149  */
1150 static struct clk dpll1_fck = {
1151         .name           = "dpll1_fck",
1152         .ops            = &clkops_null,
1153         .parent         = &core_ck,
1154         .init           = &omap2_init_clksel_parent,
1155         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
1156         .clksel_mask    = OMAP3430_MPU_CLK_SRC_MASK,
1157         .clksel         = div4_core_clksel,
1158         .recalc         = &omap2_clksel_recalc,
1159 };
1160
1161 static struct clk mpu_ck = {
1162         .name           = "mpu_ck",
1163         .ops            = &clkops_null,
1164         .parent         = &dpll1_x2m2_ck,
1165         .clkdm_name     = "mpu_clkdm",
1166         .recalc         = &followparent_recalc,
1167 };
1168
1169 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1170 static const struct clksel_rate arm_fck_rates[] = {
1171         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1172         { .div = 2, .val = 1, .flags = RATE_IN_343X },
1173         { .div = 0 },
1174 };
1175
1176 static const struct clksel arm_fck_clksel[] = {
1177         { .parent = &mpu_ck, .rates = arm_fck_rates },
1178         { .parent = NULL }
1179 };
1180
1181 static struct clk arm_fck = {
1182         .name           = "arm_fck",
1183         .ops            = &clkops_null,
1184         .parent         = &mpu_ck,
1185         .init           = &omap2_init_clksel_parent,
1186         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1187         .clksel_mask    = OMAP3430_ST_MPU_CLK_MASK,
1188         .clksel         = arm_fck_clksel,
1189         .clkdm_name     = "mpu_clkdm",
1190         .recalc         = &omap2_clksel_recalc,
1191 };
1192
1193 /* XXX What about neon_clkdm ? */
1194
1195 /*
1196  * REVISIT: This clock is never specifically defined in the 3430 TRM,
1197  * although it is referenced - so this is a guess
1198  */
1199 static struct clk emu_mpu_alwon_ck = {
1200         .name           = "emu_mpu_alwon_ck",
1201         .ops            = &clkops_null,
1202         .parent         = &mpu_ck,
1203         .recalc         = &followparent_recalc,
1204 };
1205
1206 static struct clk dpll2_fck = {
1207         .name           = "dpll2_fck",
1208         .ops            = &clkops_null,
1209         .parent         = &core_ck,
1210         .init           = &omap2_init_clksel_parent,
1211         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1212         .clksel_mask    = OMAP3430_IVA2_CLK_SRC_MASK,
1213         .clksel         = div4_core_clksel,
1214         .recalc         = &omap2_clksel_recalc,
1215 };
1216
1217 static struct clk iva2_ck = {
1218         .name           = "iva2_ck",
1219         .ops            = &clkops_omap2_dflt_wait,
1220         .parent         = &dpll2_m2_ck,
1221         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1222         .enable_bit     = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1223         .clkdm_name     = "iva2_clkdm",
1224         .recalc         = &followparent_recalc,
1225 };
1226
1227 /* Common interface clocks */
1228
1229 static const struct clksel div2_core_clksel[] = {
1230         { .parent = &core_ck, .rates = div2_rates },
1231         { .parent = NULL }
1232 };
1233
1234 static struct clk l3_ick = {
1235         .name           = "l3_ick",
1236         .ops            = &clkops_null,
1237         .parent         = &core_ck,
1238         .init           = &omap2_init_clksel_parent,
1239         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1240         .clksel_mask    = OMAP3430_CLKSEL_L3_MASK,
1241         .clksel         = div2_core_clksel,
1242         .clkdm_name     = "core_l3_clkdm",
1243         .recalc         = &omap2_clksel_recalc,
1244 };
1245
1246 static const struct clksel div2_l3_clksel[] = {
1247         { .parent = &l3_ick, .rates = div2_rates },
1248         { .parent = NULL }
1249 };
1250
1251 static struct clk l4_ick = {
1252         .name           = "l4_ick",
1253         .ops            = &clkops_null,
1254         .parent         = &l3_ick,
1255         .init           = &omap2_init_clksel_parent,
1256         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1257         .clksel_mask    = OMAP3430_CLKSEL_L4_MASK,
1258         .clksel         = div2_l3_clksel,
1259         .clkdm_name     = "core_l4_clkdm",
1260         .recalc         = &omap2_clksel_recalc,
1261
1262 };
1263
1264 static const struct clksel div2_l4_clksel[] = {
1265         { .parent = &l4_ick, .rates = div2_rates },
1266         { .parent = NULL }
1267 };
1268
1269 static struct clk rm_ick = {
1270         .name           = "rm_ick",
1271         .ops            = &clkops_null,
1272         .parent         = &l4_ick,
1273         .init           = &omap2_init_clksel_parent,
1274         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1275         .clksel_mask    = OMAP3430_CLKSEL_RM_MASK,
1276         .clksel         = div2_l4_clksel,
1277         .recalc         = &omap2_clksel_recalc,
1278 };
1279
1280 /* GFX power domain */
1281
1282 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1283
1284 static const struct clksel gfx_l3_clksel[] = {
1285         { .parent = &l3_ick, .rates = gfx_l3_rates },
1286         { .parent = NULL }
1287 };
1288
1289 /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
1290 static struct clk gfx_l3_ck = {
1291         .name           = "gfx_l3_ck",
1292         .ops            = &clkops_omap2_dflt_wait,
1293         .parent         = &l3_ick,
1294         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1295         .enable_bit     = OMAP_EN_GFX_SHIFT,
1296         .recalc         = &followparent_recalc,
1297 };
1298
1299 static struct clk gfx_l3_fck = {
1300         .name           = "gfx_l3_fck",
1301         .ops            = &clkops_null,
1302         .parent         = &gfx_l3_ck,
1303         .init           = &omap2_init_clksel_parent,
1304         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1305         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
1306         .clksel         = gfx_l3_clksel,
1307         .clkdm_name     = "gfx_3430es1_clkdm",
1308         .recalc         = &omap2_clksel_recalc,
1309 };
1310
1311 static struct clk gfx_l3_ick = {
1312         .name           = "gfx_l3_ick",
1313         .ops            = &clkops_null,
1314         .parent         = &gfx_l3_ck,
1315         .clkdm_name     = "gfx_3430es1_clkdm",
1316         .recalc         = &followparent_recalc,
1317 };
1318
1319 static struct clk gfx_cg1_ck = {
1320         .name           = "gfx_cg1_ck",
1321         .ops            = &clkops_omap2_dflt_wait,
1322         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1323         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1324         .enable_bit     = OMAP3430ES1_EN_2D_SHIFT,
1325         .clkdm_name     = "gfx_3430es1_clkdm",
1326         .recalc         = &followparent_recalc,
1327 };
1328
1329 static struct clk gfx_cg2_ck = {
1330         .name           = "gfx_cg2_ck",
1331         .ops            = &clkops_omap2_dflt_wait,
1332         .parent         = &gfx_l3_fck, /* REVISIT: correct? */
1333         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1334         .enable_bit     = OMAP3430ES1_EN_3D_SHIFT,
1335         .clkdm_name     = "gfx_3430es1_clkdm",
1336         .recalc         = &followparent_recalc,
1337 };
1338
1339 /* SGX power domain - 3430ES2 only */
1340
1341 static const struct clksel_rate sgx_core_rates[] = {
1342         { .div = 2, .val = 5, .flags = RATE_IN_36XX },
1343         { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1344         { .div = 4, .val = 1, .flags = RATE_IN_343X },
1345         { .div = 6, .val = 2, .flags = RATE_IN_343X },
1346         { .div = 0 },
1347 };
1348
1349 static const struct clksel_rate sgx_192m_rates[] = {
1350         { .div = 1,  .val = 4, .flags = RATE_IN_36XX | DEFAULT_RATE },
1351         { .div = 0 },
1352 };
1353
1354 static const struct clksel_rate sgx_corex2_rates[] = {
1355         { .div = 3, .val = 6, .flags = RATE_IN_36XX | DEFAULT_RATE },
1356         { .div = 5, .val = 7, .flags = RATE_IN_36XX },
1357         { .div = 0 },
1358 };
1359
1360 static const struct clksel_rate sgx_96m_rates[] = {
1361         { .div = 1,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1362         { .div = 0 },
1363 };
1364
1365 static const struct clksel sgx_clksel[] = {
1366         { .parent = &core_ck,    .rates = sgx_core_rates },
1367         { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1368         { .parent = &omap_192m_alwon_fck, .rates = sgx_192m_rates },
1369         { .parent = &corex2_fck, .rates = sgx_corex2_rates },
1370         { .parent = NULL }
1371 };
1372
1373 static struct clk sgx_fck = {
1374         .name           = "sgx_fck",
1375         .ops            = &clkops_omap2_dflt_wait,
1376         .init           = &omap2_init_clksel_parent,
1377         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1378         .enable_bit     = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT,
1379         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1380         .clksel_mask    = OMAP3430ES2_CLKSEL_SGX_MASK,
1381         .clksel         = sgx_clksel,
1382         .clkdm_name     = "sgx_clkdm",
1383         .recalc         = &omap2_clksel_recalc,
1384         .set_rate       = &omap2_clksel_set_rate,
1385         .round_rate     = &omap2_clksel_round_rate
1386 };
1387
1388 static struct clk sgx_ick = {
1389         .name           = "sgx_ick",
1390         .ops            = &clkops_omap2_dflt_wait,
1391         .parent         = &l3_ick,
1392         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1393         .enable_bit     = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT,
1394         .clkdm_name     = "sgx_clkdm",
1395         .recalc         = &followparent_recalc,
1396 };
1397
1398 /* CORE power domain */
1399
1400 static struct clk d2d_26m_fck = {
1401         .name           = "d2d_26m_fck",
1402         .ops            = &clkops_omap2_dflt_wait,
1403         .parent         = &sys_ck,
1404         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1405         .enable_bit     = OMAP3430ES1_EN_D2D_SHIFT,
1406         .clkdm_name     = "d2d_clkdm",
1407         .recalc         = &followparent_recalc,
1408 };
1409
1410 static struct clk modem_fck = {
1411         .name           = "modem_fck",
1412         .ops            = &clkops_omap2_dflt_wait,
1413         .parent         = &sys_ck,
1414         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1415         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
1416         .clkdm_name     = "d2d_clkdm",
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 static struct clk sad2d_ick = {
1421         .name           = "sad2d_ick",
1422         .ops            = &clkops_omap2_dflt_wait,
1423         .parent         = &l3_ick,
1424         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1425         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
1426         .clkdm_name     = "d2d_clkdm",
1427         .recalc         = &followparent_recalc,
1428 };
1429
1430 static struct clk mad2d_ick = {
1431         .name           = "mad2d_ick",
1432         .ops            = &clkops_omap2_dflt_wait,
1433         .parent         = &l3_ick,
1434         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1435         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
1436         .clkdm_name     = "d2d_clkdm",
1437         .recalc         = &followparent_recalc,
1438 };
1439
1440 static const struct clksel omap343x_gpt_clksel[] = {
1441         { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1442         { .parent = &sys_ck,       .rates = gpt_sys_rates },
1443         { .parent = NULL}
1444 };
1445
1446 static struct clk gpt10_fck = {
1447         .name           = "gpt10_fck",
1448         .ops            = &clkops_omap2_dflt_wait,
1449         .parent         = &sys_ck,
1450         .init           = &omap2_init_clksel_parent,
1451         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1452         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
1453         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1454         .clksel_mask    = OMAP3430_CLKSEL_GPT10_MASK,
1455         .clksel         = omap343x_gpt_clksel,
1456         .clkdm_name     = "core_l4_clkdm",
1457         .recalc         = &omap2_clksel_recalc,
1458 };
1459
1460 static struct clk gpt11_fck = {
1461         .name           = "gpt11_fck",
1462         .ops            = &clkops_omap2_dflt_wait,
1463         .parent         = &sys_ck,
1464         .init           = &omap2_init_clksel_parent,
1465         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1466         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
1467         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1468         .clksel_mask    = OMAP3430_CLKSEL_GPT11_MASK,
1469         .clksel         = omap343x_gpt_clksel,
1470         .clkdm_name     = "core_l4_clkdm",
1471         .recalc         = &omap2_clksel_recalc,
1472 };
1473
1474 static struct clk cpefuse_fck = {
1475         .name           = "cpefuse_fck",
1476         .ops            = &clkops_omap2_dflt,
1477         .parent         = &sys_ck,
1478         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1479         .enable_bit     = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1480         .recalc         = &followparent_recalc,
1481 };
1482
1483 static struct clk ts_fck = {
1484         .name           = "ts_fck",
1485         .ops            = &clkops_omap2_dflt,
1486         .parent         = &omap_32k_fck,
1487         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1488         .enable_bit     = OMAP3430ES2_EN_TS_SHIFT,
1489         .recalc         = &followparent_recalc,
1490 };
1491
1492 static struct clk usbtll_fck = {
1493         .name           = "usbtll_fck",
1494         .ops            = &clkops_omap2_dflt,
1495         .parent         = &dpll5_m2_ck,
1496         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1497         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1498         .recalc         = &followparent_recalc,
1499 };
1500
1501 /* CORE 96M FCLK-derived clocks */
1502
1503 static struct clk core_96m_fck = {
1504         .name           = "core_96m_fck",
1505         .ops            = &clkops_null,
1506         .parent         = &omap_96m_fck,
1507         .clkdm_name     = "core_l4_clkdm",
1508         .recalc         = &followparent_recalc,
1509 };
1510
1511 static struct clk mmchs3_fck = {
1512         .name           = "mmchs3_fck",
1513         .ops            = &clkops_omap2_dflt_wait,
1514         .parent         = &core_96m_fck,
1515         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1516         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1517         .clkdm_name     = "core_l4_clkdm",
1518         .recalc         = &followparent_recalc,
1519 };
1520
1521 static struct clk mmchs2_fck = {
1522         .name           = "mmchs2_fck",
1523         .ops            = &clkops_omap2_dflt_wait,
1524         .parent         = &core_96m_fck,
1525         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1526         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1527         .clkdm_name     = "core_l4_clkdm",
1528         .recalc         = &followparent_recalc,
1529 };
1530
1531 static struct clk mspro_fck = {
1532         .name           = "mspro_fck",
1533         .ops            = &clkops_omap2_dflt_wait,
1534         .parent         = &core_96m_fck,
1535         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1536         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1537         .clkdm_name     = "core_l4_clkdm",
1538         .recalc         = &followparent_recalc,
1539 };
1540
1541 static struct clk mmchs1_fck = {
1542         .name           = "mmchs1_fck",
1543         .ops            = &clkops_omap2_dflt_wait,
1544         .parent         = &core_96m_fck,
1545         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1546         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1547         .clkdm_name     = "core_l4_clkdm",
1548         .recalc         = &followparent_recalc,
1549 };
1550
1551 static struct clk i2c3_fck = {
1552         .name           = "i2c3_fck",
1553         .ops            = &clkops_omap2_dflt_wait,
1554         .parent         = &core_96m_fck,
1555         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1556         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
1557         .clkdm_name     = "core_l4_clkdm",
1558         .recalc         = &followparent_recalc,
1559 };
1560
1561 static struct clk i2c2_fck = {
1562         .name           = "i2c2_fck",
1563         .ops            = &clkops_omap2_dflt_wait,
1564         .parent         = &core_96m_fck,
1565         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1566         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
1567         .clkdm_name     = "core_l4_clkdm",
1568         .recalc         = &followparent_recalc,
1569 };
1570
1571 static struct clk i2c1_fck = {
1572         .name           = "i2c1_fck",
1573         .ops            = &clkops_omap2_dflt_wait,
1574         .parent         = &core_96m_fck,
1575         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1576         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
1577         .clkdm_name     = "core_l4_clkdm",
1578         .recalc         = &followparent_recalc,
1579 };
1580
1581 /*
1582  * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1583  * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1584  */
1585 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1586         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1587         { .div = 0 }
1588 };
1589
1590 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1591         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1592         { .div = 0 }
1593 };
1594
1595 static const struct clksel mcbsp_15_clksel[] = {
1596         { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1597         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
1598         { .parent = NULL }
1599 };
1600
1601 static struct clk mcbsp5_fck = {
1602         .name           = "mcbsp5_fck",
1603         .ops            = &clkops_omap2_dflt_wait,
1604         .init           = &omap2_init_clksel_parent,
1605         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1606         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
1607         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1608         .clksel_mask    = OMAP2_MCBSP5_CLKS_MASK,
1609         .clksel         = mcbsp_15_clksel,
1610         .clkdm_name     = "core_l4_clkdm",
1611         .recalc         = &omap2_clksel_recalc,
1612 };
1613
1614 static struct clk mcbsp1_fck = {
1615         .name           = "mcbsp1_fck",
1616         .ops            = &clkops_omap2_dflt_wait,
1617         .init           = &omap2_init_clksel_parent,
1618         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1619         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
1620         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1621         .clksel_mask    = OMAP2_MCBSP1_CLKS_MASK,
1622         .clksel         = mcbsp_15_clksel,
1623         .clkdm_name     = "core_l4_clkdm",
1624         .recalc         = &omap2_clksel_recalc,
1625 };
1626
1627 /* CORE_48M_FCK-derived clocks */
1628
1629 static struct clk core_48m_fck = {
1630         .name           = "core_48m_fck",
1631         .ops            = &clkops_null,
1632         .parent         = &omap_48m_fck,
1633         .clkdm_name     = "core_l4_clkdm",
1634         .recalc         = &followparent_recalc,
1635 };
1636
1637 static struct clk mcspi4_fck = {
1638         .name           = "mcspi4_fck",
1639         .ops            = &clkops_omap2_dflt_wait,
1640         .parent         = &core_48m_fck,
1641         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1642         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1643         .recalc         = &followparent_recalc,
1644 };
1645
1646 static struct clk mcspi3_fck = {
1647         .name           = "mcspi3_fck",
1648         .ops            = &clkops_omap2_dflt_wait,
1649         .parent         = &core_48m_fck,
1650         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1651         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1652         .recalc         = &followparent_recalc,
1653 };
1654
1655 static struct clk mcspi2_fck = {
1656         .name           = "mcspi2_fck",
1657         .ops            = &clkops_omap2_dflt_wait,
1658         .parent         = &core_48m_fck,
1659         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1660         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1661         .recalc         = &followparent_recalc,
1662 };
1663
1664 static struct clk mcspi1_fck = {
1665         .name           = "mcspi1_fck",
1666         .ops            = &clkops_omap2_dflt_wait,
1667         .parent         = &core_48m_fck,
1668         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1669         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
1670         .recalc         = &followparent_recalc,
1671 };
1672
1673 static struct clk uart2_fck = {
1674         .name           = "uart2_fck",
1675         .ops            = &clkops_omap2_dflt_wait,
1676         .parent         = &core_48m_fck,
1677         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1678         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
1679         .clkdm_name     = "core_l4_clkdm",
1680         .recalc         = &followparent_recalc,
1681 };
1682
1683 static struct clk uart1_fck = {
1684         .name           = "uart1_fck",
1685         .ops            = &clkops_omap2_dflt_wait,
1686         .parent         = &core_48m_fck,
1687         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1688         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
1689         .clkdm_name     = "core_l4_clkdm",
1690         .recalc         = &followparent_recalc,
1691 };
1692
1693 static struct clk fshostusb_fck = {
1694         .name           = "fshostusb_fck",
1695         .ops            = &clkops_omap2_dflt_wait,
1696         .parent         = &core_48m_fck,
1697         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1698         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1699         .recalc         = &followparent_recalc,
1700 };
1701
1702 /* CORE_12M_FCK based clocks */
1703
1704 static struct clk core_12m_fck = {
1705         .name           = "core_12m_fck",
1706         .ops            = &clkops_null,
1707         .parent         = &omap_12m_fck,
1708         .clkdm_name     = "core_l4_clkdm",
1709         .recalc         = &followparent_recalc,
1710 };
1711
1712 static struct clk hdq_fck = {
1713         .name           = "hdq_fck",
1714         .ops            = &clkops_omap2_dflt_wait,
1715         .parent         = &core_12m_fck,
1716         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1717         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1718         .recalc         = &followparent_recalc,
1719 };
1720
1721 /* DPLL3-derived clock */
1722
1723 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1724         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1725         { .div = 2, .val = 2, .flags = RATE_IN_343X },
1726         { .div = 3, .val = 3, .flags = RATE_IN_343X },
1727         { .div = 4, .val = 4, .flags = RATE_IN_343X },
1728         { .div = 6, .val = 6, .flags = RATE_IN_343X },
1729         { .div = 8, .val = 8, .flags = RATE_IN_343X },
1730         { .div = 0 }
1731 };
1732
1733 static const struct clksel ssi_ssr_clksel[] = {
1734         { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1735         { .parent = NULL }
1736 };
1737
1738 static struct clk ssi_ssr_fck_3430es1 = {
1739         .name           = "ssi_ssr_fck",
1740         .ops            = &clkops_omap2_dflt,
1741         .init           = &omap2_init_clksel_parent,
1742         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1743         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1744         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1745         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1746         .clksel         = ssi_ssr_clksel,
1747         .clkdm_name     = "core_l4_clkdm",
1748         .recalc         = &omap2_clksel_recalc,
1749 };
1750
1751 static struct clk ssi_ssr_fck_3430es2 = {
1752         .name           = "ssi_ssr_fck",
1753         .ops            = &clkops_omap3430es2_ssi_wait,
1754         .init           = &omap2_init_clksel_parent,
1755         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1756         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
1757         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1758         .clksel_mask    = OMAP3430_CLKSEL_SSI_MASK,
1759         .clksel         = ssi_ssr_clksel,
1760         .clkdm_name     = "core_l4_clkdm",
1761         .recalc         = &omap2_clksel_recalc,
1762 };
1763
1764 static struct clk ssi_sst_fck_3430es1 = {
1765         .name           = "ssi_sst_fck",
1766         .ops            = &clkops_null,
1767         .parent         = &ssi_ssr_fck_3430es1,
1768         .fixed_div      = 2,
1769         .recalc         = &omap_fixed_divisor_recalc,
1770 };
1771
1772 static struct clk ssi_sst_fck_3430es2 = {
1773         .name           = "ssi_sst_fck",
1774         .ops            = &clkops_null,
1775         .parent         = &ssi_ssr_fck_3430es2,
1776         .fixed_div      = 2,
1777         .recalc         = &omap_fixed_divisor_recalc,
1778 };
1779
1780
1781
1782 /* CORE_L3_ICK based clocks */
1783
1784 /*
1785  * XXX must add clk_enable/clk_disable for these if standard code won't
1786  * handle it
1787  */
1788 static struct clk core_l3_ick = {
1789         .name           = "core_l3_ick",
1790         .ops            = &clkops_null,
1791         .parent         = &l3_ick,
1792         .clkdm_name     = "core_l3_clkdm",
1793         .recalc         = &followparent_recalc,
1794 };
1795
1796 static struct clk hsotgusb_ick_3430es1 = {
1797         .name           = "hsotgusb_ick",
1798         .ops            = &clkops_omap2_dflt,
1799         .parent         = &core_l3_ick,
1800         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1801         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1802         .clkdm_name     = "core_l3_clkdm",
1803         .recalc         = &followparent_recalc,
1804 };
1805
1806 static struct clk hsotgusb_ick_3430es2 = {
1807         .name           = "hsotgusb_ick",
1808         .ops            = &clkops_omap3430es2_hsotgusb_wait,
1809         .parent         = &core_l3_ick,
1810         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1811         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
1812         .clkdm_name     = "core_l3_clkdm",
1813         .recalc         = &followparent_recalc,
1814 };
1815
1816 static struct clk sdrc_ick = {
1817         .name           = "sdrc_ick",
1818         .ops            = &clkops_omap2_dflt_wait,
1819         .parent         = &core_l3_ick,
1820         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1821         .enable_bit     = OMAP3430_EN_SDRC_SHIFT,
1822         .flags          = ENABLE_ON_INIT,
1823         .clkdm_name     = "core_l3_clkdm",
1824         .recalc         = &followparent_recalc,
1825 };
1826
1827 static struct clk gpmc_fck = {
1828         .name           = "gpmc_fck",
1829         .ops            = &clkops_null,
1830         .parent         = &core_l3_ick,
1831         .flags          = ENABLE_ON_INIT, /* huh? */
1832         .clkdm_name     = "core_l3_clkdm",
1833         .recalc         = &followparent_recalc,
1834 };
1835
1836 /* SECURITY_L3_ICK based clocks */
1837
1838 static struct clk security_l3_ick = {
1839         .name           = "security_l3_ick",
1840         .ops            = &clkops_null,
1841         .parent         = &l3_ick,
1842         .recalc         = &followparent_recalc,
1843 };
1844
1845 static struct clk pka_ick = {
1846         .name           = "pka_ick",
1847         .ops            = &clkops_omap2_dflt_wait,
1848         .parent         = &security_l3_ick,
1849         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1850         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
1851         .recalc         = &followparent_recalc,
1852 };
1853
1854 /* CORE_L4_ICK based clocks */
1855
1856 static struct clk core_l4_ick = {
1857         .name           = "core_l4_ick",
1858         .ops            = &clkops_null,
1859         .parent         = &l4_ick,
1860         .clkdm_name     = "core_l4_clkdm",
1861         .recalc         = &followparent_recalc,
1862 };
1863
1864 static struct clk usbtll_ick = {
1865         .name           = "usbtll_ick",
1866         .ops            = &clkops_omap2_dflt_wait,
1867         .parent         = &core_l4_ick,
1868         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1869         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
1870         .clkdm_name     = "core_l4_clkdm",
1871         .recalc         = &followparent_recalc,
1872 };
1873
1874 static struct clk mmchs3_ick = {
1875         .name           = "mmchs3_ick",
1876         .ops            = &clkops_omap2_dflt_wait,
1877         .parent         = &core_l4_ick,
1878         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1879         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
1880         .clkdm_name     = "core_l4_clkdm",
1881         .recalc         = &followparent_recalc,
1882 };
1883
1884 /* Intersystem Communication Registers - chassis mode only */
1885 static struct clk icr_ick = {
1886         .name           = "icr_ick",
1887         .ops            = &clkops_omap2_dflt_wait,
1888         .parent         = &core_l4_ick,
1889         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1890         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
1891         .clkdm_name     = "core_l4_clkdm",
1892         .recalc         = &followparent_recalc,
1893 };
1894
1895 static struct clk aes2_ick = {
1896         .name           = "aes2_ick",
1897         .ops            = &clkops_omap2_dflt_wait,
1898         .parent         = &core_l4_ick,
1899         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1900         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
1901         .clkdm_name     = "core_l4_clkdm",
1902         .recalc         = &followparent_recalc,
1903 };
1904
1905 static struct clk sha12_ick = {
1906         .name           = "sha12_ick",
1907         .ops            = &clkops_omap2_dflt_wait,
1908         .parent         = &core_l4_ick,
1909         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1910         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
1911         .clkdm_name     = "core_l4_clkdm",
1912         .recalc         = &followparent_recalc,
1913 };
1914
1915 static struct clk des2_ick = {
1916         .name           = "des2_ick",
1917         .ops            = &clkops_omap2_dflt_wait,
1918         .parent         = &core_l4_ick,
1919         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1920         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
1921         .clkdm_name     = "core_l4_clkdm",
1922         .recalc         = &followparent_recalc,
1923 };
1924
1925 static struct clk mmchs2_ick = {
1926         .name           = "mmchs2_ick",
1927         .ops            = &clkops_omap2_dflt_wait,
1928         .parent         = &core_l4_ick,
1929         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1930         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
1931         .clkdm_name     = "core_l4_clkdm",
1932         .recalc         = &followparent_recalc,
1933 };
1934
1935 static struct clk mmchs1_ick = {
1936         .name           = "mmchs1_ick",
1937         .ops            = &clkops_omap2_dflt_wait,
1938         .parent         = &core_l4_ick,
1939         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1940         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
1941         .clkdm_name     = "core_l4_clkdm",
1942         .recalc         = &followparent_recalc,
1943 };
1944
1945 static struct clk mspro_ick = {
1946         .name           = "mspro_ick",
1947         .ops            = &clkops_omap2_dflt_wait,
1948         .parent         = &core_l4_ick,
1949         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1950         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
1951         .clkdm_name     = "core_l4_clkdm",
1952         .recalc         = &followparent_recalc,
1953 };
1954
1955 static struct clk hdq_ick = {
1956         .name           = "hdq_ick",
1957         .ops            = &clkops_omap2_dflt_wait,
1958         .parent         = &core_l4_ick,
1959         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1960         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
1961         .clkdm_name     = "core_l4_clkdm",
1962         .recalc         = &followparent_recalc,
1963 };
1964
1965 static struct clk mcspi4_ick = {
1966         .name           = "mcspi4_ick",
1967         .ops            = &clkops_omap2_dflt_wait,
1968         .parent         = &core_l4_ick,
1969         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1970         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
1971         .clkdm_name     = "core_l4_clkdm",
1972         .recalc         = &followparent_recalc,
1973 };
1974
1975 static struct clk mcspi3_ick = {
1976         .name           = "mcspi3_ick",
1977         .ops            = &clkops_omap2_dflt_wait,
1978         .parent         = &core_l4_ick,
1979         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1980         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
1981         .clkdm_name     = "core_l4_clkdm",
1982         .recalc         = &followparent_recalc,
1983 };
1984
1985 static struct clk mcspi2_ick = {
1986         .name           = "mcspi2_ick",
1987         .ops            = &clkops_omap2_dflt_wait,
1988         .parent         = &core_l4_ick,
1989         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1990         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
1991         .clkdm_name     = "core_l4_clkdm",
1992         .recalc         = &followparent_recalc,
1993 };
1994
1995 static struct clk mcspi1_ick = {
1996         .name           = "mcspi1_ick",
1997         .ops            = &clkops_omap2_dflt_wait,
1998         .parent         = &core_l4_ick,
1999         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2000         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
2001         .clkdm_name     = "core_l4_clkdm",
2002         .recalc         = &followparent_recalc,
2003 };
2004
2005 static struct clk i2c3_ick = {
2006         .name           = "i2c3_ick",
2007         .ops            = &clkops_omap2_dflt_wait,
2008         .parent         = &core_l4_ick,
2009         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2010         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
2011         .clkdm_name     = "core_l4_clkdm",
2012         .recalc         = &followparent_recalc,
2013 };
2014
2015 static struct clk i2c2_ick = {
2016         .name           = "i2c2_ick",
2017         .ops            = &clkops_omap2_dflt_wait,
2018         .parent         = &core_l4_ick,
2019         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2020         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
2021         .clkdm_name     = "core_l4_clkdm",
2022         .recalc         = &followparent_recalc,
2023 };
2024
2025 static struct clk i2c1_ick = {
2026         .name           = "i2c1_ick",
2027         .ops            = &clkops_omap2_dflt_wait,
2028         .parent         = &core_l4_ick,
2029         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2030         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
2031         .clkdm_name     = "core_l4_clkdm",
2032         .recalc         = &followparent_recalc,
2033 };
2034
2035 static struct clk uart2_ick = {
2036         .name           = "uart2_ick",
2037         .ops            = &clkops_omap2_dflt_wait,
2038         .parent         = &core_l4_ick,
2039         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2040         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
2041         .clkdm_name     = "core_l4_clkdm",
2042         .recalc         = &followparent_recalc,
2043 };
2044
2045 static struct clk uart1_ick = {
2046         .name           = "uart1_ick",
2047         .ops            = &clkops_omap2_dflt_wait,
2048         .parent         = &core_l4_ick,
2049         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2050         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
2051         .clkdm_name     = "core_l4_clkdm",
2052         .recalc         = &followparent_recalc,
2053 };
2054
2055 static struct clk gpt11_ick = {
2056         .name           = "gpt11_ick",
2057         .ops            = &clkops_omap2_dflt_wait,
2058         .parent         = &core_l4_ick,
2059         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2060         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
2061         .clkdm_name     = "core_l4_clkdm",
2062         .recalc         = &followparent_recalc,
2063 };
2064
2065 static struct clk gpt10_ick = {
2066         .name           = "gpt10_ick",
2067         .ops            = &clkops_omap2_dflt_wait,
2068         .parent         = &core_l4_ick,
2069         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2070         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
2071         .clkdm_name     = "core_l4_clkdm",
2072         .recalc         = &followparent_recalc,
2073 };
2074
2075 static struct clk mcbsp5_ick = {
2076         .name           = "mcbsp5_ick",
2077         .ops            = &clkops_omap2_dflt_wait,
2078         .parent         = &core_l4_ick,
2079         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2080         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
2081         .clkdm_name     = "core_l4_clkdm",
2082         .recalc         = &followparent_recalc,
2083 };
2084
2085 static struct clk mcbsp1_ick = {
2086         .name           = "mcbsp1_ick",
2087         .ops            = &clkops_omap2_dflt_wait,
2088         .parent         = &core_l4_ick,
2089         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2090         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
2091         .clkdm_name     = "core_l4_clkdm",
2092         .recalc         = &followparent_recalc,
2093 };
2094
2095 static struct clk fac_ick = {
2096         .name           = "fac_ick",
2097         .ops            = &clkops_omap2_dflt_wait,
2098         .parent         = &core_l4_ick,
2099         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2100         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
2101         .clkdm_name     = "core_l4_clkdm",
2102         .recalc         = &followparent_recalc,
2103 };
2104
2105 static struct clk mailboxes_ick = {
2106         .name           = "mailboxes_ick",
2107         .ops            = &clkops_omap2_dflt_wait,
2108         .parent         = &core_l4_ick,
2109         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2110         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
2111         .clkdm_name     = "core_l4_clkdm",
2112         .recalc         = &followparent_recalc,
2113 };
2114
2115 static struct clk omapctrl_ick = {
2116         .name           = "omapctrl_ick",
2117         .ops            = &clkops_omap2_dflt_wait,
2118         .parent         = &core_l4_ick,
2119         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2120         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
2121         .flags          = ENABLE_ON_INIT,
2122         .recalc         = &followparent_recalc,
2123 };
2124
2125 /* SSI_L4_ICK based clocks */
2126
2127 static struct clk ssi_l4_ick = {
2128         .name           = "ssi_l4_ick",
2129         .ops            = &clkops_null,
2130         .parent         = &l4_ick,
2131         .clkdm_name     = "core_l4_clkdm",
2132         .recalc         = &followparent_recalc,
2133 };
2134
2135 static struct clk ssi_ick_3430es1 = {
2136         .name           = "ssi_ick",
2137         .ops            = &clkops_omap2_dflt,
2138         .parent         = &ssi_l4_ick,
2139         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2140         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2141         .clkdm_name     = "core_l4_clkdm",
2142         .recalc         = &followparent_recalc,
2143 };
2144
2145 static struct clk ssi_ick_3430es2 = {
2146         .name           = "ssi_ick",
2147         .ops            = &clkops_omap3430es2_ssi_wait,
2148         .parent         = &ssi_l4_ick,
2149         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2150         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
2151         .clkdm_name     = "core_l4_clkdm",
2152         .recalc         = &followparent_recalc,
2153 };
2154
2155 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
2156  * but l4_ick makes more sense to me */
2157
2158 static const struct clksel usb_l4_clksel[] = {
2159         { .parent = &l4_ick, .rates = div2_rates },
2160         { .parent = NULL },
2161 };
2162
2163 static struct clk usb_l4_ick = {
2164         .name           = "usb_l4_ick",
2165         .ops            = &clkops_omap2_dflt_wait,
2166         .parent         = &l4_ick,
2167         .init           = &omap2_init_clksel_parent,
2168         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
2169         .enable_bit     = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
2170         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
2171         .clksel_mask    = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
2172         .clksel         = usb_l4_clksel,
2173         .recalc         = &omap2_clksel_recalc,
2174 };
2175
2176 /* SECURITY_L4_ICK2 based clocks */
2177
2178 static struct clk security_l4_ick2 = {
2179         .name           = "security_l4_ick2",
2180         .ops            = &clkops_null,
2181         .parent         = &l4_ick,
2182         .recalc         = &followparent_recalc,
2183 };
2184
2185 static struct clk aes1_ick = {
2186         .name           = "aes1_ick",
2187         .ops            = &clkops_omap2_dflt_wait,
2188         .parent         = &security_l4_ick2,
2189         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2190         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
2191         .recalc         = &followparent_recalc,
2192 };
2193
2194 static struct clk rng_ick = {
2195         .name           = "rng_ick",
2196         .ops            = &clkops_omap2_dflt_wait,
2197         .parent         = &security_l4_ick2,
2198         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2199         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
2200         .recalc         = &followparent_recalc,
2201 };
2202
2203 static struct clk sha11_ick = {
2204         .name           = "sha11_ick",
2205         .ops            = &clkops_omap2_dflt_wait,
2206         .parent         = &security_l4_ick2,
2207         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2208         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
2209         .recalc         = &followparent_recalc,
2210 };
2211
2212 static struct clk des1_ick = {
2213         .name           = "des1_ick",
2214         .ops            = &clkops_omap2_dflt_wait,
2215         .parent         = &security_l4_ick2,
2216         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
2217         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
2218         .recalc         = &followparent_recalc,
2219 };
2220
2221 /* DSS */
2222 static struct clk dss1_alwon_fck_3430es1 = {
2223         .name           = "dss1_alwon_fck",
2224         .ops            = &clkops_omap2_dflt,
2225         .parent         = &dpll4_m4x2_ck,
2226         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2227         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2228         .clkdm_name     = "dss_clkdm",
2229         .recalc         = &followparent_recalc,
2230 };
2231
2232 static struct clk dss1_alwon_fck_3430es2 = {
2233         .name           = "dss1_alwon_fck",
2234         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2235         .parent         = &dpll4_m4x2_ck,
2236         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2237         .enable_bit     = OMAP3430_EN_DSS1_SHIFT,
2238         .clkdm_name     = "dss_clkdm",
2239         .recalc         = &followparent_recalc,
2240 };
2241
2242 static struct clk dss_tv_fck = {
2243         .name           = "dss_tv_fck",
2244         .ops            = &clkops_omap2_dflt,
2245         .parent         = &omap_54m_fck,
2246         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2247         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2248         .clkdm_name     = "dss_clkdm",
2249         .recalc         = &followparent_recalc,
2250 };
2251
2252 static struct clk dss_96m_fck = {
2253         .name           = "dss_96m_fck",
2254         .ops            = &clkops_omap2_dflt,
2255         .parent         = &omap_96m_fck,
2256         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2257         .enable_bit     = OMAP3430_EN_TV_SHIFT,
2258         .clkdm_name     = "dss_clkdm",
2259         .recalc         = &followparent_recalc,
2260 };
2261
2262 static struct clk dss2_alwon_fck = {
2263         .name           = "dss2_alwon_fck",
2264         .ops            = &clkops_omap2_dflt,
2265         .parent         = &sys_ck,
2266         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2267         .enable_bit     = OMAP3430_EN_DSS2_SHIFT,
2268         .clkdm_name     = "dss_clkdm",
2269         .recalc         = &followparent_recalc,
2270 };
2271
2272 static struct clk dss_ick_3430es1 = {
2273         /* Handles both L3 and L4 clocks */
2274         .name           = "dss_ick",
2275         .ops            = &clkops_omap2_dflt,
2276         .parent         = &l4_ick,
2277         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2278         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2279         .clkdm_name     = "dss_clkdm",
2280         .recalc         = &followparent_recalc,
2281 };
2282
2283 static struct clk dss_ick_3430es2 = {
2284         /* Handles both L3 and L4 clocks */
2285         .name           = "dss_ick",
2286         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2287         .parent         = &l4_ick,
2288         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2289         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2290         .clkdm_name     = "dss_clkdm",
2291         .recalc         = &followparent_recalc,
2292 };
2293
2294 /* CAM */
2295
2296 static struct clk cam_mclk = {
2297         .name           = "cam_mclk",
2298         .ops            = &clkops_omap2_dflt,
2299         .parent         = &dpll4_m5x2_ck,
2300         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2301         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2302         .clkdm_name     = "cam_clkdm",
2303         .recalc         = &followparent_recalc,
2304 };
2305
2306 static struct clk cam_ick = {
2307         /* Handles both L3 and L4 clocks */
2308         .name           = "cam_ick",
2309         .ops            = &clkops_omap2_dflt,
2310         .parent         = &l4_ick,
2311         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2312         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
2313         .clkdm_name     = "cam_clkdm",
2314         .recalc         = &followparent_recalc,
2315 };
2316
2317 static struct clk csi2_96m_fck = {
2318         .name           = "csi2_96m_fck",
2319         .ops            = &clkops_omap2_dflt,
2320         .parent         = &core_96m_fck,
2321         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2322         .enable_bit     = OMAP3430_EN_CSI2_SHIFT,
2323         .clkdm_name     = "cam_clkdm",
2324         .recalc         = &followparent_recalc,
2325 };
2326
2327 /* USBHOST - 3430ES2 only */
2328
2329 static struct clk usbhost_120m_fck = {
2330         .name           = "usbhost_120m_fck",
2331         .ops            = &clkops_omap2_dflt,
2332         .parent         = &dpll5_m2_ck,
2333         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2334         .enable_bit     = OMAP3430ES2_EN_USBHOST2_SHIFT,
2335         .clkdm_name     = "usbhost_clkdm",
2336         .recalc         = &followparent_recalc,
2337 };
2338
2339 static struct clk usbhost_48m_fck = {
2340         .name           = "usbhost_48m_fck",
2341         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2342         .parent         = &omap_48m_fck,
2343         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2344         .enable_bit     = OMAP3430ES2_EN_USBHOST1_SHIFT,
2345         .clkdm_name     = "usbhost_clkdm",
2346         .recalc         = &followparent_recalc,
2347 };
2348
2349 static struct clk usbhost_ick = {
2350         /* Handles both L3 and L4 clocks */
2351         .name           = "usbhost_ick",
2352         .ops            = &clkops_omap3430es2_dss_usbhost_wait,
2353         .parent         = &l4_ick,
2354         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2355         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
2356         .clkdm_name     = "usbhost_clkdm",
2357         .recalc         = &followparent_recalc,
2358 };
2359
2360 /* WKUP */
2361
2362 static const struct clksel_rate usim_96m_rates[] = {
2363         { .div = 2,  .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2364         { .div = 4,  .val = 4, .flags = RATE_IN_343X },
2365         { .div = 8,  .val = 5, .flags = RATE_IN_343X },
2366         { .div = 10, .val = 6, .flags = RATE_IN_343X },
2367         { .div = 0 },
2368 };
2369
2370 static const struct clksel_rate usim_120m_rates[] = {
2371         { .div = 4,  .val = 7,  .flags = RATE_IN_343X | DEFAULT_RATE },
2372         { .div = 8,  .val = 8,  .flags = RATE_IN_343X },
2373         { .div = 16, .val = 9,  .flags = RATE_IN_343X },
2374         { .div = 20, .val = 10, .flags = RATE_IN_343X },
2375         { .div = 0 },
2376 };
2377
2378 static const struct clksel usim_clksel[] = {
2379         { .parent = &omap_96m_fck,      .rates = usim_96m_rates },
2380         { .parent = &dpll5_m2_ck,       .rates = usim_120m_rates },
2381         { .parent = &sys_ck,            .rates = div2_rates },
2382         { .parent = NULL },
2383 };
2384
2385 /* 3430ES2 only */
2386 static struct clk usim_fck = {
2387         .name           = "usim_fck",
2388         .ops            = &clkops_omap2_dflt_wait,
2389         .init           = &omap2_init_clksel_parent,
2390         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2391         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2392         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2393         .clksel_mask    = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2394         .clksel         = usim_clksel,
2395         .recalc         = &omap2_clksel_recalc,
2396 };
2397
2398 /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */
2399 static struct clk gpt1_fck = {
2400         .name           = "gpt1_fck",
2401         .ops            = &clkops_omap2_dflt_wait,
2402         .init           = &omap2_init_clksel_parent,
2403         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2404         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2405         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2406         .clksel_mask    = OMAP3430_CLKSEL_GPT1_MASK,
2407         .clksel         = omap343x_gpt_clksel,
2408         .clkdm_name     = "wkup_clkdm",
2409         .recalc         = &omap2_clksel_recalc,
2410 };
2411
2412 static struct clk wkup_32k_fck = {
2413         .name           = "wkup_32k_fck",
2414         .ops            = &clkops_null,
2415         .parent         = &omap_32k_fck,
2416         .clkdm_name     = "wkup_clkdm",
2417         .recalc         = &followparent_recalc,
2418 };
2419
2420 static struct clk gpio1_dbck = {
2421         .name           = "gpio1_dbck",
2422         .ops            = &clkops_omap2_dflt,
2423         .parent         = &wkup_32k_fck,
2424         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2425         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2426         .clkdm_name     = "wkup_clkdm",
2427         .recalc         = &followparent_recalc,
2428 };
2429
2430 static struct clk wdt2_fck = {
2431         .name           = "wdt2_fck",
2432         .ops            = &clkops_omap2_dflt_wait,
2433         .parent         = &wkup_32k_fck,
2434         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2435         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2436         .clkdm_name     = "wkup_clkdm",
2437         .recalc         = &followparent_recalc,
2438 };
2439
2440 static struct clk wkup_l4_ick = {
2441         .name           = "wkup_l4_ick",
2442         .ops            = &clkops_null,
2443         .parent         = &sys_ck,
2444         .clkdm_name     = "wkup_clkdm",
2445         .recalc         = &followparent_recalc,
2446 };
2447
2448 /* 3430ES2 only */
2449 /* Never specifically named in the TRM, so we have to infer a likely name */
2450 static struct clk usim_ick = {
2451         .name           = "usim_ick",
2452         .ops            = &clkops_omap2_dflt_wait,
2453         .parent         = &wkup_l4_ick,
2454         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2455         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
2456         .clkdm_name     = "wkup_clkdm",
2457         .recalc         = &followparent_recalc,
2458 };
2459
2460 static struct clk wdt2_ick = {
2461         .name           = "wdt2_ick",
2462         .ops            = &clkops_omap2_dflt_wait,
2463         .parent         = &wkup_l4_ick,
2464         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2465         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
2466         .clkdm_name     = "wkup_clkdm",
2467         .recalc         = &followparent_recalc,
2468 };
2469
2470 static struct clk wdt1_ick = {
2471         .name           = "wdt1_ick",
2472         .ops            = &clkops_omap2_dflt_wait,
2473         .parent         = &wkup_l4_ick,
2474         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2475         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
2476         .clkdm_name     = "wkup_clkdm",
2477         .recalc         = &followparent_recalc,
2478 };
2479
2480 static struct clk gpio1_ick = {
2481         .name           = "gpio1_ick",
2482         .ops            = &clkops_omap2_dflt_wait,
2483         .parent         = &wkup_l4_ick,
2484         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2485         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
2486         .clkdm_name     = "wkup_clkdm",
2487         .recalc         = &followparent_recalc,
2488 };
2489
2490 static struct clk omap_32ksync_ick = {
2491         .name           = "omap_32ksync_ick",
2492         .ops            = &clkops_omap2_dflt_wait,
2493         .parent         = &wkup_l4_ick,
2494         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2495         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
2496         .clkdm_name     = "wkup_clkdm",
2497         .recalc         = &followparent_recalc,
2498 };
2499
2500 /* XXX This clock no longer exists in 3430 TRM rev F */
2501 static struct clk gpt12_ick = {
2502         .name           = "gpt12_ick",
2503         .ops            = &clkops_omap2_dflt_wait,
2504         .parent         = &wkup_l4_ick,
2505         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2506         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
2507         .clkdm_name     = "wkup_clkdm",
2508         .recalc         = &followparent_recalc,
2509 };
2510
2511 static struct clk gpt1_ick = {
2512         .name           = "gpt1_ick",
2513         .ops            = &clkops_omap2_dflt_wait,
2514         .parent         = &wkup_l4_ick,
2515         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2516         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
2517         .clkdm_name     = "wkup_clkdm",
2518         .recalc         = &followparent_recalc,
2519 };
2520
2521
2522
2523 /* PER clock domain */
2524
2525 static struct clk per_96m_fck = {
2526         .name           = "per_96m_fck",
2527         .ops            = &clkops_null,
2528         .parent         = &omap_96m_alwon_fck,
2529         .clkdm_name     = "per_clkdm",
2530         .recalc         = &followparent_recalc,
2531 };
2532
2533 static struct clk per_48m_fck = {
2534         .name           = "per_48m_fck",
2535         .ops            = &clkops_null,
2536         .parent         = &omap_48m_fck,
2537         .clkdm_name     = "per_clkdm",
2538         .recalc         = &followparent_recalc,
2539 };
2540
2541 static struct clk uart3_fck = {
2542         .name           = "uart3_fck",
2543         .ops            = &clkops_omap2_dflt_wait,
2544         .parent         = &per_48m_fck,
2545         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2546         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2547         .clkdm_name     = "per_clkdm",
2548         .recalc         = &followparent_recalc,
2549 };
2550
2551 static struct clk gpt2_fck = {
2552         .name           = "gpt2_fck",
2553         .ops            = &clkops_omap2_dflt_wait,
2554         .init           = &omap2_init_clksel_parent,
2555         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2556         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2557         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2558         .clksel_mask    = OMAP3430_CLKSEL_GPT2_MASK,
2559         .clksel         = omap343x_gpt_clksel,
2560         .clkdm_name     = "per_clkdm",
2561         .recalc         = &omap2_clksel_recalc,
2562 };
2563
2564 static struct clk gpt3_fck = {
2565         .name           = "gpt3_fck",
2566         .ops            = &clkops_omap2_dflt_wait,
2567         .init           = &omap2_init_clksel_parent,
2568         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2569         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2570         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2571         .clksel_mask    = OMAP3430_CLKSEL_GPT3_MASK,
2572         .clksel         = omap343x_gpt_clksel,
2573         .clkdm_name     = "per_clkdm",
2574         .recalc         = &omap2_clksel_recalc,
2575 };
2576
2577 static struct clk gpt4_fck = {
2578         .name           = "gpt4_fck",
2579         .ops            = &clkops_omap2_dflt_wait,
2580         .init           = &omap2_init_clksel_parent,
2581         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2582         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2583         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2584         .clksel_mask    = OMAP3430_CLKSEL_GPT4_MASK,
2585         .clksel         = omap343x_gpt_clksel,
2586         .clkdm_name     = "per_clkdm",
2587         .recalc         = &omap2_clksel_recalc,
2588 };
2589
2590 static struct clk gpt5_fck = {
2591         .name           = "gpt5_fck",
2592         .ops            = &clkops_omap2_dflt_wait,
2593         .init           = &omap2_init_clksel_parent,
2594         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2595         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2596         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2597         .clksel_mask    = OMAP3430_CLKSEL_GPT5_MASK,
2598         .clksel         = omap343x_gpt_clksel,
2599         .clkdm_name     = "per_clkdm",
2600         .recalc         = &omap2_clksel_recalc,
2601 };
2602
2603 static struct clk gpt6_fck = {
2604         .name           = "gpt6_fck",
2605         .ops            = &clkops_omap2_dflt_wait,
2606         .init           = &omap2_init_clksel_parent,
2607         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2608         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2609         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2610         .clksel_mask    = OMAP3430_CLKSEL_GPT6_MASK,
2611         .clksel         = omap343x_gpt_clksel,
2612         .clkdm_name     = "per_clkdm",
2613         .recalc         = &omap2_clksel_recalc,
2614 };
2615
2616 static struct clk gpt7_fck = {
2617         .name           = "gpt7_fck",
2618         .ops            = &clkops_omap2_dflt_wait,
2619         .init           = &omap2_init_clksel_parent,
2620         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2621         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2622         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2623         .clksel_mask    = OMAP3430_CLKSEL_GPT7_MASK,
2624         .clksel         = omap343x_gpt_clksel,
2625         .clkdm_name     = "per_clkdm",
2626         .recalc         = &omap2_clksel_recalc,
2627 };
2628
2629 static struct clk gpt8_fck = {
2630         .name           = "gpt8_fck",
2631         .ops            = &clkops_omap2_dflt_wait,
2632         .init           = &omap2_init_clksel_parent,
2633         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2634         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2635         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2636         .clksel_mask    = OMAP3430_CLKSEL_GPT8_MASK,
2637         .clksel         = omap343x_gpt_clksel,
2638         .clkdm_name     = "per_clkdm",
2639         .recalc         = &omap2_clksel_recalc,
2640 };
2641
2642 static struct clk gpt9_fck = {
2643         .name           = "gpt9_fck",
2644         .ops            = &clkops_omap2_dflt_wait,
2645         .init           = &omap2_init_clksel_parent,
2646         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2647         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2648         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2649         .clksel_mask    = OMAP3430_CLKSEL_GPT9_MASK,
2650         .clksel         = omap343x_gpt_clksel,
2651         .clkdm_name     = "per_clkdm",
2652         .recalc         = &omap2_clksel_recalc,
2653 };
2654
2655 static struct clk per_32k_alwon_fck = {
2656         .name           = "per_32k_alwon_fck",
2657         .ops            = &clkops_null,
2658         .parent         = &omap_32k_fck,
2659         .clkdm_name     = "per_clkdm",
2660         .recalc         = &followparent_recalc,
2661 };
2662
2663 static struct clk gpio6_dbck = {
2664         .name           = "gpio6_dbck",
2665         .ops            = &clkops_omap2_dflt,
2666         .parent         = &per_32k_alwon_fck,
2667         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2668         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2669         .clkdm_name     = "per_clkdm",
2670         .recalc         = &followparent_recalc,
2671 };
2672
2673 static struct clk gpio5_dbck = {
2674         .name           = "gpio5_dbck",
2675         .ops            = &clkops_omap2_dflt,
2676         .parent         = &per_32k_alwon_fck,
2677         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2678         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2679         .clkdm_name     = "per_clkdm",
2680         .recalc         = &followparent_recalc,
2681 };
2682
2683 static struct clk gpio4_dbck = {
2684         .name           = "gpio4_dbck",
2685         .ops            = &clkops_omap2_dflt,
2686         .parent         = &per_32k_alwon_fck,
2687         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2688         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2689         .clkdm_name     = "per_clkdm",
2690         .recalc         = &followparent_recalc,
2691 };
2692
2693 static struct clk gpio3_dbck = {
2694         .name           = "gpio3_dbck",
2695         .ops            = &clkops_omap2_dflt,
2696         .parent         = &per_32k_alwon_fck,
2697         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2698         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2699         .clkdm_name     = "per_clkdm",
2700         .recalc         = &followparent_recalc,
2701 };
2702
2703 static struct clk gpio2_dbck = {
2704         .name           = "gpio2_dbck",
2705         .ops            = &clkops_omap2_dflt,
2706         .parent         = &per_32k_alwon_fck,
2707         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2708         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2709         .clkdm_name     = "per_clkdm",
2710         .recalc         = &followparent_recalc,
2711 };
2712
2713 static struct clk wdt3_fck = {
2714         .name           = "wdt3_fck",
2715         .ops            = &clkops_omap2_dflt_wait,
2716         .parent         = &per_32k_alwon_fck,
2717         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2718         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2719         .clkdm_name     = "per_clkdm",
2720         .recalc         = &followparent_recalc,
2721 };
2722
2723 static struct clk per_l4_ick = {
2724         .name           = "per_l4_ick",
2725         .ops            = &clkops_null,
2726         .parent         = &l4_ick,
2727         .clkdm_name     = "per_clkdm",
2728         .recalc         = &followparent_recalc,
2729 };
2730
2731 static struct clk gpio6_ick = {
2732         .name           = "gpio6_ick",
2733         .ops            = &clkops_omap2_dflt_wait,
2734         .parent         = &per_l4_ick,
2735         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2736         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
2737         .clkdm_name     = "per_clkdm",
2738         .recalc         = &followparent_recalc,
2739 };
2740
2741 static struct clk gpio5_ick = {
2742         .name           = "gpio5_ick",
2743         .ops            = &clkops_omap2_dflt_wait,
2744         .parent         = &per_l4_ick,
2745         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2746         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
2747         .clkdm_name     = "per_clkdm",
2748         .recalc         = &followparent_recalc,
2749 };
2750
2751 static struct clk gpio4_ick = {
2752         .name           = "gpio4_ick",
2753         .ops            = &clkops_omap2_dflt_wait,
2754         .parent         = &per_l4_ick,
2755         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2756         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
2757         .clkdm_name     = "per_clkdm",
2758         .recalc         = &followparent_recalc,
2759 };
2760
2761 static struct clk gpio3_ick = {
2762         .name           = "gpio3_ick",
2763         .ops            = &clkops_omap2_dflt_wait,
2764         .parent         = &per_l4_ick,
2765         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2766         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
2767         .clkdm_name     = "per_clkdm",
2768         .recalc         = &followparent_recalc,
2769 };
2770
2771 static struct clk gpio2_ick = {
2772         .name           = "gpio2_ick",
2773         .ops            = &clkops_omap2_dflt_wait,
2774         .parent         = &per_l4_ick,
2775         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2776         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
2777         .clkdm_name     = "per_clkdm",
2778         .recalc         = &followparent_recalc,
2779 };
2780
2781 static struct clk wdt3_ick = {
2782         .name           = "wdt3_ick",
2783         .ops            = &clkops_omap2_dflt_wait,
2784         .parent         = &per_l4_ick,
2785         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2786         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
2787         .clkdm_name     = "per_clkdm",
2788         .recalc         = &followparent_recalc,
2789 };
2790
2791 static struct clk uart3_ick = {
2792         .name           = "uart3_ick",
2793         .ops            = &clkops_omap2_dflt_wait,
2794         .parent         = &per_l4_ick,
2795         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2796         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
2797         .clkdm_name     = "per_clkdm",
2798         .recalc         = &followparent_recalc,
2799 };
2800
2801 static struct clk gpt9_ick = {
2802         .name           = "gpt9_ick",
2803         .ops            = &clkops_omap2_dflt_wait,
2804         .parent         = &per_l4_ick,
2805         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2806         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
2807         .clkdm_name     = "per_clkdm",
2808         .recalc         = &followparent_recalc,
2809 };
2810
2811 static struct clk gpt8_ick = {
2812         .name           = "gpt8_ick",
2813         .ops            = &clkops_omap2_dflt_wait,
2814         .parent         = &per_l4_ick,
2815         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2816         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
2817         .clkdm_name     = "per_clkdm",
2818         .recalc         = &followparent_recalc,
2819 };
2820
2821 static struct clk gpt7_ick = {
2822         .name           = "gpt7_ick",
2823         .ops            = &clkops_omap2_dflt_wait,
2824         .parent         = &per_l4_ick,
2825         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2826         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
2827         .clkdm_name     = "per_clkdm",
2828         .recalc         = &followparent_recalc,
2829 };
2830
2831 static struct clk gpt6_ick = {
2832         .name           = "gpt6_ick",
2833         .ops            = &clkops_omap2_dflt_wait,
2834         .parent         = &per_l4_ick,
2835         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2836         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
2837         .clkdm_name     = "per_clkdm",
2838         .recalc         = &followparent_recalc,
2839 };
2840
2841 static struct clk gpt5_ick = {
2842         .name           = "gpt5_ick",
2843         .ops            = &clkops_omap2_dflt_wait,
2844         .parent         = &per_l4_ick,
2845         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2846         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
2847         .clkdm_name     = "per_clkdm",
2848         .recalc         = &followparent_recalc,
2849 };
2850
2851 static struct clk gpt4_ick = {
2852         .name           = "gpt4_ick",
2853         .ops            = &clkops_omap2_dflt_wait,
2854         .parent         = &per_l4_ick,
2855         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2856         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
2857         .clkdm_name     = "per_clkdm",
2858         .recalc         = &followparent_recalc,
2859 };
2860
2861 static struct clk gpt3_ick = {
2862         .name           = "gpt3_ick",
2863         .ops            = &clkops_omap2_dflt_wait,
2864         .parent         = &per_l4_ick,
2865         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2866         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
2867         .clkdm_name     = "per_clkdm",
2868         .recalc         = &followparent_recalc,
2869 };
2870
2871 static struct clk gpt2_ick = {
2872         .name           = "gpt2_ick",
2873         .ops            = &clkops_omap2_dflt_wait,
2874         .parent         = &per_l4_ick,
2875         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2876         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
2877         .clkdm_name     = "per_clkdm",
2878         .recalc         = &followparent_recalc,
2879 };
2880
2881 static struct clk mcbsp2_ick = {
2882         .name           = "mcbsp2_ick",
2883         .ops            = &clkops_omap2_dflt_wait,
2884         .parent         = &per_l4_ick,
2885         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2886         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2887         .clkdm_name     = "per_clkdm",
2888         .recalc         = &followparent_recalc,
2889 };
2890
2891 static struct clk mcbsp3_ick = {
2892         .name           = "mcbsp3_ick",
2893         .ops            = &clkops_omap2_dflt_wait,
2894         .parent         = &per_l4_ick,
2895         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2896         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2897         .clkdm_name     = "per_clkdm",
2898         .recalc         = &followparent_recalc,
2899 };
2900
2901 static struct clk mcbsp4_ick = {
2902         .name           = "mcbsp4_ick",
2903         .ops            = &clkops_omap2_dflt_wait,
2904         .parent         = &per_l4_ick,
2905         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2906         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2907         .clkdm_name     = "per_clkdm",
2908         .recalc         = &followparent_recalc,
2909 };
2910
2911 static const struct clksel mcbsp_234_clksel[] = {
2912         { .parent = &per_96m_fck,  .rates = common_mcbsp_96m_rates },
2913         { .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
2914         { .parent = NULL }
2915 };
2916
2917 static struct clk mcbsp2_fck = {
2918         .name           = "mcbsp2_fck",
2919         .ops            = &clkops_omap2_dflt_wait,
2920         .init           = &omap2_init_clksel_parent,
2921         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2922         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
2923         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2924         .clksel_mask    = OMAP2_MCBSP2_CLKS_MASK,
2925         .clksel         = mcbsp_234_clksel,
2926         .clkdm_name     = "per_clkdm",
2927         .recalc         = &omap2_clksel_recalc,
2928 };
2929
2930 static struct clk mcbsp3_fck = {
2931         .name           = "mcbsp3_fck",
2932         .ops            = &clkops_omap2_dflt_wait,
2933         .init           = &omap2_init_clksel_parent,
2934         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2935         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
2936         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2937         .clksel_mask    = OMAP2_MCBSP3_CLKS_MASK,
2938         .clksel         = mcbsp_234_clksel,
2939         .clkdm_name     = "per_clkdm",
2940         .recalc         = &omap2_clksel_recalc,
2941 };
2942
2943 static struct clk mcbsp4_fck = {
2944         .name           = "mcbsp4_fck",
2945         .ops            = &clkops_omap2_dflt_wait,
2946         .init           = &omap2_init_clksel_parent,
2947         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2948         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
2949         .clksel_reg     = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2950         .clksel_mask    = OMAP2_MCBSP4_CLKS_MASK,
2951         .clksel         = mcbsp_234_clksel,
2952         .clkdm_name     = "per_clkdm",
2953         .recalc         = &omap2_clksel_recalc,
2954 };
2955
2956 /* EMU clocks */
2957
2958 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2959
2960 static const struct clksel_rate emu_src_sys_rates[] = {
2961         { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2962         { .div = 0 },
2963 };
2964
2965 static const struct clksel_rate emu_src_core_rates[] = {
2966         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2967         { .div = 0 },
2968 };
2969
2970 static const struct clksel_rate emu_src_per_rates[] = {
2971         { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2972         { .div = 0 },
2973 };
2974
2975 static const struct clksel_rate emu_src_mpu_rates[] = {
2976         { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2977         { .div = 0 },
2978 };
2979
2980 static const struct clksel emu_src_clksel[] = {
2981         { .parent = &sys_ck,            .rates = emu_src_sys_rates },
2982         { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2983         { .parent = &emu_per_alwon_ck,  .rates = emu_src_per_rates },
2984         { .parent = &emu_mpu_alwon_ck,  .rates = emu_src_mpu_rates },
2985         { .parent = NULL },
2986 };
2987
2988 /*
2989  * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2990  * to switch the source of some of the EMU clocks.
2991  * XXX Are there CLKEN bits for these EMU clks?
2992  */
2993 static struct clk emu_src_ck = {
2994         .name           = "emu_src_ck",
2995         .ops            = &clkops_null,
2996         .init           = &omap2_init_clksel_parent,
2997         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2998         .clksel_mask    = OMAP3430_MUX_CTRL_MASK,
2999         .clksel         = emu_src_clksel,
3000         .clkdm_name     = "emu_clkdm",
3001         .recalc         = &omap2_clksel_recalc,
3002 };
3003
3004 static const struct clksel_rate pclk_emu_rates[] = {
3005         { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
3006         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3007         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3008         { .div = 6, .val = 6, .flags = RATE_IN_343X },
3009         { .div = 0 },
3010 };
3011
3012 static const struct clksel pclk_emu_clksel[] = {
3013         { .parent = &emu_src_ck, .rates = pclk_emu_rates },
3014         { .parent = NULL },
3015 };
3016
3017 static struct clk pclk_fck = {
3018         .name           = "pclk_fck",
3019         .ops            = &clkops_null,
3020         .init           = &omap2_init_clksel_parent,
3021         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3022         .clksel_mask    = OMAP3430_CLKSEL_PCLK_MASK,
3023         .clksel         = pclk_emu_clksel,
3024         .clkdm_name     = "emu_clkdm",
3025         .recalc         = &omap2_clksel_recalc,
3026 };
3027
3028 static const struct clksel_rate pclkx2_emu_rates[] = {
3029         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3030         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3031         { .div = 3, .val = 3, .flags = RATE_IN_343X },
3032         { .div = 0 },
3033 };
3034
3035 static const struct clksel pclkx2_emu_clksel[] = {
3036         { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
3037         { .parent = NULL },
3038 };
3039
3040 static struct clk pclkx2_fck = {
3041         .name           = "pclkx2_fck",
3042         .ops            = &clkops_null,
3043         .init           = &omap2_init_clksel_parent,
3044         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3045         .clksel_mask    = OMAP3430_CLKSEL_PCLKX2_MASK,
3046         .clksel         = pclkx2_emu_clksel,
3047         .clkdm_name     = "emu_clkdm",
3048         .recalc         = &omap2_clksel_recalc,
3049 };
3050
3051 static const struct clksel atclk_emu_clksel[] = {
3052         { .parent = &emu_src_ck, .rates = div2_rates },
3053         { .parent = NULL },
3054 };
3055
3056 static struct clk atclk_fck = {
3057         .name           = "atclk_fck",
3058         .ops            = &clkops_null,
3059         .init           = &omap2_init_clksel_parent,
3060         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3061         .clksel_mask    = OMAP3430_CLKSEL_ATCLK_MASK,
3062         .clksel         = atclk_emu_clksel,
3063         .clkdm_name     = "emu_clkdm",
3064         .recalc         = &omap2_clksel_recalc,
3065 };
3066
3067 static struct clk traceclk_src_fck = {
3068         .name           = "traceclk_src_fck",
3069         .ops            = &clkops_null,
3070         .init           = &omap2_init_clksel_parent,
3071         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3072         .clksel_mask    = OMAP3430_TRACE_MUX_CTRL_MASK,
3073         .clksel         = emu_src_clksel,
3074         .clkdm_name     = "emu_clkdm",
3075         .recalc         = &omap2_clksel_recalc,
3076 };
3077
3078 static const struct clksel_rate traceclk_rates[] = {
3079         { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
3080         { .div = 2, .val = 2, .flags = RATE_IN_343X },
3081         { .div = 4, .val = 4, .flags = RATE_IN_343X },
3082         { .div = 0 },
3083 };
3084
3085 static const struct clksel traceclk_clksel[] = {
3086         { .parent = &traceclk_src_fck, .rates = traceclk_rates },
3087         { .parent = NULL },
3088 };
3089
3090 static struct clk traceclk_fck = {
3091         .name           = "traceclk_fck",
3092         .ops            = &clkops_null,
3093         .init           = &omap2_init_clksel_parent,
3094         .clksel_reg     = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
3095         .clksel_mask    = OMAP3430_CLKSEL_TRACECLK_MASK,
3096         .clksel         = traceclk_clksel,
3097         .clkdm_name     = "emu_clkdm",
3098         .recalc         = &omap2_clksel_recalc,
3099 };
3100
3101 /* SR clocks */
3102
3103 /* SmartReflex fclk (VDD1) */
3104 static struct clk sr1_fck = {
3105         .name           = "sr1_fck",
3106         .ops            = &clkops_omap2_dflt_wait,
3107         .parent         = &sys_ck,
3108         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3109         .enable_bit     = OMAP3430_EN_SR1_SHIFT,
3110         .recalc         = &followparent_recalc,
3111 };
3112
3113 /* SmartReflex fclk (VDD2) */
3114 static struct clk sr2_fck = {
3115         .name           = "sr2_fck",
3116         .ops            = &clkops_omap2_dflt_wait,
3117         .parent         = &sys_ck,
3118         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
3119         .enable_bit     = OMAP3430_EN_SR2_SHIFT,
3120         .recalc         = &followparent_recalc,
3121 };
3122
3123 static struct clk sr_l4_ick = {
3124         .name           = "sr_l4_ick",
3125         .ops            = &clkops_null, /* RMK: missing? */
3126         .parent         = &l4_ick,
3127         .clkdm_name     = "core_l4_clkdm",
3128         .recalc         = &followparent_recalc,
3129 };
3130
3131 /* SECURE_32K_FCK clocks */
3132
3133 static struct clk gpt12_fck = {
3134         .name           = "gpt12_fck",
3135         .ops            = &clkops_null,
3136         .parent         = &secure_32k_fck,
3137         .recalc         = &followparent_recalc,
3138 };
3139
3140 static struct clk wdt1_fck = {
3141         .name           = "wdt1_fck",
3142         .ops            = &clkops_null,
3143         .parent         = &secure_32k_fck,
3144         .recalc         = &followparent_recalc,
3145 };
3146
3147 /* Clocks for AM35XX */
3148 static struct clk ipss_ick = {
3149         .name           = "ipss_ick",
3150         .ops            = &clkops_am35xx_ipss_wait,
3151         .parent         = &core_l3_ick,
3152         .clkdm_name     = "core_l3_clkdm",
3153         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3154         .enable_bit     = AM35XX_EN_IPSS_SHIFT,
3155         .recalc         = &followparent_recalc,
3156 };
3157
3158 static struct clk emac_ick = {
3159         .name           = "emac_ick",
3160         .ops            = &clkops_am35xx_ipss_module_wait,
3161         .parent         = &ipss_ick,
3162         .clkdm_name     = "core_l3_clkdm",
3163         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3164         .enable_bit     = AM35XX_CPGMAC_VBUSP_CLK_SHIFT,
3165         .recalc         = &followparent_recalc,
3166 };
3167
3168 static struct clk rmii_ck = {
3169         .name           = "rmii_ck",
3170         .ops            = &clkops_null,
3171         .flags          = RATE_FIXED,
3172         .rate           = 50000000,
3173 };
3174
3175 static struct clk emac_fck = {
3176         .name           = "emac_fck",
3177         .ops            = &clkops_omap2_dflt,
3178         .parent         = &rmii_ck,
3179         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3180         .enable_bit     = AM35XX_CPGMAC_FCLK_SHIFT,
3181         .recalc         = &followparent_recalc,
3182 };
3183
3184 static struct clk hsotgusb_ick_am35xx = {
3185         .name           = "hsotgusb_ick",
3186         .ops            = &clkops_am35xx_ipss_module_wait,
3187         .parent         = &ipss_ick,
3188         .clkdm_name     = "core_l3_clkdm",
3189         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3190         .enable_bit     = AM35XX_USBOTG_VBUSP_CLK_SHIFT,
3191         .recalc         = &followparent_recalc,
3192 };
3193
3194 static struct clk hsotgusb_fck_am35xx = {
3195         .name           = "hsotgusb_fck",
3196         .ops            = &clkops_omap2_dflt,
3197         .parent         = &sys_ck,
3198         .clkdm_name     = "core_l3_clkdm",
3199         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3200         .enable_bit     = AM35XX_USBOTG_FCLK_SHIFT,
3201         .recalc         = &followparent_recalc,
3202 };
3203
3204 static struct clk hecc_ck = {
3205         .name           = "hecc_ck",
3206         .ops            = &clkops_am35xx_ipss_module_wait,
3207         .parent         = &sys_ck,
3208         .clkdm_name     = "core_l3_clkdm",
3209         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3210         .enable_bit     = AM35XX_HECC_VBUSP_CLK_SHIFT,
3211         .recalc         = &followparent_recalc,
3212 };
3213
3214 static struct clk vpfe_ick = {
3215         .name           = "vpfe_ick",
3216         .ops            = &clkops_am35xx_ipss_module_wait,
3217         .parent         = &ipss_ick,
3218         .clkdm_name     = "core_l3_clkdm",
3219         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3220         .enable_bit     = AM35XX_VPFE_VBUSP_CLK_SHIFT,
3221         .recalc         = &followparent_recalc,
3222 };
3223
3224 static struct clk pclk_ck = {
3225         .name           = "pclk_ck",
3226         .ops            = &clkops_null,
3227         .flags          = RATE_FIXED,
3228         .rate           = 27000000,
3229 };
3230
3231 static struct clk vpfe_fck = {
3232         .name           = "vpfe_fck",
3233         .ops            = &clkops_omap2_dflt,
3234         .parent         = &pclk_ck,
3235         .enable_reg     = OMAP343X_CTRL_REGADDR(AM35XX_CONTROL_IPSS_CLK_CTRL),
3236         .enable_bit     = AM35XX_VPFE_FCLK_SHIFT,
3237         .recalc         = &followparent_recalc,
3238 };
3239
3240 /*
3241  * The UART1/2 functional clock acts as the functional
3242  * clock for UART4. No separate fclk control available.
3243  */
3244 static struct clk uart4_ick_am35xx = {
3245         .name           = "uart4_ick",
3246         .ops            = &clkops_omap2_dflt_wait,
3247         .parent         = &core_l4_ick,
3248         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
3249         .enable_bit     = AM35XX_EN_UART4_SHIFT,
3250         .clkdm_name     = "core_l4_clkdm",
3251         .recalc         = &followparent_recalc,
3252 };
3253
3254
3255 /*
3256  * clkdev
3257  */
3258
3259 /* XXX At some point we should rename this file to clock3xxx_data.c */
3260 static struct omap_clk omap3xxx_clks[] = {
3261         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
3262         CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
3263         CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
3264         CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2 | CK_AM35XX),
3265         CLK(NULL,       "virt_19_2m_ck", &virt_19_2m_ck, CK_3XXX),
3266         CLK(NULL,       "virt_26m_ck",  &virt_26m_ck,   CK_3XXX),
3267         CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
3268         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
3269         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
3270         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
3271         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
3272         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
3273         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
3274         CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
3275         CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
3276         CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_343X),
3277         CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_343X),
3278         CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
3279         CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
3280         CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
3281         CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
3282         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
3283         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
3284         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
3285         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
3286         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
3287         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
3288         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
3289         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
3290         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
3291         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
3292         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
3293         CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
3294         CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
3295         CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
3296         CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
3297         CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
3298         CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
3299         CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
3300         CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
3301         CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
3302         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
3303         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
3304         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
3305         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
3306         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2 | CK_AM35XX),
3307         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2 | CK_AM35XX),
3308         CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
3309         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
3310         CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
3311         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
3312         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
3313         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
3314         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
3315         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_343X),
3316         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_343X),
3317         CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
3318         CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
3319         CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
3320         CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
3321         CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
3322         CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
3323         CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
3324         CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
3325         CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2 | CK_3517),
3326         CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2 | CK_3517),
3327         CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
3328         CLK(NULL,       "modem_fck",    &modem_fck,     CK_343X),
3329         CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_343X),
3330         CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_343X),
3331         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
3332         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
3333         CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2 | CK_AM35XX),
3334         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2 | CK_AM35XX),
3335         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2 | CK_AM35XX),
3336         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
3337         CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2 | CK_AM35XX),
3338         CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_3XXX),
3339         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_343X),
3340         CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_3XXX),
3341         CLK("i2c_omap.3", "fck",        &i2c3_fck,      CK_3XXX),
3342         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_3XXX),
3343         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_3XXX),
3344         CLK("omap-mcbsp.5", "fck",      &mcbsp5_fck,    CK_3XXX),
3345         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_3XXX),
3346         CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
3347         CLK("omap2_mcspi.4", "fck",     &mcspi4_fck,    CK_3XXX),
3348         CLK("omap2_mcspi.3", "fck",     &mcspi3_fck,    CK_3XXX),
3349         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_3XXX),
3350         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_3XXX),
3351         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
3352         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
3353         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
3354         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
3355         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_3XXX),
3356         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
3357         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2),
3358         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
3359         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2),
3360         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
3361         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
3362         CLK("musb_hdrc",        "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2),
3363         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
3364         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
3365         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
3366         CLK(NULL,       "pka_ick",      &pka_ick,       CK_343X),
3367         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
3368         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2 | CK_AM35XX),
3369         CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2 | CK_AM35XX),
3370         CLK(NULL,       "icr_ick",      &icr_ick,       CK_343X),
3371         CLK(NULL,       "aes2_ick",     &aes2_ick,      CK_343X),
3372         CLK(NULL,       "sha12_ick",    &sha12_ick,     CK_343X),
3373         CLK(NULL,       "des2_ick",     &des2_ick,      CK_343X),
3374         CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_3XXX),
3375         CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_3XXX),
3376         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_343X),
3377         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
3378         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
3379         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
3380         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
3381         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
3382         CLK("i2c_omap.3", "ick",        &i2c3_ick,      CK_3XXX),
3383         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_3XXX),
3384         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_3XXX),
3385         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
3386         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
3387         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
3388         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
3389         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
3390         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
3391         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
3392         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_343X),
3393         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
3394         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_343X),
3395         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
3396         CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2),
3397         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
3398         CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_343X),
3399         CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_343X),
3400         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
3401         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
3402         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
3403         CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es1, CK_3430ES1),
3404         CLK("omapdss",  "dss1_fck",     &dss1_alwon_fck_3430es2, CK_3430ES2 | CK_AM35XX),
3405         CLK("omapdss",  "tv_fck",       &dss_tv_fck,    CK_3XXX),
3406         CLK("omapdss",  "video_fck",    &dss_96m_fck,   CK_3XXX),
3407         CLK("omapdss",  "dss2_fck",     &dss2_alwon_fck, CK_3XXX),
3408         CLK("omapdss",  "ick",          &dss_ick_3430es1,       CK_3430ES1),
3409         CLK("omapdss",  "ick",          &dss_ick_3430es2,       CK_3430ES2 | CK_AM35XX),
3410         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
3411         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
3412         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
3413         CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2 | CK_AM35XX),
3414         CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2 | CK_AM35XX),
3415         CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2 | CK_AM35XX),
3416         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2),
3417         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
3418         CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
3419         CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
3420         CLK("omap_wdt", "fck",          &wdt2_fck,      CK_3XXX),
3421         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_343X),
3422         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2),
3423         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
3424         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
3425         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
3426         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
3427         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
3428         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
3429         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
3430         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
3431         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
3432         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
3433         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
3434         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
3435         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
3436         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
3437         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
3438         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
3439         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
3440         CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
3441         CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
3442         CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
3443         CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
3444         CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
3445         CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
3446         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
3447         CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
3448         CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
3449         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
3450         CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
3451         CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
3452         CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
3453         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
3454         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
3455         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
3456         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
3457         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
3458         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
3459         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
3460         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
3461         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
3462         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
3463         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
3464         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
3465         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
3466         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_3XXX),
3467         CLK("omap-mcbsp.3", "fck",      &mcbsp3_fck,    CK_3XXX),
3468         CLK("omap-mcbsp.4", "fck",      &mcbsp4_fck,    CK_3XXX),
3469         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
3470         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
3471         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
3472         CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
3473         CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
3474         CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
3475         CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_343X),
3476         CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_343X),
3477         CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_343X),
3478         CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
3479         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
3480         CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
3481         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
3482         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
3483         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
3484         CLK("davinci_emac",     "ick",          &emac_ick,      CK_AM35XX),
3485         CLK("davinci_emac",     "fck",          &emac_fck,      CK_AM35XX),
3486         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
3487         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
3488         CLK("musb_hdrc",        "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
3489         CLK("musb_hdrc",        "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
3490         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
3491         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
3492 };
3493
3494
3495 int __init omap3xxx_clk_init(void)
3496 {
3497         struct omap_clk *c;
3498         u32 cpu_clkflg = CK_3XXX;
3499
3500         if (cpu_is_omap3517()) {
3501                 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3502                 cpu_clkflg |= CK_3517;
3503         } else if (cpu_is_omap3505()) {
3504                 cpu_mask = RATE_IN_343X | RATE_IN_3430ES2;
3505                 cpu_clkflg |= CK_3505;
3506         } else if (cpu_is_omap34xx()) {
3507                 cpu_mask = RATE_IN_343X;
3508                 cpu_clkflg |= CK_343X;
3509
3510                 /*
3511                  * Update this if there are further clock changes between ES2
3512                  * and production parts
3513                  */
3514                 if (omap_rev() == OMAP3430_REV_ES1_0) {
3515                         /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */
3516                         cpu_clkflg |= CK_3430ES1;
3517                 } else {
3518                         cpu_mask |= RATE_IN_3430ES2;
3519                         cpu_clkflg |= CK_3430ES2;
3520                 }
3521         }
3522         if (omap3_has_192mhz_clk())
3523                 omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
3524
3525         if (cpu_is_omap3630()) {
3526                 cpu_mask |= RATE_IN_36XX;
3527                 cpu_clkflg |= CK_36XX;
3528
3529                 /*
3530                  * XXX This type of dynamic rewriting of the clock tree is
3531                  * deprecated and should be revised soon.
3532                  */
3533                 dpll4_m2_ck = dpll4_m2_ck_3630;
3534                 dpll4_m3_ck = dpll4_m3_ck_3630;
3535                 dpll4_m4_ck = dpll4_m4_ck_3630;
3536                 dpll4_m5_ck = dpll4_m5_ck_3630;
3537                 dpll4_m6_ck = dpll4_m6_ck_3630;
3538
3539                 /*
3540                  * For 3630: override clkops_omap2_dflt_wait for the
3541                  * clocks affected from PWRDN reset Limitation
3542                  */
3543                 dpll3_m3x2_ck.ops =
3544                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3545                 dpll4_m2x2_ck.ops =
3546                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3547                 dpll4_m3x2_ck.ops =
3548                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3549                 dpll4_m4x2_ck.ops =
3550                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3551                 dpll4_m5x2_ck.ops =
3552                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3553                 dpll4_m6x2_ck.ops =
3554                                 &clkops_omap36xx_pwrdn_with_hsdiv_wait_restore;
3555         } else {
3556                 /*
3557                  * XXX This type of dynamic rewriting of the clock tree is
3558                  * deprecated and should be revised soon.
3559                  */
3560                 dpll4_m2_ck = dpll4_m2_ck_34xx;
3561                 dpll4_m3_ck = dpll4_m3_ck_34xx;
3562                 dpll4_m4_ck = dpll4_m4_ck_34xx;
3563                 dpll4_m5_ck = dpll4_m5_ck_34xx;
3564                 dpll4_m6_ck = dpll4_m6_ck_34xx;
3565         }
3566
3567         if (cpu_is_omap3630())
3568                 dpll4_dd = dpll4_dd_3630;
3569         else
3570                 dpll4_dd = dpll4_dd_34xx;
3571
3572         clk_init(&omap2_clk_functions);
3573
3574         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3575              c++)
3576                 clk_preinit(c->lk.clk);
3577
3578         for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
3579              c++)
3580                 if (c->cpu & cpu_clkflg) {
3581                         clkdev_add(&c->lk);
3582                         clk_register(c->lk.clk);
3583                         omap2_init_clk_clkdm(c->lk.clk);
3584                 }
3585
3586         recalculate_root_clocks();
3587
3588         printk(KERN_INFO "Clocking rate (Crystal/Core/MPU): "
3589                "%ld.%01ld/%ld/%ld MHz\n",
3590                (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
3591                (core_ck.rate / 1000000), (arm_fck.rate / 1000000));
3592
3593         /*
3594          * Only enable those clocks we will need, let the drivers
3595          * enable other clocks as necessary
3596          */
3597         clk_enable_init_clocks();
3598
3599         /*
3600          * Lock DPLL5 and put it in autoidle.
3601          */
3602         if (omap_rev() >= OMAP3430_REV_ES2_0)
3603                 omap3_clk_lock_dpll5();
3604
3605         /* Avoid sleeping during omap3_core_dpll_m2_set_rate() */
3606         sdrc_ick_p = clk_get(NULL, "sdrc_ick");
3607         arm_fck_p = clk_get(NULL, "arm_fck");
3608
3609         return 0;
3610 }