2 * OMAP3 clock framework
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2008 Nokia Corporation
7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
19 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
20 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
22 #include <asm/arch/control.h>
26 #include "cm-regbits-34xx.h"
28 #include "prm-regbits-34xx.h"
30 static void omap3_dpll_recalc(struct clk *clk);
31 static void omap3_clkoutx2_recalc(struct clk *clk);
32 static void omap3_dpll_allow_idle(struct clk *clk);
33 static void omap3_dpll_deny_idle(struct clk *clk);
34 static u32 omap3_dpll_autoidle_read(struct clk *clk);
35 static int omap3_noncore_dpll_enable(struct clk *clk);
36 static void omap3_noncore_dpll_disable(struct clk *clk);
39 * DPLL1 supplies clock to the MPU.
40 * DPLL2 supplies clock to the IVA2.
41 * DPLL3 supplies CORE domain clocks.
42 * DPLL4 supplies peripheral clocks.
43 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
46 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
47 #define DPLL_LOW_POWER_STOP 0x1
48 #define DPLL_LOW_POWER_BYPASS 0x5
49 #define DPLL_LOCKED 0x7
53 /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
54 static struct clk omap_32k_fck = {
55 .name = "omap_32k_fck",
57 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
59 .recalc = &propagate_rate,
62 static struct clk secure_32k_fck = {
63 .name = "secure_32k_fck",
65 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
67 .recalc = &propagate_rate,
70 /* Virtual source clocks for osc_sys_ck */
71 static struct clk virt_12m_ck = {
72 .name = "virt_12m_ck",
74 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
76 .recalc = &propagate_rate,
79 static struct clk virt_13m_ck = {
80 .name = "virt_13m_ck",
82 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
84 .recalc = &propagate_rate,
87 static struct clk virt_16_8m_ck = {
88 .name = "virt_16_8m_ck",
90 .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
92 .recalc = &propagate_rate,
95 static struct clk virt_19_2m_ck = {
96 .name = "virt_19_2m_ck",
98 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
100 .recalc = &propagate_rate,
103 static struct clk virt_26m_ck = {
104 .name = "virt_26m_ck",
106 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
108 .recalc = &propagate_rate,
111 static struct clk virt_38_4m_ck = {
112 .name = "virt_38_4m_ck",
114 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
116 .recalc = &propagate_rate,
119 static const struct clksel_rate osc_sys_12m_rates[] = {
120 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
124 static const struct clksel_rate osc_sys_13m_rates[] = {
125 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
129 static const struct clksel_rate osc_sys_16_8m_rates[] = {
130 { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE },
134 static const struct clksel_rate osc_sys_19_2m_rates[] = {
135 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
139 static const struct clksel_rate osc_sys_26m_rates[] = {
140 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
144 static const struct clksel_rate osc_sys_38_4m_rates[] = {
145 { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE },
149 static const struct clksel osc_sys_clksel[] = {
150 { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates },
151 { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates },
152 { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates },
153 { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates },
154 { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates },
155 { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates },
159 /* Oscillator clock */
160 /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */
161 static struct clk osc_sys_ck = {
162 .name = "osc_sys_ck",
163 .init = &omap2_init_clksel_parent,
164 .clksel_reg = OMAP3430_PRM_CLKSEL,
165 .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK,
166 .clksel = osc_sys_clksel,
167 /* REVISIT: deal with autoextclkmode? */
168 .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
170 .recalc = &omap2_clksel_recalc,
173 static const struct clksel_rate div2_rates[] = {
174 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
175 { .div = 2, .val = 2, .flags = RATE_IN_343X },
179 static const struct clksel sys_clksel[] = {
180 { .parent = &osc_sys_ck, .rates = div2_rates },
184 /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */
185 /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */
186 static struct clk sys_ck = {
188 .parent = &osc_sys_ck,
189 .init = &omap2_init_clksel_parent,
190 .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL,
191 .clksel_mask = OMAP_SYSCLKDIV_MASK,
192 .clksel = sys_clksel,
193 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
194 .recalc = &omap2_clksel_recalc,
197 static struct clk sys_altclk = {
198 .name = "sys_altclk",
199 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
200 .recalc = &propagate_rate,
203 /* Optional external clock input for some McBSPs */
204 static struct clk mcbsp_clks = {
205 .name = "mcbsp_clks",
206 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
207 .recalc = &propagate_rate,
210 /* PRM EXTERNAL CLOCK OUTPUT */
212 static struct clk sys_clkout1 = {
213 .name = "sys_clkout1",
214 .parent = &osc_sys_ck,
215 .enable_reg = OMAP3430_PRM_CLKOUT_CTRL,
216 .enable_bit = OMAP3430_CLKOUT_EN_SHIFT,
217 .flags = CLOCK_IN_OMAP343X,
218 .recalc = &followparent_recalc,
225 static const struct clksel_rate dpll_bypass_rates[] = {
226 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
230 static const struct clksel_rate dpll_locked_rates[] = {
231 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
235 static const struct clksel_rate div16_dpll_rates[] = {
236 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
237 { .div = 2, .val = 2, .flags = RATE_IN_343X },
238 { .div = 3, .val = 3, .flags = RATE_IN_343X },
239 { .div = 4, .val = 4, .flags = RATE_IN_343X },
240 { .div = 5, .val = 5, .flags = RATE_IN_343X },
241 { .div = 6, .val = 6, .flags = RATE_IN_343X },
242 { .div = 7, .val = 7, .flags = RATE_IN_343X },
243 { .div = 8, .val = 8, .flags = RATE_IN_343X },
244 { .div = 9, .val = 9, .flags = RATE_IN_343X },
245 { .div = 10, .val = 10, .flags = RATE_IN_343X },
246 { .div = 11, .val = 11, .flags = RATE_IN_343X },
247 { .div = 12, .val = 12, .flags = RATE_IN_343X },
248 { .div = 13, .val = 13, .flags = RATE_IN_343X },
249 { .div = 14, .val = 14, .flags = RATE_IN_343X },
250 { .div = 15, .val = 15, .flags = RATE_IN_343X },
251 { .div = 16, .val = 16, .flags = RATE_IN_343X },
256 /* MPU clock source */
258 static const struct dpll_data dpll1_dd = {
259 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
260 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
261 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
262 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
263 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
264 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
265 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
266 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
267 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
268 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
269 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
270 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
271 .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT,
274 static struct clk dpll1_ck = {
277 .dpll_data = &dpll1_dd,
278 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
279 .recalc = &omap3_dpll_recalc,
283 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
284 * DPLL isn't bypassed.
286 static struct clk dpll1_x2_ck = {
287 .name = "dpll1_x2_ck",
289 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
290 PARENT_CONTROLS_CLOCK,
291 .recalc = &omap3_clkoutx2_recalc,
294 /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */
295 static const struct clksel div16_dpll1_x2m2_clksel[] = {
296 { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates },
301 * Does not exist in the TRM - needed to separate the M2 divider from
302 * bypass selection in mpu_ck
304 static struct clk dpll1_x2m2_ck = {
305 .name = "dpll1_x2m2_ck",
306 .parent = &dpll1_x2_ck,
307 .init = &omap2_init_clksel_parent,
308 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL),
309 .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK,
310 .clksel = div16_dpll1_x2m2_clksel,
311 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
312 PARENT_CONTROLS_CLOCK,
313 .recalc = &omap2_clksel_recalc,
317 /* IVA2 clock source */
320 static const struct dpll_data dpll2_dd = {
321 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
322 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
323 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
324 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
325 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
326 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
327 (1 << DPLL_LOW_POWER_BYPASS),
328 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
329 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
330 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
331 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
332 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
333 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
334 .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT
337 static struct clk dpll2_ck = {
340 .dpll_data = &dpll2_dd,
341 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
342 .enable = &omap3_noncore_dpll_enable,
343 .disable = &omap3_noncore_dpll_disable,
344 .recalc = &omap3_dpll_recalc,
347 static const struct clksel div16_dpll2_m2x2_clksel[] = {
348 { .parent = &dpll2_ck, .rates = div16_dpll_rates },
353 * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT
354 * or CLKOUTX2. CLKOUT seems most plausible.
356 static struct clk dpll2_m2_ck = {
357 .name = "dpll2_m2_ck",
359 .init = &omap2_init_clksel_parent,
360 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
361 OMAP3430_CM_CLKSEL2_PLL),
362 .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK,
363 .clksel = div16_dpll2_m2x2_clksel,
364 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
365 PARENT_CONTROLS_CLOCK,
366 .recalc = &omap2_clksel_recalc,
371 * Source clock for all interfaces and for some device fclks
372 * REVISIT: Also supports fast relock bypass - not included below
374 static const struct dpll_data dpll3_dd = {
375 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
376 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
377 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
378 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
379 .enable_mask = OMAP3430_EN_CORE_DPLL_MASK,
380 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
381 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
382 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
383 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
384 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
387 static struct clk dpll3_ck = {
390 .dpll_data = &dpll3_dd,
391 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
392 .recalc = &omap3_dpll_recalc,
396 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
397 * DPLL isn't bypassed
399 static struct clk dpll3_x2_ck = {
400 .name = "dpll3_x2_ck",
402 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
403 PARENT_CONTROLS_CLOCK,
404 .recalc = &omap3_clkoutx2_recalc,
407 static const struct clksel_rate div31_dpll3_rates[] = {
408 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
409 { .div = 2, .val = 2, .flags = RATE_IN_343X },
410 { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 },
411 { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 },
412 { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 },
413 { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 },
414 { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 },
415 { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 },
416 { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 },
417 { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 },
418 { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 },
419 { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 },
420 { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 },
421 { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 },
422 { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 },
423 { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 },
424 { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 },
425 { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 },
426 { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 },
427 { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 },
428 { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 },
429 { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 },
430 { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 },
431 { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 },
432 { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 },
433 { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 },
434 { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 },
435 { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 },
436 { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 },
437 { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 },
438 { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 },
442 static const struct clksel div31_dpll3m2_clksel[] = {
443 { .parent = &dpll3_ck, .rates = div31_dpll3_rates },
449 * REVISIT: This DPLL output divider must be changed in SRAM, so until
450 * that code is ready, this should remain a 'read-only' clksel clock.
452 static struct clk dpll3_m2_ck = {
453 .name = "dpll3_m2_ck",
455 .init = &omap2_init_clksel_parent,
456 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
457 .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK,
458 .clksel = div31_dpll3m2_clksel,
459 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
460 PARENT_CONTROLS_CLOCK,
461 .recalc = &omap2_clksel_recalc,
464 static const struct clksel core_ck_clksel[] = {
465 { .parent = &sys_ck, .rates = dpll_bypass_rates },
466 { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates },
470 static struct clk core_ck = {
472 .init = &omap2_init_clksel_parent,
473 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
474 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
475 .clksel = core_ck_clksel,
476 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
477 PARENT_CONTROLS_CLOCK,
478 .recalc = &omap2_clksel_recalc,
481 static const struct clksel dpll3_m2x2_ck_clksel[] = {
482 { .parent = &sys_ck, .rates = dpll_bypass_rates },
483 { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates },
487 static struct clk dpll3_m2x2_ck = {
488 .name = "dpll3_m2x2_ck",
489 .init = &omap2_init_clksel_parent,
490 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
491 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
492 .clksel = dpll3_m2x2_ck_clksel,
493 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
494 PARENT_CONTROLS_CLOCK,
495 .recalc = &omap2_clksel_recalc,
498 /* The PWRDN bit is apparently only available on 3430ES2 and above */
499 static const struct clksel div16_dpll3_clksel[] = {
500 { .parent = &dpll3_ck, .rates = div16_dpll_rates },
504 /* This virtual clock is the source for dpll3_m3x2_ck */
505 static struct clk dpll3_m3_ck = {
506 .name = "dpll3_m3_ck",
508 .init = &omap2_init_clksel_parent,
509 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
510 .clksel_mask = OMAP3430_DIV_DPLL3_MASK,
511 .clksel = div16_dpll3_clksel,
512 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
513 PARENT_CONTROLS_CLOCK,
514 .recalc = &omap2_clksel_recalc,
517 /* The PWRDN bit is apparently only available on 3430ES2 and above */
518 static struct clk dpll3_m3x2_ck = {
519 .name = "dpll3_m3x2_ck",
520 .parent = &dpll3_m3_ck,
521 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
522 .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT,
523 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
524 .recalc = &omap3_clkoutx2_recalc,
527 static const struct clksel emu_core_alwon_ck_clksel[] = {
528 { .parent = &sys_ck, .rates = dpll_bypass_rates },
529 { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates },
533 static struct clk emu_core_alwon_ck = {
534 .name = "emu_core_alwon_ck",
535 .parent = &dpll3_m3x2_ck,
536 .init = &omap2_init_clksel_parent,
537 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
538 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
539 .clksel = emu_core_alwon_ck_clksel,
540 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
541 PARENT_CONTROLS_CLOCK,
542 .recalc = &omap2_clksel_recalc,
546 /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
548 static const struct dpll_data dpll4_dd = {
549 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
550 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
551 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
552 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
553 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
554 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
555 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
556 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
557 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
558 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
559 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
560 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
561 .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT,
564 static struct clk dpll4_ck = {
567 .dpll_data = &dpll4_dd,
568 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
569 .enable = &omap3_noncore_dpll_enable,
570 .disable = &omap3_noncore_dpll_disable,
571 .recalc = &omap3_dpll_recalc,
575 * This virtual clock provides the CLKOUTX2 output from the DPLL if the
576 * DPLL isn't bypassed --
577 * XXX does this serve any downstream clocks?
579 static struct clk dpll4_x2_ck = {
580 .name = "dpll4_x2_ck",
582 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
583 PARENT_CONTROLS_CLOCK,
584 .recalc = &omap3_clkoutx2_recalc,
587 static const struct clksel div16_dpll4_clksel[] = {
588 { .parent = &dpll4_ck, .rates = div16_dpll_rates },
592 /* This virtual clock is the source for dpll4_m2x2_ck */
593 static struct clk dpll4_m2_ck = {
594 .name = "dpll4_m2_ck",
596 .init = &omap2_init_clksel_parent,
597 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3),
598 .clksel_mask = OMAP3430_DIV_96M_MASK,
599 .clksel = div16_dpll4_clksel,
600 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
601 PARENT_CONTROLS_CLOCK,
602 .recalc = &omap2_clksel_recalc,
605 /* The PWRDN bit is apparently only available on 3430ES2 and above */
606 static struct clk dpll4_m2x2_ck = {
607 .name = "dpll4_m2x2_ck",
608 .parent = &dpll4_m2_ck,
609 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
610 .enable_bit = OMAP3430_PWRDN_96M_SHIFT,
611 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
612 .recalc = &omap3_clkoutx2_recalc,
615 static const struct clksel omap_96m_alwon_fck_clksel[] = {
616 { .parent = &sys_ck, .rates = dpll_bypass_rates },
617 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
621 static struct clk omap_96m_alwon_fck = {
622 .name = "omap_96m_alwon_fck",
623 .parent = &dpll4_m2x2_ck,
624 .init = &omap2_init_clksel_parent,
625 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
626 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
627 .clksel = omap_96m_alwon_fck_clksel,
628 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
629 PARENT_CONTROLS_CLOCK,
630 .recalc = &omap2_clksel_recalc,
633 static struct clk omap_96m_fck = {
634 .name = "omap_96m_fck",
635 .parent = &omap_96m_alwon_fck,
636 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
637 PARENT_CONTROLS_CLOCK,
638 .recalc = &followparent_recalc,
641 static const struct clksel cm_96m_fck_clksel[] = {
642 { .parent = &sys_ck, .rates = dpll_bypass_rates },
643 { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates },
647 static struct clk cm_96m_fck = {
648 .name = "cm_96m_fck",
649 .parent = &dpll4_m2x2_ck,
650 .init = &omap2_init_clksel_parent,
651 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
652 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
653 .clksel = cm_96m_fck_clksel,
654 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
655 PARENT_CONTROLS_CLOCK,
656 .recalc = &omap2_clksel_recalc,
659 /* This virtual clock is the source for dpll4_m3x2_ck */
660 static struct clk dpll4_m3_ck = {
661 .name = "dpll4_m3_ck",
663 .init = &omap2_init_clksel_parent,
664 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
665 .clksel_mask = OMAP3430_CLKSEL_TV_MASK,
666 .clksel = div16_dpll4_clksel,
667 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
668 PARENT_CONTROLS_CLOCK,
669 .recalc = &omap2_clksel_recalc,
672 /* The PWRDN bit is apparently only available on 3430ES2 and above */
673 static struct clk dpll4_m3x2_ck = {
674 .name = "dpll4_m3x2_ck",
675 .parent = &dpll4_m3_ck,
676 .init = &omap2_init_clksel_parent,
677 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
678 .enable_bit = OMAP3430_PWRDN_TV_SHIFT,
679 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
680 .recalc = &omap3_clkoutx2_recalc,
683 static const struct clksel virt_omap_54m_fck_clksel[] = {
684 { .parent = &sys_ck, .rates = dpll_bypass_rates },
685 { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates },
689 static struct clk virt_omap_54m_fck = {
690 .name = "virt_omap_54m_fck",
691 .parent = &dpll4_m3x2_ck,
692 .init = &omap2_init_clksel_parent,
693 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
694 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
695 .clksel = virt_omap_54m_fck_clksel,
696 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
697 PARENT_CONTROLS_CLOCK,
698 .recalc = &omap2_clksel_recalc,
701 static const struct clksel_rate omap_54m_d4m3x2_rates[] = {
702 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
706 static const struct clksel_rate omap_54m_alt_rates[] = {
707 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
711 static const struct clksel omap_54m_clksel[] = {
712 { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates },
713 { .parent = &sys_altclk, .rates = omap_54m_alt_rates },
717 static struct clk omap_54m_fck = {
718 .name = "omap_54m_fck",
719 .init = &omap2_init_clksel_parent,
720 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
721 .clksel_mask = OMAP3430_SOURCE_54M,
722 .clksel = omap_54m_clksel,
723 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
724 PARENT_CONTROLS_CLOCK,
725 .recalc = &omap2_clksel_recalc,
728 static const struct clksel_rate omap_48m_96md2_rates[] = {
729 { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
733 static const struct clksel_rate omap_48m_alt_rates[] = {
734 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
738 static const struct clksel omap_48m_clksel[] = {
739 { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates },
740 { .parent = &sys_altclk, .rates = omap_48m_alt_rates },
744 static struct clk omap_48m_fck = {
745 .name = "omap_48m_fck",
746 .init = &omap2_init_clksel_parent,
747 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
748 .clksel_mask = OMAP3430_SOURCE_48M,
749 .clksel = omap_48m_clksel,
750 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
751 PARENT_CONTROLS_CLOCK,
752 .recalc = &omap2_clksel_recalc,
755 static struct clk omap_12m_fck = {
756 .name = "omap_12m_fck",
757 .parent = &omap_48m_fck,
759 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
760 PARENT_CONTROLS_CLOCK,
761 .recalc = &omap2_fixed_divisor_recalc,
764 /* This virstual clock is the source for dpll4_m4x2_ck */
765 static struct clk dpll4_m4_ck = {
766 .name = "dpll4_m4_ck",
768 .init = &omap2_init_clksel_parent,
769 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL),
770 .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK,
771 .clksel = div16_dpll4_clksel,
772 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
773 PARENT_CONTROLS_CLOCK,
774 .recalc = &omap2_clksel_recalc,
777 /* The PWRDN bit is apparently only available on 3430ES2 and above */
778 static struct clk dpll4_m4x2_ck = {
779 .name = "dpll4_m4x2_ck",
780 .parent = &dpll4_m4_ck,
781 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
782 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
783 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
784 .recalc = &omap3_clkoutx2_recalc,
787 /* This virtual clock is the source for dpll4_m5x2_ck */
788 static struct clk dpll4_m5_ck = {
789 .name = "dpll4_m5_ck",
791 .init = &omap2_init_clksel_parent,
792 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL),
793 .clksel_mask = OMAP3430_CLKSEL_CAM_MASK,
794 .clksel = div16_dpll4_clksel,
795 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
796 PARENT_CONTROLS_CLOCK,
797 .recalc = &omap2_clksel_recalc,
800 /* The PWRDN bit is apparently only available on 3430ES2 and above */
801 static struct clk dpll4_m5x2_ck = {
802 .name = "dpll4_m5x2_ck",
803 .parent = &dpll4_m5_ck,
804 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
805 .enable_bit = OMAP3430_PWRDN_CAM_SHIFT,
806 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
807 .recalc = &omap3_clkoutx2_recalc,
810 /* This virtual clock is the source for dpll4_m6x2_ck */
811 static struct clk dpll4_m6_ck = {
812 .name = "dpll4_m6_ck",
814 .init = &omap2_init_clksel_parent,
815 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
816 .clksel_mask = OMAP3430_DIV_DPLL4_MASK,
817 .clksel = div16_dpll4_clksel,
818 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
819 PARENT_CONTROLS_CLOCK,
820 .recalc = &omap2_clksel_recalc,
823 /* The PWRDN bit is apparently only available on 3430ES2 and above */
824 static struct clk dpll4_m6x2_ck = {
825 .name = "dpll4_m6x2_ck",
826 .parent = &dpll4_m6_ck,
827 .init = &omap2_init_clksel_parent,
828 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
829 .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT,
830 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE,
831 .recalc = &omap3_clkoutx2_recalc,
834 static struct clk emu_per_alwon_ck = {
835 .name = "emu_per_alwon_ck",
836 .parent = &dpll4_m6x2_ck,
837 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
838 PARENT_CONTROLS_CLOCK,
839 .recalc = &followparent_recalc,
843 /* Supplies 120MHz clock, USIM source clock */
846 static const struct dpll_data dpll5_dd = {
847 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
848 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
849 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
850 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
851 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
852 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
853 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
854 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
855 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
856 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
857 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
858 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
859 .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
862 static struct clk dpll5_ck = {
865 .dpll_data = &dpll5_dd,
866 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
867 .enable = &omap3_noncore_dpll_enable,
868 .disable = &omap3_noncore_dpll_disable,
869 .recalc = &omap3_dpll_recalc,
872 static const struct clksel div16_dpll5_clksel[] = {
873 { .parent = &dpll5_ck, .rates = div16_dpll_rates },
877 static struct clk dpll5_m2_ck = {
878 .name = "dpll5_m2_ck",
880 .init = &omap2_init_clksel_parent,
881 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5),
882 .clksel_mask = OMAP3430ES2_DIV_120M_MASK,
883 .clksel = div16_dpll5_clksel,
884 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
885 PARENT_CONTROLS_CLOCK,
886 .recalc = &omap2_clksel_recalc,
889 static const struct clksel omap_120m_fck_clksel[] = {
890 { .parent = &sys_ck, .rates = dpll_bypass_rates },
891 { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates },
895 static struct clk omap_120m_fck = {
896 .name = "omap_120m_fck",
897 .parent = &dpll5_m2_ck,
898 .init = &omap2_init_clksel_parent,
899 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
900 .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK,
901 .clksel = omap_120m_fck_clksel,
902 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES |
903 PARENT_CONTROLS_CLOCK,
904 .recalc = &omap2_clksel_recalc,
907 /* CM EXTERNAL CLOCK OUTPUTS */
909 static const struct clksel_rate clkout2_src_core_rates[] = {
910 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
914 static const struct clksel_rate clkout2_src_sys_rates[] = {
915 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
919 static const struct clksel_rate clkout2_src_96m_rates[] = {
920 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
924 static const struct clksel_rate clkout2_src_54m_rates[] = {
925 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
929 static const struct clksel clkout2_src_clksel[] = {
930 { .parent = &core_ck, .rates = clkout2_src_core_rates },
931 { .parent = &sys_ck, .rates = clkout2_src_sys_rates },
932 { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates },
933 { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates },
937 static struct clk clkout2_src_ck = {
938 .name = "clkout2_src_ck",
939 .init = &omap2_init_clksel_parent,
940 .enable_reg = OMAP3430_CM_CLKOUT_CTRL,
941 .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT,
942 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
943 .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK,
944 .clksel = clkout2_src_clksel,
945 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
946 .recalc = &omap2_clksel_recalc,
949 static const struct clksel_rate sys_clkout2_rates[] = {
950 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
951 { .div = 2, .val = 1, .flags = RATE_IN_343X },
952 { .div = 4, .val = 2, .flags = RATE_IN_343X },
953 { .div = 8, .val = 3, .flags = RATE_IN_343X },
954 { .div = 16, .val = 4, .flags = RATE_IN_343X },
958 static const struct clksel sys_clkout2_clksel[] = {
959 { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates },
963 static struct clk sys_clkout2 = {
964 .name = "sys_clkout2",
965 .init = &omap2_init_clksel_parent,
966 .clksel_reg = OMAP3430_CM_CLKOUT_CTRL,
967 .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK,
968 .clksel = sys_clkout2_clksel,
969 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
970 .recalc = &omap2_clksel_recalc,
973 /* CM OUTPUT CLOCKS */
975 static struct clk corex2_fck = {
976 .name = "corex2_fck",
977 .parent = &dpll3_m2x2_ck,
978 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
979 PARENT_CONTROLS_CLOCK,
980 .recalc = &followparent_recalc,
983 /* DPLL power domain clock controls */
985 static const struct clksel div2_core_clksel[] = {
986 { .parent = &core_ck, .rates = div2_rates },
991 * REVISIT: Are these in DPLL power domain or CM power domain? docs
992 * may be inconsistent here?
994 static struct clk dpll1_fck = {
997 .init = &omap2_init_clksel_parent,
998 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
999 .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK,
1000 .clksel = div2_core_clksel,
1001 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1002 PARENT_CONTROLS_CLOCK,
1003 .recalc = &omap2_clksel_recalc,
1008 * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck
1009 * derives from the high-frequency bypass clock originating from DPLL3,
1010 * called 'dpll1_fck'
1012 static const struct clksel mpu_clksel[] = {
1013 { .parent = &dpll1_fck, .rates = dpll_bypass_rates },
1014 { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates },
1018 static struct clk mpu_ck = {
1020 .parent = &dpll1_x2m2_ck,
1021 .init = &omap2_init_clksel_parent,
1022 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1023 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1024 .clksel = mpu_clksel,
1025 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1026 PARENT_CONTROLS_CLOCK,
1027 .recalc = &omap2_clksel_recalc,
1030 /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */
1031 static const struct clksel_rate arm_fck_rates[] = {
1032 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1033 { .div = 2, .val = 1, .flags = RATE_IN_343X },
1037 static const struct clksel arm_fck_clksel[] = {
1038 { .parent = &mpu_ck, .rates = arm_fck_rates },
1042 static struct clk arm_fck = {
1045 .init = &omap2_init_clksel_parent,
1046 .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
1047 .clksel_mask = OMAP3430_ST_MPU_CLK_MASK,
1048 .clksel = arm_fck_clksel,
1049 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1050 PARENT_CONTROLS_CLOCK,
1051 .recalc = &omap2_clksel_recalc,
1055 * REVISIT: This clock is never specifically defined in the 3430 TRM,
1056 * although it is referenced - so this is a guess
1058 static struct clk emu_mpu_alwon_ck = {
1059 .name = "emu_mpu_alwon_ck",
1061 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1062 PARENT_CONTROLS_CLOCK,
1063 .recalc = &followparent_recalc,
1066 static struct clk dpll2_fck = {
1067 .name = "dpll2_fck",
1069 .init = &omap2_init_clksel_parent,
1070 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
1071 .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK,
1072 .clksel = div2_core_clksel,
1073 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1074 PARENT_CONTROLS_CLOCK,
1075 .recalc = &omap2_clksel_recalc,
1080 * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck
1081 * derives from the high-frequency bypass clock originating from DPLL3,
1082 * called 'dpll2_fck'
1085 static const struct clksel iva2_clksel[] = {
1086 { .parent = &dpll2_fck, .rates = dpll_bypass_rates },
1087 { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates },
1091 static struct clk iva2_ck = {
1093 .parent = &dpll2_m2_ck,
1094 .init = &omap2_init_clksel_parent,
1095 .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN),
1096 .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
1097 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD,
1098 OMAP3430_CM_IDLEST_PLL),
1099 .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK,
1100 .clksel = iva2_clksel,
1101 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1102 .recalc = &omap2_clksel_recalc,
1105 /* Common interface clocks */
1107 static struct clk l3_ick = {
1110 .init = &omap2_init_clksel_parent,
1111 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1112 .clksel_mask = OMAP3430_CLKSEL_L3_MASK,
1113 .clksel = div2_core_clksel,
1114 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1115 PARENT_CONTROLS_CLOCK,
1116 .recalc = &omap2_clksel_recalc,
1119 static const struct clksel div2_l3_clksel[] = {
1120 { .parent = &l3_ick, .rates = div2_rates },
1124 static struct clk l4_ick = {
1127 .init = &omap2_init_clksel_parent,
1128 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1129 .clksel_mask = OMAP3430_CLKSEL_L4_MASK,
1130 .clksel = div2_l3_clksel,
1131 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1132 PARENT_CONTROLS_CLOCK,
1133 .recalc = &omap2_clksel_recalc,
1137 static const struct clksel div2_l4_clksel[] = {
1138 { .parent = &l4_ick, .rates = div2_rates },
1142 static struct clk rm_ick = {
1145 .init = &omap2_init_clksel_parent,
1146 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
1147 .clksel_mask = OMAP3430_CLKSEL_RM_MASK,
1148 .clksel = div2_l4_clksel,
1149 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1150 .recalc = &omap2_clksel_recalc,
1153 /* GFX power domain */
1155 /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
1157 static const struct clksel gfx_l3_clksel[] = {
1158 { .parent = &l3_ick, .rates = gfx_l3_rates },
1162 static struct clk gfx_l3_fck = {
1163 .name = "gfx_l3_fck",
1165 .init = &omap2_init_clksel_parent,
1166 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1167 .enable_bit = OMAP_EN_GFX_SHIFT,
1168 .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
1169 .clksel_mask = OMAP_CLKSEL_GFX_MASK,
1170 .clksel = gfx_l3_clksel,
1171 .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
1172 .recalc = &omap2_clksel_recalc,
1175 static struct clk gfx_l3_ick = {
1176 .name = "gfx_l3_ick",
1178 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
1179 .enable_bit = OMAP_EN_GFX_SHIFT,
1180 .flags = CLOCK_IN_OMAP3430ES1,
1181 .recalc = &followparent_recalc,
1184 static struct clk gfx_cg1_ck = {
1185 .name = "gfx_cg1_ck",
1186 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1187 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1188 .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
1189 .flags = CLOCK_IN_OMAP3430ES1,
1190 .recalc = &followparent_recalc,
1193 static struct clk gfx_cg2_ck = {
1194 .name = "gfx_cg2_ck",
1195 .parent = &gfx_l3_fck, /* REVISIT: correct? */
1196 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
1197 .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
1198 .flags = CLOCK_IN_OMAP3430ES1,
1199 .recalc = &followparent_recalc,
1202 /* SGX power domain - 3430ES2 only */
1204 static const struct clksel_rate sgx_core_rates[] = {
1205 { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1206 { .div = 4, .val = 1, .flags = RATE_IN_343X },
1207 { .div = 6, .val = 2, .flags = RATE_IN_343X },
1211 static const struct clksel_rate sgx_96m_rates[] = {
1212 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
1216 static const struct clksel sgx_clksel[] = {
1217 { .parent = &core_ck, .rates = sgx_core_rates },
1218 { .parent = &cm_96m_fck, .rates = sgx_96m_rates },
1222 static struct clk sgx_fck = {
1224 .init = &omap2_init_clksel_parent,
1225 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN),
1226 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1227 .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL),
1228 .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK,
1229 .clksel = sgx_clksel,
1230 .flags = CLOCK_IN_OMAP3430ES2,
1231 .recalc = &omap2_clksel_recalc,
1234 static struct clk sgx_ick = {
1237 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN),
1238 .enable_bit = OMAP3430ES2_EN_SGX_SHIFT,
1239 .flags = CLOCK_IN_OMAP3430ES2,
1240 .recalc = &followparent_recalc,
1243 /* CORE power domain */
1245 static struct clk d2d_26m_fck = {
1246 .name = "d2d_26m_fck",
1248 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1249 .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
1250 .flags = CLOCK_IN_OMAP3430ES1,
1251 .recalc = &followparent_recalc,
1254 static const struct clksel omap343x_gpt_clksel[] = {
1255 { .parent = &omap_32k_fck, .rates = gpt_32k_rates },
1256 { .parent = &sys_ck, .rates = gpt_sys_rates },
1260 static struct clk gpt10_fck = {
1261 .name = "gpt10_fck",
1263 .init = &omap2_init_clksel_parent,
1264 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1265 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1266 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1267 .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK,
1268 .clksel = omap343x_gpt_clksel,
1269 .flags = CLOCK_IN_OMAP343X,
1270 .recalc = &omap2_clksel_recalc,
1273 static struct clk gpt11_fck = {
1274 .name = "gpt11_fck",
1276 .init = &omap2_init_clksel_parent,
1277 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1278 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1279 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1280 .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK,
1281 .clksel = omap343x_gpt_clksel,
1282 .flags = CLOCK_IN_OMAP343X,
1283 .recalc = &omap2_clksel_recalc,
1286 static struct clk cpefuse_fck = {
1287 .name = "cpefuse_fck",
1289 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1290 .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT,
1291 .flags = CLOCK_IN_OMAP3430ES2,
1292 .recalc = &followparent_recalc,
1295 static struct clk ts_fck = {
1297 .parent = &omap_32k_fck,
1298 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1299 .enable_bit = OMAP3430ES2_EN_TS_SHIFT,
1300 .flags = CLOCK_IN_OMAP3430ES2,
1301 .recalc = &followparent_recalc,
1304 static struct clk usbtll_fck = {
1305 .name = "usbtll_fck",
1306 .parent = &omap_120m_fck,
1307 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3),
1308 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1309 .flags = CLOCK_IN_OMAP3430ES2,
1310 .recalc = &followparent_recalc,
1313 /* CORE 96M FCLK-derived clocks */
1315 static struct clk core_96m_fck = {
1316 .name = "core_96m_fck",
1317 .parent = &omap_96m_fck,
1318 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1319 PARENT_CONTROLS_CLOCK,
1320 .recalc = &followparent_recalc,
1323 static struct clk mmchs3_fck = {
1324 .name = "mmchs_fck",
1326 .parent = &core_96m_fck,
1327 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1328 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1329 .flags = CLOCK_IN_OMAP3430ES2,
1330 .recalc = &followparent_recalc,
1333 static struct clk mmchs2_fck = {
1334 .name = "mmchs_fck",
1336 .parent = &core_96m_fck,
1337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1338 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1339 .flags = CLOCK_IN_OMAP343X,
1340 .recalc = &followparent_recalc,
1343 static struct clk mspro_fck = {
1344 .name = "mspro_fck",
1345 .parent = &core_96m_fck,
1346 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1347 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1348 .flags = CLOCK_IN_OMAP343X,
1349 .recalc = &followparent_recalc,
1352 static struct clk mmchs1_fck = {
1353 .name = "mmchs_fck",
1355 .parent = &core_96m_fck,
1356 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1357 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1358 .flags = CLOCK_IN_OMAP343X,
1359 .recalc = &followparent_recalc,
1362 static struct clk i2c3_fck = {
1365 .parent = &core_96m_fck,
1366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1367 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1368 .flags = CLOCK_IN_OMAP343X,
1369 .recalc = &followparent_recalc,
1372 static struct clk i2c2_fck = {
1375 .parent = &core_96m_fck,
1376 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1377 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1378 .flags = CLOCK_IN_OMAP343X,
1379 .recalc = &followparent_recalc,
1382 static struct clk i2c1_fck = {
1385 .parent = &core_96m_fck,
1386 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1387 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1388 .flags = CLOCK_IN_OMAP343X,
1389 .recalc = &followparent_recalc,
1393 * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck;
1394 * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck.
1396 static const struct clksel_rate common_mcbsp_96m_rates[] = {
1397 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
1401 static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1402 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1406 static const struct clksel mcbsp_15_clksel[] = {
1407 { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates },
1408 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1412 static struct clk mcbsp5_fck = {
1413 .name = "mcbsp_fck",
1415 .init = &omap2_init_clksel_parent,
1416 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1417 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1418 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
1419 .clksel_mask = OMAP2_MCBSP5_CLKS_MASK,
1420 .clksel = mcbsp_15_clksel,
1421 .flags = CLOCK_IN_OMAP343X,
1422 .recalc = &omap2_clksel_recalc,
1425 static struct clk mcbsp1_fck = {
1426 .name = "mcbsp_fck",
1428 .init = &omap2_init_clksel_parent,
1429 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1430 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1431 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1432 .clksel_mask = OMAP2_MCBSP1_CLKS_MASK,
1433 .clksel = mcbsp_15_clksel,
1434 .flags = CLOCK_IN_OMAP343X,
1435 .recalc = &omap2_clksel_recalc,
1438 /* CORE_48M_FCK-derived clocks */
1440 static struct clk core_48m_fck = {
1441 .name = "core_48m_fck",
1442 .parent = &omap_48m_fck,
1443 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1444 PARENT_CONTROLS_CLOCK,
1445 .recalc = &followparent_recalc,
1448 static struct clk mcspi4_fck = {
1449 .name = "mcspi_fck",
1451 .parent = &core_48m_fck,
1452 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1453 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1454 .flags = CLOCK_IN_OMAP343X,
1455 .recalc = &followparent_recalc,
1458 static struct clk mcspi3_fck = {
1459 .name = "mcspi_fck",
1461 .parent = &core_48m_fck,
1462 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1463 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1464 .flags = CLOCK_IN_OMAP343X,
1465 .recalc = &followparent_recalc,
1468 static struct clk mcspi2_fck = {
1469 .name = "mcspi_fck",
1471 .parent = &core_48m_fck,
1472 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1473 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1474 .flags = CLOCK_IN_OMAP343X,
1475 .recalc = &followparent_recalc,
1478 static struct clk mcspi1_fck = {
1479 .name = "mcspi_fck",
1481 .parent = &core_48m_fck,
1482 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1483 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1484 .flags = CLOCK_IN_OMAP343X,
1485 .recalc = &followparent_recalc,
1488 static struct clk uart2_fck = {
1489 .name = "uart2_fck",
1490 .parent = &core_48m_fck,
1491 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1492 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1493 .flags = CLOCK_IN_OMAP343X,
1494 .recalc = &followparent_recalc,
1497 static struct clk uart1_fck = {
1498 .name = "uart1_fck",
1499 .parent = &core_48m_fck,
1500 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1501 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1502 .flags = CLOCK_IN_OMAP343X,
1503 .recalc = &followparent_recalc,
1506 static struct clk fshostusb_fck = {
1507 .name = "fshostusb_fck",
1508 .parent = &core_48m_fck,
1509 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1510 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1511 .flags = CLOCK_IN_OMAP3430ES1,
1512 .recalc = &followparent_recalc,
1515 /* CORE_12M_FCK based clocks */
1517 static struct clk core_12m_fck = {
1518 .name = "core_12m_fck",
1519 .parent = &omap_12m_fck,
1520 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1521 PARENT_CONTROLS_CLOCK,
1522 .recalc = &followparent_recalc,
1525 static struct clk hdq_fck = {
1527 .parent = &core_12m_fck,
1528 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1529 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1530 .flags = CLOCK_IN_OMAP343X,
1531 .recalc = &followparent_recalc,
1534 /* DPLL3-derived clock */
1536 static const struct clksel_rate ssi_ssr_corex2_rates[] = {
1537 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
1538 { .div = 2, .val = 2, .flags = RATE_IN_343X },
1539 { .div = 3, .val = 3, .flags = RATE_IN_343X },
1540 { .div = 4, .val = 4, .flags = RATE_IN_343X },
1541 { .div = 6, .val = 6, .flags = RATE_IN_343X },
1542 { .div = 8, .val = 8, .flags = RATE_IN_343X },
1546 static const struct clksel ssi_ssr_clksel[] = {
1547 { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates },
1551 static struct clk ssi_ssr_fck = {
1552 .name = "ssi_ssr_fck",
1553 .init = &omap2_init_clksel_parent,
1554 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1555 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1556 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1557 .clksel_mask = OMAP3430_CLKSEL_SSI_MASK,
1558 .clksel = ssi_ssr_clksel,
1559 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
1560 .recalc = &omap2_clksel_recalc,
1563 static struct clk ssi_sst_fck = {
1564 .name = "ssi_sst_fck",
1565 .parent = &ssi_ssr_fck,
1567 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK,
1568 .recalc = &omap2_fixed_divisor_recalc,
1573 /* CORE_L3_ICK based clocks */
1575 static struct clk core_l3_ick = {
1576 .name = "core_l3_ick",
1578 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1579 PARENT_CONTROLS_CLOCK,
1580 .recalc = &followparent_recalc,
1583 static struct clk hsotgusb_ick = {
1584 .name = "hsotgusb_ick",
1585 .parent = &core_l3_ick,
1586 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1587 .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1588 .flags = CLOCK_IN_OMAP343X,
1589 .recalc = &followparent_recalc,
1592 static struct clk sdrc_ick = {
1594 .parent = &core_l3_ick,
1595 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1596 .enable_bit = OMAP3430_EN_SDRC_SHIFT,
1597 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1598 .recalc = &followparent_recalc,
1601 static struct clk gpmc_fck = {
1603 .parent = &core_l3_ick,
1604 .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK |
1606 .recalc = &followparent_recalc,
1609 /* SECURITY_L3_ICK based clocks */
1611 static struct clk security_l3_ick = {
1612 .name = "security_l3_ick",
1614 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1615 PARENT_CONTROLS_CLOCK,
1616 .recalc = &followparent_recalc,
1619 static struct clk pka_ick = {
1621 .parent = &security_l3_ick,
1622 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1623 .enable_bit = OMAP3430_EN_PKA_SHIFT,
1624 .flags = CLOCK_IN_OMAP343X,
1625 .recalc = &followparent_recalc,
1628 /* CORE_L4_ICK based clocks */
1630 static struct clk core_l4_ick = {
1631 .name = "core_l4_ick",
1633 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1634 PARENT_CONTROLS_CLOCK,
1635 .recalc = &followparent_recalc,
1638 static struct clk usbtll_ick = {
1639 .name = "usbtll_ick",
1640 .parent = &core_l4_ick,
1641 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1642 .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1643 .flags = CLOCK_IN_OMAP3430ES2,
1644 .recalc = &followparent_recalc,
1647 static struct clk mmchs3_ick = {
1648 .name = "mmchs_ick",
1650 .parent = &core_l4_ick,
1651 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1652 .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT,
1653 .flags = CLOCK_IN_OMAP3430ES2,
1654 .recalc = &followparent_recalc,
1657 /* Intersystem Communication Registers - chassis mode only */
1658 static struct clk icr_ick = {
1660 .parent = &core_l4_ick,
1661 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1662 .enable_bit = OMAP3430_EN_ICR_SHIFT,
1663 .flags = CLOCK_IN_OMAP343X,
1664 .recalc = &followparent_recalc,
1667 static struct clk aes2_ick = {
1669 .parent = &core_l4_ick,
1670 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1671 .enable_bit = OMAP3430_EN_AES2_SHIFT,
1672 .flags = CLOCK_IN_OMAP343X,
1673 .recalc = &followparent_recalc,
1676 static struct clk sha12_ick = {
1677 .name = "sha12_ick",
1678 .parent = &core_l4_ick,
1679 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1680 .enable_bit = OMAP3430_EN_SHA12_SHIFT,
1681 .flags = CLOCK_IN_OMAP343X,
1682 .recalc = &followparent_recalc,
1685 static struct clk des2_ick = {
1687 .parent = &core_l4_ick,
1688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1689 .enable_bit = OMAP3430_EN_DES2_SHIFT,
1690 .flags = CLOCK_IN_OMAP343X,
1691 .recalc = &followparent_recalc,
1694 static struct clk mmchs2_ick = {
1695 .name = "mmchs_ick",
1697 .parent = &core_l4_ick,
1698 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1699 .enable_bit = OMAP3430_EN_MMC2_SHIFT,
1700 .flags = CLOCK_IN_OMAP343X,
1701 .recalc = &followparent_recalc,
1704 static struct clk mmchs1_ick = {
1705 .name = "mmchs_ick",
1707 .parent = &core_l4_ick,
1708 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1709 .enable_bit = OMAP3430_EN_MMC1_SHIFT,
1710 .flags = CLOCK_IN_OMAP343X,
1711 .recalc = &followparent_recalc,
1714 static struct clk mspro_ick = {
1715 .name = "mspro_ick",
1716 .parent = &core_l4_ick,
1717 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1718 .enable_bit = OMAP3430_EN_MSPRO_SHIFT,
1719 .flags = CLOCK_IN_OMAP343X,
1720 .recalc = &followparent_recalc,
1723 static struct clk hdq_ick = {
1725 .parent = &core_l4_ick,
1726 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1727 .enable_bit = OMAP3430_EN_HDQ_SHIFT,
1728 .flags = CLOCK_IN_OMAP343X,
1729 .recalc = &followparent_recalc,
1732 static struct clk mcspi4_ick = {
1733 .name = "mcspi_ick",
1735 .parent = &core_l4_ick,
1736 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1737 .enable_bit = OMAP3430_EN_MCSPI4_SHIFT,
1738 .flags = CLOCK_IN_OMAP343X,
1739 .recalc = &followparent_recalc,
1742 static struct clk mcspi3_ick = {
1743 .name = "mcspi_ick",
1745 .parent = &core_l4_ick,
1746 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1747 .enable_bit = OMAP3430_EN_MCSPI3_SHIFT,
1748 .flags = CLOCK_IN_OMAP343X,
1749 .recalc = &followparent_recalc,
1752 static struct clk mcspi2_ick = {
1753 .name = "mcspi_ick",
1755 .parent = &core_l4_ick,
1756 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1757 .enable_bit = OMAP3430_EN_MCSPI2_SHIFT,
1758 .flags = CLOCK_IN_OMAP343X,
1759 .recalc = &followparent_recalc,
1762 static struct clk mcspi1_ick = {
1763 .name = "mcspi_ick",
1765 .parent = &core_l4_ick,
1766 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1767 .enable_bit = OMAP3430_EN_MCSPI1_SHIFT,
1768 .flags = CLOCK_IN_OMAP343X,
1769 .recalc = &followparent_recalc,
1772 static struct clk i2c3_ick = {
1775 .parent = &core_l4_ick,
1776 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1777 .enable_bit = OMAP3430_EN_I2C3_SHIFT,
1778 .flags = CLOCK_IN_OMAP343X,
1779 .recalc = &followparent_recalc,
1782 static struct clk i2c2_ick = {
1785 .parent = &core_l4_ick,
1786 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1787 .enable_bit = OMAP3430_EN_I2C2_SHIFT,
1788 .flags = CLOCK_IN_OMAP343X,
1789 .recalc = &followparent_recalc,
1792 static struct clk i2c1_ick = {
1795 .parent = &core_l4_ick,
1796 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1797 .enable_bit = OMAP3430_EN_I2C1_SHIFT,
1798 .flags = CLOCK_IN_OMAP343X,
1799 .recalc = &followparent_recalc,
1802 static struct clk uart2_ick = {
1803 .name = "uart2_ick",
1804 .parent = &core_l4_ick,
1805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1806 .enable_bit = OMAP3430_EN_UART2_SHIFT,
1807 .flags = CLOCK_IN_OMAP343X,
1808 .recalc = &followparent_recalc,
1811 static struct clk uart1_ick = {
1812 .name = "uart1_ick",
1813 .parent = &core_l4_ick,
1814 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1815 .enable_bit = OMAP3430_EN_UART1_SHIFT,
1816 .flags = CLOCK_IN_OMAP343X,
1817 .recalc = &followparent_recalc,
1820 static struct clk gpt11_ick = {
1821 .name = "gpt11_ick",
1822 .parent = &core_l4_ick,
1823 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1824 .enable_bit = OMAP3430_EN_GPT11_SHIFT,
1825 .flags = CLOCK_IN_OMAP343X,
1826 .recalc = &followparent_recalc,
1829 static struct clk gpt10_ick = {
1830 .name = "gpt10_ick",
1831 .parent = &core_l4_ick,
1832 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1833 .enable_bit = OMAP3430_EN_GPT10_SHIFT,
1834 .flags = CLOCK_IN_OMAP343X,
1835 .recalc = &followparent_recalc,
1838 static struct clk mcbsp5_ick = {
1839 .name = "mcbsp_ick",
1841 .parent = &core_l4_ick,
1842 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1843 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
1844 .flags = CLOCK_IN_OMAP343X,
1845 .recalc = &followparent_recalc,
1848 static struct clk mcbsp1_ick = {
1849 .name = "mcbsp_ick",
1851 .parent = &core_l4_ick,
1852 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1853 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
1854 .flags = CLOCK_IN_OMAP343X,
1855 .recalc = &followparent_recalc,
1858 static struct clk fac_ick = {
1860 .parent = &core_l4_ick,
1861 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1862 .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
1863 .flags = CLOCK_IN_OMAP3430ES1,
1864 .recalc = &followparent_recalc,
1867 static struct clk mailboxes_ick = {
1868 .name = "mailboxes_ick",
1869 .parent = &core_l4_ick,
1870 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1871 .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1872 .flags = CLOCK_IN_OMAP343X,
1873 .recalc = &followparent_recalc,
1876 static struct clk omapctrl_ick = {
1877 .name = "omapctrl_ick",
1878 .parent = &core_l4_ick,
1879 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1880 .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT,
1881 .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT,
1882 .recalc = &followparent_recalc,
1885 /* SSI_L4_ICK based clocks */
1887 static struct clk ssi_l4_ick = {
1888 .name = "ssi_l4_ick",
1890 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1891 PARENT_CONTROLS_CLOCK,
1892 .recalc = &followparent_recalc,
1895 static struct clk ssi_ick = {
1897 .parent = &ssi_l4_ick,
1898 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1899 .enable_bit = OMAP3430_EN_SSI_SHIFT,
1900 .flags = CLOCK_IN_OMAP343X,
1901 .recalc = &followparent_recalc,
1904 /* REVISIT: Technically the TRM claims that this is CORE_CLK based,
1905 * but l4_ick makes more sense to me */
1907 static const struct clksel usb_l4_clksel[] = {
1908 { .parent = &l4_ick, .rates = div2_rates },
1912 static struct clk usb_l4_ick = {
1913 .name = "usb_l4_ick",
1915 .init = &omap2_init_clksel_parent,
1916 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1917 .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
1918 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1919 .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
1920 .clksel = usb_l4_clksel,
1921 .flags = CLOCK_IN_OMAP3430ES1,
1922 .recalc = &omap2_clksel_recalc,
1925 /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */
1927 /* SECURITY_L4_ICK2 based clocks */
1929 static struct clk security_l4_ick2 = {
1930 .name = "security_l4_ick2",
1932 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
1933 PARENT_CONTROLS_CLOCK,
1934 .recalc = &followparent_recalc,
1937 static struct clk aes1_ick = {
1939 .parent = &security_l4_ick2,
1940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1941 .enable_bit = OMAP3430_EN_AES1_SHIFT,
1942 .flags = CLOCK_IN_OMAP343X,
1943 .recalc = &followparent_recalc,
1946 static struct clk rng_ick = {
1948 .parent = &security_l4_ick2,
1949 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1950 .enable_bit = OMAP3430_EN_RNG_SHIFT,
1951 .flags = CLOCK_IN_OMAP343X,
1952 .recalc = &followparent_recalc,
1955 static struct clk sha11_ick = {
1956 .name = "sha11_ick",
1957 .parent = &security_l4_ick2,
1958 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1959 .enable_bit = OMAP3430_EN_SHA11_SHIFT,
1960 .flags = CLOCK_IN_OMAP343X,
1961 .recalc = &followparent_recalc,
1964 static struct clk des1_ick = {
1966 .parent = &security_l4_ick2,
1967 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1968 .enable_bit = OMAP3430_EN_DES1_SHIFT,
1969 .flags = CLOCK_IN_OMAP343X,
1970 .recalc = &followparent_recalc,
1974 static const struct clksel dss1_alwon_fck_clksel[] = {
1975 { .parent = &sys_ck, .rates = dpll_bypass_rates },
1976 { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates },
1980 static struct clk dss1_alwon_fck = {
1981 .name = "dss1_alwon_fck",
1982 .parent = &dpll4_m4x2_ck,
1983 .init = &omap2_init_clksel_parent,
1984 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1985 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1986 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1987 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
1988 .clksel = dss1_alwon_fck_clksel,
1989 .flags = CLOCK_IN_OMAP343X,
1990 .recalc = &omap2_clksel_recalc,
1993 static struct clk dss_tv_fck = {
1994 .name = "dss_tv_fck",
1995 .parent = &omap_54m_fck,
1996 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1997 .enable_bit = OMAP3430_EN_TV_SHIFT,
1998 .flags = CLOCK_IN_OMAP343X,
1999 .recalc = &followparent_recalc,
2002 static struct clk dss_96m_fck = {
2003 .name = "dss_96m_fck",
2004 .parent = &omap_96m_fck,
2005 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2006 .enable_bit = OMAP3430_EN_TV_SHIFT,
2007 .flags = CLOCK_IN_OMAP343X,
2008 .recalc = &followparent_recalc,
2011 static struct clk dss2_alwon_fck = {
2012 .name = "dss2_alwon_fck",
2014 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
2015 .enable_bit = OMAP3430_EN_DSS2_SHIFT,
2016 .flags = CLOCK_IN_OMAP343X,
2017 .recalc = &followparent_recalc,
2020 static struct clk dss_ick = {
2021 /* Handles both L3 and L4 clocks */
2024 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
2025 .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
2026 .flags = CLOCK_IN_OMAP343X,
2027 .recalc = &followparent_recalc,
2032 static const struct clksel cam_mclk_clksel[] = {
2033 { .parent = &sys_ck, .rates = dpll_bypass_rates },
2034 { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates },
2038 static struct clk cam_mclk = {
2040 .parent = &dpll4_m5x2_ck,
2041 .init = &omap2_init_clksel_parent,
2042 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
2043 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
2044 .clksel = cam_mclk_clksel,
2045 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
2046 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2047 .flags = CLOCK_IN_OMAP343X,
2048 .recalc = &omap2_clksel_recalc,
2051 static struct clk cam_l3_ick = {
2052 .name = "cam_l3_ick",
2054 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2055 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2056 .flags = CLOCK_IN_OMAP343X,
2057 .recalc = &followparent_recalc,
2060 static struct clk cam_l4_ick = {
2061 .name = "cam_l4_ick",
2063 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
2064 .enable_bit = OMAP3430_EN_CAM_SHIFT,
2065 .flags = CLOCK_IN_OMAP343X,
2066 .recalc = &followparent_recalc,
2069 /* USBHOST - 3430ES2 only */
2071 static struct clk usbhost_120m_fck = {
2072 .name = "usbhost_120m_fck",
2073 .parent = &omap_120m_fck,
2074 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2075 .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT,
2076 .flags = CLOCK_IN_OMAP3430ES2,
2077 .recalc = &followparent_recalc,
2080 static struct clk usbhost_48m_fck = {
2081 .name = "usbhost_48m_fck",
2082 .parent = &omap_48m_fck,
2083 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN),
2084 .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
2085 .flags = CLOCK_IN_OMAP3430ES2,
2086 .recalc = &followparent_recalc,
2089 static struct clk usbhost_l3_ick = {
2090 .name = "usbhost_l3_ick",
2092 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2093 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2094 .flags = CLOCK_IN_OMAP3430ES2,
2095 .recalc = &followparent_recalc,
2098 static struct clk usbhost_l4_ick = {
2099 .name = "usbhost_l4_ick",
2101 .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
2102 .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT,
2103 .flags = CLOCK_IN_OMAP3430ES2,
2104 .recalc = &followparent_recalc,
2107 static struct clk usbhost_sar_fck = {
2108 .name = "usbhost_sar_fck",
2109 .parent = &osc_sys_ck,
2110 .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL),
2111 .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT,
2112 .flags = CLOCK_IN_OMAP3430ES2,
2113 .recalc = &followparent_recalc,
2118 static const struct clksel_rate usim_96m_rates[] = {
2119 { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2120 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2121 { .div = 8, .val = 5, .flags = RATE_IN_343X },
2122 { .div = 10, .val = 6, .flags = RATE_IN_343X },
2126 static const struct clksel_rate usim_120m_rates[] = {
2127 { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE },
2128 { .div = 8, .val = 8, .flags = RATE_IN_343X },
2129 { .div = 16, .val = 9, .flags = RATE_IN_343X },
2130 { .div = 20, .val = 10, .flags = RATE_IN_343X },
2134 static const struct clksel usim_clksel[] = {
2135 { .parent = &omap_96m_fck, .rates = usim_96m_rates },
2136 { .parent = &omap_120m_fck, .rates = usim_120m_rates },
2137 { .parent = &sys_ck, .rates = div2_rates },
2142 static struct clk usim_fck = {
2144 .init = &omap2_init_clksel_parent,
2145 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2146 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2147 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2148 .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK,
2149 .clksel = usim_clksel,
2150 .flags = CLOCK_IN_OMAP3430ES2,
2151 .recalc = &omap2_clksel_recalc,
2154 static struct clk gpt1_fck = {
2156 .init = &omap2_init_clksel_parent,
2157 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2158 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2159 .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL),
2160 .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK,
2161 .clksel = omap343x_gpt_clksel,
2162 .flags = CLOCK_IN_OMAP343X,
2163 .recalc = &omap2_clksel_recalc,
2166 static struct clk wkup_32k_fck = {
2167 .name = "wkup_32k_fck",
2168 .parent = &omap_32k_fck,
2169 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2170 .recalc = &followparent_recalc,
2173 static struct clk gpio1_fck = {
2174 .name = "gpio1_fck",
2175 .parent = &wkup_32k_fck,
2176 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2177 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2178 .flags = CLOCK_IN_OMAP343X,
2179 .recalc = &followparent_recalc,
2182 static struct clk wdt2_fck = {
2184 .parent = &wkup_32k_fck,
2185 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2186 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2187 .flags = CLOCK_IN_OMAP343X,
2188 .recalc = &followparent_recalc,
2191 static struct clk wkup_l4_ick = {
2192 .name = "wkup_l4_ick",
2194 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2195 .recalc = &followparent_recalc,
2199 /* Never specifically named in the TRM, so we have to infer a likely name */
2200 static struct clk usim_ick = {
2202 .parent = &wkup_l4_ick,
2203 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2204 .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT,
2205 .flags = CLOCK_IN_OMAP3430ES2,
2206 .recalc = &followparent_recalc,
2209 static struct clk wdt2_ick = {
2211 .parent = &wkup_l4_ick,
2212 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2213 .enable_bit = OMAP3430_EN_WDT2_SHIFT,
2214 .flags = CLOCK_IN_OMAP343X,
2215 .recalc = &followparent_recalc,
2218 static struct clk wdt1_ick = {
2220 .parent = &wkup_l4_ick,
2221 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2222 .enable_bit = OMAP3430_EN_WDT1_SHIFT,
2223 .flags = CLOCK_IN_OMAP343X,
2224 .recalc = &followparent_recalc,
2227 static struct clk gpio1_ick = {
2228 .name = "gpio1_ick",
2229 .parent = &wkup_l4_ick,
2230 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2231 .enable_bit = OMAP3430_EN_GPIO1_SHIFT,
2232 .flags = CLOCK_IN_OMAP343X,
2233 .recalc = &followparent_recalc,
2236 static struct clk omap_32ksync_ick = {
2237 .name = "omap_32ksync_ick",
2238 .parent = &wkup_l4_ick,
2239 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2240 .enable_bit = OMAP3430_EN_32KSYNC_SHIFT,
2241 .flags = CLOCK_IN_OMAP343X,
2242 .recalc = &followparent_recalc,
2245 static struct clk gpt12_ick = {
2246 .name = "gpt12_ick",
2247 .parent = &wkup_l4_ick,
2248 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2249 .enable_bit = OMAP3430_EN_GPT12_SHIFT,
2250 .flags = CLOCK_IN_OMAP343X,
2251 .recalc = &followparent_recalc,
2254 static struct clk gpt1_ick = {
2256 .parent = &wkup_l4_ick,
2257 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
2258 .enable_bit = OMAP3430_EN_GPT1_SHIFT,
2259 .flags = CLOCK_IN_OMAP343X,
2260 .recalc = &followparent_recalc,
2265 /* PER clock domain */
2267 static struct clk per_96m_fck = {
2268 .name = "per_96m_fck",
2269 .parent = &omap_96m_alwon_fck,
2270 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2271 PARENT_CONTROLS_CLOCK,
2272 .recalc = &followparent_recalc,
2275 static struct clk per_48m_fck = {
2276 .name = "per_48m_fck",
2277 .parent = &omap_48m_fck,
2278 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2279 PARENT_CONTROLS_CLOCK,
2280 .recalc = &followparent_recalc,
2283 static struct clk uart3_fck = {
2284 .name = "uart3_fck",
2285 .parent = &per_48m_fck,
2286 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2287 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2288 .flags = CLOCK_IN_OMAP343X,
2289 .recalc = &followparent_recalc,
2292 static struct clk gpt2_fck = {
2294 .init = &omap2_init_clksel_parent,
2295 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2296 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2297 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2298 .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK,
2299 .clksel = omap343x_gpt_clksel,
2300 .flags = CLOCK_IN_OMAP343X,
2301 .recalc = &omap2_clksel_recalc,
2304 static struct clk gpt3_fck = {
2306 .init = &omap2_init_clksel_parent,
2307 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2308 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2309 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2310 .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK,
2311 .clksel = omap343x_gpt_clksel,
2312 .flags = CLOCK_IN_OMAP343X,
2313 .recalc = &omap2_clksel_recalc,
2316 static struct clk gpt4_fck = {
2318 .init = &omap2_init_clksel_parent,
2319 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2320 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2321 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2322 .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK,
2323 .clksel = omap343x_gpt_clksel,
2324 .flags = CLOCK_IN_OMAP343X,
2325 .recalc = &omap2_clksel_recalc,
2328 static struct clk gpt5_fck = {
2330 .init = &omap2_init_clksel_parent,
2331 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2332 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2333 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2334 .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK,
2335 .clksel = omap343x_gpt_clksel,
2336 .flags = CLOCK_IN_OMAP343X,
2337 .recalc = &omap2_clksel_recalc,
2340 static struct clk gpt6_fck = {
2342 .init = &omap2_init_clksel_parent,
2343 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2344 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2345 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2346 .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK,
2347 .clksel = omap343x_gpt_clksel,
2348 .flags = CLOCK_IN_OMAP343X,
2349 .recalc = &omap2_clksel_recalc,
2352 static struct clk gpt7_fck = {
2354 .init = &omap2_init_clksel_parent,
2355 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2356 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2357 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2358 .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK,
2359 .clksel = omap343x_gpt_clksel,
2360 .flags = CLOCK_IN_OMAP343X,
2361 .recalc = &omap2_clksel_recalc,
2364 static struct clk gpt8_fck = {
2366 .init = &omap2_init_clksel_parent,
2367 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2368 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2369 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2370 .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK,
2371 .clksel = omap343x_gpt_clksel,
2372 .flags = CLOCK_IN_OMAP343X,
2373 .recalc = &omap2_clksel_recalc,
2376 static struct clk gpt9_fck = {
2378 .init = &omap2_init_clksel_parent,
2379 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2380 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2381 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL),
2382 .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK,
2383 .clksel = omap343x_gpt_clksel,
2384 .flags = CLOCK_IN_OMAP343X,
2385 .recalc = &omap2_clksel_recalc,
2388 static struct clk per_32k_alwon_fck = {
2389 .name = "per_32k_alwon_fck",
2390 .parent = &omap_32k_fck,
2391 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2392 .recalc = &followparent_recalc,
2395 static struct clk gpio6_fck = {
2396 .name = "gpio6_fck",
2397 .parent = &per_32k_alwon_fck,
2398 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2399 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2400 .flags = CLOCK_IN_OMAP343X,
2401 .recalc = &followparent_recalc,
2404 static struct clk gpio5_fck = {
2405 .name = "gpio5_fck",
2406 .parent = &per_32k_alwon_fck,
2407 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2408 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2409 .flags = CLOCK_IN_OMAP343X,
2410 .recalc = &followparent_recalc,
2413 static struct clk gpio4_fck = {
2414 .name = "gpio4_fck",
2415 .parent = &per_32k_alwon_fck,
2416 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2417 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2418 .flags = CLOCK_IN_OMAP343X,
2419 .recalc = &followparent_recalc,
2422 static struct clk gpio3_fck = {
2423 .name = "gpio3_fck",
2424 .parent = &per_32k_alwon_fck,
2425 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2426 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2427 .flags = CLOCK_IN_OMAP343X,
2428 .recalc = &followparent_recalc,
2431 static struct clk gpio2_fck = {
2432 .name = "gpio2_fck",
2433 .parent = &per_32k_alwon_fck,
2434 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2435 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2436 .flags = CLOCK_IN_OMAP343X,
2437 .recalc = &followparent_recalc,
2440 static struct clk wdt3_fck = {
2442 .parent = &per_32k_alwon_fck,
2443 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2444 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2445 .flags = CLOCK_IN_OMAP343X,
2446 .recalc = &followparent_recalc,
2449 static struct clk per_l4_ick = {
2450 .name = "per_l4_ick",
2452 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
2453 PARENT_CONTROLS_CLOCK,
2454 .recalc = &followparent_recalc,
2457 static struct clk gpio6_ick = {
2458 .name = "gpio6_ick",
2459 .parent = &per_l4_ick,
2460 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2461 .enable_bit = OMAP3430_EN_GPIO6_SHIFT,
2462 .flags = CLOCK_IN_OMAP343X,
2463 .recalc = &followparent_recalc,
2466 static struct clk gpio5_ick = {
2467 .name = "gpio5_ick",
2468 .parent = &per_l4_ick,
2469 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2470 .enable_bit = OMAP3430_EN_GPIO5_SHIFT,
2471 .flags = CLOCK_IN_OMAP343X,
2472 .recalc = &followparent_recalc,
2475 static struct clk gpio4_ick = {
2476 .name = "gpio4_ick",
2477 .parent = &per_l4_ick,
2478 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2479 .enable_bit = OMAP3430_EN_GPIO4_SHIFT,
2480 .flags = CLOCK_IN_OMAP343X,
2481 .recalc = &followparent_recalc,
2484 static struct clk gpio3_ick = {
2485 .name = "gpio3_ick",
2486 .parent = &per_l4_ick,
2487 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2488 .enable_bit = OMAP3430_EN_GPIO3_SHIFT,
2489 .flags = CLOCK_IN_OMAP343X,
2490 .recalc = &followparent_recalc,
2493 static struct clk gpio2_ick = {
2494 .name = "gpio2_ick",
2495 .parent = &per_l4_ick,
2496 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2497 .enable_bit = OMAP3430_EN_GPIO2_SHIFT,
2498 .flags = CLOCK_IN_OMAP343X,
2499 .recalc = &followparent_recalc,
2502 static struct clk wdt3_ick = {
2504 .parent = &per_l4_ick,
2505 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2506 .enable_bit = OMAP3430_EN_WDT3_SHIFT,
2507 .flags = CLOCK_IN_OMAP343X,
2508 .recalc = &followparent_recalc,
2511 static struct clk uart3_ick = {
2512 .name = "uart3_ick",
2513 .parent = &per_l4_ick,
2514 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2515 .enable_bit = OMAP3430_EN_UART3_SHIFT,
2516 .flags = CLOCK_IN_OMAP343X,
2517 .recalc = &followparent_recalc,
2520 static struct clk gpt9_ick = {
2522 .parent = &per_l4_ick,
2523 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2524 .enable_bit = OMAP3430_EN_GPT9_SHIFT,
2525 .flags = CLOCK_IN_OMAP343X,
2526 .recalc = &followparent_recalc,
2529 static struct clk gpt8_ick = {
2531 .parent = &per_l4_ick,
2532 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2533 .enable_bit = OMAP3430_EN_GPT8_SHIFT,
2534 .flags = CLOCK_IN_OMAP343X,
2535 .recalc = &followparent_recalc,
2538 static struct clk gpt7_ick = {
2540 .parent = &per_l4_ick,
2541 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2542 .enable_bit = OMAP3430_EN_GPT7_SHIFT,
2543 .flags = CLOCK_IN_OMAP343X,
2544 .recalc = &followparent_recalc,
2547 static struct clk gpt6_ick = {
2549 .parent = &per_l4_ick,
2550 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2551 .enable_bit = OMAP3430_EN_GPT6_SHIFT,
2552 .flags = CLOCK_IN_OMAP343X,
2553 .recalc = &followparent_recalc,
2556 static struct clk gpt5_ick = {
2558 .parent = &per_l4_ick,
2559 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2560 .enable_bit = OMAP3430_EN_GPT5_SHIFT,
2561 .flags = CLOCK_IN_OMAP343X,
2562 .recalc = &followparent_recalc,
2565 static struct clk gpt4_ick = {
2567 .parent = &per_l4_ick,
2568 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2569 .enable_bit = OMAP3430_EN_GPT4_SHIFT,
2570 .flags = CLOCK_IN_OMAP343X,
2571 .recalc = &followparent_recalc,
2574 static struct clk gpt3_ick = {
2576 .parent = &per_l4_ick,
2577 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2578 .enable_bit = OMAP3430_EN_GPT3_SHIFT,
2579 .flags = CLOCK_IN_OMAP343X,
2580 .recalc = &followparent_recalc,
2583 static struct clk gpt2_ick = {
2585 .parent = &per_l4_ick,
2586 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2587 .enable_bit = OMAP3430_EN_GPT2_SHIFT,
2588 .flags = CLOCK_IN_OMAP343X,
2589 .recalc = &followparent_recalc,
2592 static struct clk mcbsp2_ick = {
2593 .name = "mcbsp_ick",
2595 .parent = &per_l4_ick,
2596 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2597 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2598 .flags = CLOCK_IN_OMAP343X,
2599 .recalc = &followparent_recalc,
2602 static struct clk mcbsp3_ick = {
2603 .name = "mcbsp_ick",
2605 .parent = &per_l4_ick,
2606 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2607 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2608 .flags = CLOCK_IN_OMAP343X,
2609 .recalc = &followparent_recalc,
2612 static struct clk mcbsp4_ick = {
2613 .name = "mcbsp_ick",
2615 .parent = &per_l4_ick,
2616 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2617 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2618 .flags = CLOCK_IN_OMAP343X,
2619 .recalc = &followparent_recalc,
2622 static const struct clksel mcbsp_234_clksel[] = {
2623 { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates },
2624 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
2628 static struct clk mcbsp2_fck = {
2629 .name = "mcbsp_fck",
2631 .init = &omap2_init_clksel_parent,
2632 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2633 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
2634 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
2635 .clksel_mask = OMAP2_MCBSP2_CLKS_MASK,
2636 .clksel = mcbsp_234_clksel,
2637 .flags = CLOCK_IN_OMAP343X,
2638 .recalc = &omap2_clksel_recalc,
2641 static struct clk mcbsp3_fck = {
2642 .name = "mcbsp_fck",
2644 .init = &omap2_init_clksel_parent,
2645 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2646 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
2647 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2648 .clksel_mask = OMAP2_MCBSP3_CLKS_MASK,
2649 .clksel = mcbsp_234_clksel,
2650 .flags = CLOCK_IN_OMAP343X,
2651 .recalc = &omap2_clksel_recalc,
2654 static struct clk mcbsp4_fck = {
2655 .name = "mcbsp_fck",
2657 .init = &omap2_init_clksel_parent,
2658 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2659 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
2660 .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1),
2661 .clksel_mask = OMAP2_MCBSP4_CLKS_MASK,
2662 .clksel = mcbsp_234_clksel,
2663 .flags = CLOCK_IN_OMAP343X,
2664 .recalc = &omap2_clksel_recalc,
2669 /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */
2671 static const struct clksel_rate emu_src_sys_rates[] = {
2672 { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE },
2676 static const struct clksel_rate emu_src_core_rates[] = {
2677 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2681 static const struct clksel_rate emu_src_per_rates[] = {
2682 { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2686 static const struct clksel_rate emu_src_mpu_rates[] = {
2687 { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE },
2691 static const struct clksel emu_src_clksel[] = {
2692 { .parent = &sys_ck, .rates = emu_src_sys_rates },
2693 { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates },
2694 { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates },
2695 { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates },
2700 * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only
2701 * to switch the source of some of the EMU clocks.
2702 * XXX Are there CLKEN bits for these EMU clks?
2704 static struct clk emu_src_ck = {
2705 .name = "emu_src_ck",
2706 .init = &omap2_init_clksel_parent,
2707 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2708 .clksel_mask = OMAP3430_MUX_CTRL_MASK,
2709 .clksel = emu_src_clksel,
2710 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2711 .recalc = &omap2_clksel_recalc,
2714 static const struct clksel_rate pclk_emu_rates[] = {
2715 { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE },
2716 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2717 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2718 { .div = 6, .val = 6, .flags = RATE_IN_343X },
2722 static const struct clksel pclk_emu_clksel[] = {
2723 { .parent = &emu_src_ck, .rates = pclk_emu_rates },
2727 static struct clk pclk_fck = {
2729 .init = &omap2_init_clksel_parent,
2730 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2731 .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK,
2732 .clksel = pclk_emu_clksel,
2733 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2734 .recalc = &omap2_clksel_recalc,
2737 static const struct clksel_rate pclkx2_emu_rates[] = {
2738 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2739 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2740 { .div = 3, .val = 3, .flags = RATE_IN_343X },
2744 static const struct clksel pclkx2_emu_clksel[] = {
2745 { .parent = &emu_src_ck, .rates = pclkx2_emu_rates },
2749 static struct clk pclkx2_fck = {
2750 .name = "pclkx2_fck",
2751 .init = &omap2_init_clksel_parent,
2752 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2753 .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK,
2754 .clksel = pclkx2_emu_clksel,
2755 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2756 .recalc = &omap2_clksel_recalc,
2759 static const struct clksel atclk_emu_clksel[] = {
2760 { .parent = &emu_src_ck, .rates = div2_rates },
2764 static struct clk atclk_fck = {
2765 .name = "atclk_fck",
2766 .init = &omap2_init_clksel_parent,
2767 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2768 .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK,
2769 .clksel = atclk_emu_clksel,
2770 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2771 .recalc = &omap2_clksel_recalc,
2774 static struct clk traceclk_src_fck = {
2775 .name = "traceclk_src_fck",
2776 .init = &omap2_init_clksel_parent,
2777 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2778 .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK,
2779 .clksel = emu_src_clksel,
2780 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
2781 .recalc = &omap2_clksel_recalc,
2784 static const struct clksel_rate traceclk_rates[] = {
2785 { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE },
2786 { .div = 2, .val = 2, .flags = RATE_IN_343X },
2787 { .div = 4, .val = 4, .flags = RATE_IN_343X },
2791 static const struct clksel traceclk_clksel[] = {
2792 { .parent = &traceclk_src_fck, .rates = traceclk_rates },
2796 static struct clk traceclk_fck = {
2797 .name = "traceclk_fck",
2798 .init = &omap2_init_clksel_parent,
2799 .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1),
2800 .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK,
2801 .clksel = traceclk_clksel,
2802 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2803 .recalc = &omap2_clksel_recalc,
2808 /* SmartReflex fclk (VDD1) */
2809 static struct clk sr1_fck = {
2812 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2813 .enable_bit = OMAP3430_EN_SR1_SHIFT,
2814 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2815 .recalc = &followparent_recalc,
2818 /* SmartReflex fclk (VDD2) */
2819 static struct clk sr2_fck = {
2822 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
2823 .enable_bit = OMAP3430_EN_SR2_SHIFT,
2824 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
2825 .recalc = &followparent_recalc,
2828 static struct clk sr_l4_ick = {
2829 .name = "sr_l4_ick",
2831 .flags = CLOCK_IN_OMAP343X,
2832 .recalc = &followparent_recalc,
2835 /* SECURE_32K_FCK clocks */
2837 static struct clk gpt12_fck = {
2838 .name = "gpt12_fck",
2839 .parent = &secure_32k_fck,
2840 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2841 .recalc = &followparent_recalc,
2844 static struct clk wdt1_fck = {
2846 .parent = &secure_32k_fck,
2847 .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED,
2848 .recalc = &followparent_recalc,
2851 static struct clk *onchip_34xx_clks[] __initdata = {
2879 &omap_96m_alwon_fck,