0c6834ae1fc43a8ab20409dccd1bb24d7eeb20fd
[linux-3.10.git] / arch / arm / mach-omap2 / cclock44xx_data.c
1 /*
2  * OMAP4 Clock data
3  *
4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
5  * Copyright (C) 2009-2010 Nokia Corporation
6  *
7  * Paul Walmsley (paul@pwsan.com)
8  * Rajendra Nayak (rnayak@ti.com)
9  * Benoit Cousson (b-cousson@ti.com)
10  * Mike Turquette (mturquette@ti.com)
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  *
16  * XXX Some of the ES1 clocks have been removed/changed; once support
17  * is added for discriminating clocks by ES level, these should be added back
18  * in.
19  *
20  * XXX All of the remaining MODULEMODE clock nodes should be removed
21  * once the drivers are updated to use pm_runtime or to use the appropriate
22  * upstream clock node for rate/parent selection.
23  */
24
25 #include <linux/kernel.h>
26 #include <linux/list.h>
27 #include <linux/clk-private.h>
28 #include <linux/clkdev.h>
29 #include <linux/io.h>
30
31 #include "soc.h"
32 #include "iomap.h"
33 #include "clock.h"
34 #include "clock44xx.h"
35 #include "cm1_44xx.h"
36 #include "cm2_44xx.h"
37 #include "cm-regbits-44xx.h"
38 #include "prm44xx.h"
39 #include "prm-regbits-44xx.h"
40 #include "control.h"
41 #include "scrm44xx.h"
42
43 /* OMAP4 modulemode control */
44 #define OMAP4430_MODULEMODE_HWCTRL_SHIFT                0
45 #define OMAP4430_MODULEMODE_SWCTRL_SHIFT                1
46
47 /*
48  * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
49  * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
50  * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
51  * half of this value.
52  */
53 #define OMAP4_DPLL_ABE_DEFFREQ                          98304000
54
55 /*
56  * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
57  * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
58  * locked frequency for the USB DPLL is 960MHz.
59  */
60 #define OMAP4_DPLL_USB_DEFFREQ                          960000000
61
62 /* Root clocks */
63
64 DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
65
66 DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
67
68 DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
69                 OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
70                 0x0, NULL);
71
72 DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
73
74 DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
75
76 DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
77
78 DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
79                 OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
80                 0x0, NULL);
81
82 DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
83
84 DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
85
86 DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
87
88 DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
89
90 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
91
92 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
93
94 DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
95
96 DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
97
98 static const char *sys_clkin_ck_parents[] = {
99         "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
100         "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
101         "virt_38400000_ck",
102 };
103
104 DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
105                OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
106                OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
107
108 DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
109
110 DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
111
112 DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
113
114 DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
115
116 DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
117
118 /* Module clocks and DPLL outputs */
119
120 static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
121         "sys_clkin_ck", "sys_32k_ck",
122 };
123
124 DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
125                NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
126                OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
127
128 DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
129                0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
130                OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
131
132 /* DPLL_ABE */
133 static struct dpll_data dpll_abe_dd = {
134         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
135         .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
136         .clk_ref        = &abe_dpll_refclk_mux_ck,
137         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
138         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
139         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
140         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
141         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
142         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
143         .enable_mask    = OMAP4430_DPLL_EN_MASK,
144         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
145         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
146         .m4xen_mask     = OMAP4430_DPLL_REGM4XEN_MASK,
147         .lpmode_mask    = OMAP4430_DPLL_LPMODE_EN_MASK,
148         .max_multiplier = 2047,
149         .max_divider    = 128,
150         .min_divider    = 1,
151 };
152
153
154 static const char *dpll_abe_ck_parents[] = {
155         "abe_dpll_refclk_mux_ck",
156 };
157
158 static struct clk dpll_abe_ck;
159
160 static const struct clk_ops dpll_abe_ck_ops = {
161         .enable         = &omap3_noncore_dpll_enable,
162         .disable        = &omap3_noncore_dpll_disable,
163         .recalc_rate    = &omap4_dpll_regm4xen_recalc,
164         .round_rate     = &omap4_dpll_regm4xen_round_rate,
165         .set_rate       = &omap3_noncore_dpll_set_rate,
166         .get_parent     = &omap2_init_dpll_parent,
167 };
168
169 static struct clk_hw_omap dpll_abe_ck_hw = {
170         .hw = {
171                 .clk = &dpll_abe_ck,
172         },
173         .dpll_data      = &dpll_abe_dd,
174         .ops            = &clkhwops_omap3_dpll,
175 };
176
177 DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
178
179 static const char *dpll_abe_x2_ck_parents[] = {
180         "dpll_abe_ck",
181 };
182
183 static struct clk dpll_abe_x2_ck;
184
185 static const struct clk_ops dpll_abe_x2_ck_ops = {
186         .recalc_rate    = &omap3_clkoutx2_recalc,
187 };
188
189 static struct clk_hw_omap dpll_abe_x2_ck_hw = {
190         .hw = {
191                 .clk = &dpll_abe_x2_ck,
192         },
193         .flags          = CLOCK_CLKOUTX2,
194         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
195         .ops            = &clkhwops_omap4_dpllmx,
196 };
197
198 DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
199
200 static const struct clk_ops omap_hsdivider_ops = {
201         .set_rate       = &omap2_clksel_set_rate,
202         .recalc_rate    = &omap2_clksel_recalc,
203         .round_rate     = &omap2_clksel_round_rate,
204 };
205
206 DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
207                           0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
208                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
209
210 DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
211                         0x0, 1, 8);
212
213 DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
214                    OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
215                    OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
216
217 DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
218                    OMAP4430_CM1_ABE_AESS_CLKCTRL,
219                    OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
220                    OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
221                    0x0, NULL);
222
223 DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
224                           0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
225                           OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
226
227 static const char *core_hsd_byp_clk_mux_ck_parents[] = {
228         "sys_clkin_ck", "dpll_abe_m3x2_ck",
229 };
230
231 DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
232                0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
233                OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
234                0x0, NULL);
235
236 /* DPLL_CORE */
237 static struct dpll_data dpll_core_dd = {
238         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
239         .clk_bypass     = &core_hsd_byp_clk_mux_ck,
240         .clk_ref        = &sys_clkin_ck,
241         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
242         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
243         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
244         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
245         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
246         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
247         .enable_mask    = OMAP4430_DPLL_EN_MASK,
248         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
249         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
250         .max_multiplier = 2047,
251         .max_divider    = 128,
252         .min_divider    = 1,
253 };
254
255
256 static const char *dpll_core_ck_parents[] = {
257         "sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
258 };
259
260 static struct clk dpll_core_ck;
261
262 static const struct clk_ops dpll_core_ck_ops = {
263         .recalc_rate    = &omap3_dpll_recalc,
264         .get_parent     = &omap2_init_dpll_parent,
265 };
266
267 static struct clk_hw_omap dpll_core_ck_hw = {
268         .hw = {
269                 .clk = &dpll_core_ck,
270         },
271         .dpll_data      = &dpll_core_dd,
272         .ops            = &clkhwops_omap3_dpll,
273 };
274
275 DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
276
277 static const char *dpll_core_x2_ck_parents[] = {
278         "dpll_core_ck",
279 };
280
281 static struct clk dpll_core_x2_ck;
282
283 static struct clk_hw_omap dpll_core_x2_ck_hw = {
284         .hw = {
285                 .clk = &dpll_core_x2_ck,
286         },
287 };
288
289 DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
290
291 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
292                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
293                           OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
294
295 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
296                           OMAP4430_CM_DIV_M2_DPLL_CORE,
297                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
298
299 DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
300                         2);
301
302 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
303                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
304                           OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
305
306 DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
307                    OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
308                    OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
309
310 DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
311                    0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
312                    OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
313
314 DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
315                    0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
316                    OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
317
318 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
319                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
320                           OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
321
322 DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
323                         0x0, 1, 2);
324
325 DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
326                    OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
327                    OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
328
329 static const struct clk_ops dpll_hsd_ops = {
330         .enable         = &omap2_dflt_clk_enable,
331         .disable        = &omap2_dflt_clk_disable,
332         .is_enabled     = &omap2_dflt_clk_is_enabled,
333         .recalc_rate    = &omap2_clksel_recalc,
334         .get_parent     = &omap2_clksel_find_parent_index,
335         .set_parent     = &omap2_clksel_set_parent,
336         .init           = &omap2_init_clk_clkdm,
337 };
338
339 static const struct clk_ops func_dmic_abe_gfclk_ops = {
340         .recalc_rate    = &omap2_clksel_recalc,
341         .get_parent     = &omap2_clksel_find_parent_index,
342         .set_parent     = &omap2_clksel_set_parent,
343 };
344
345 static const char *dpll_core_m3x2_ck_parents[] = {
346         "dpll_core_x2_ck",
347 };
348
349 static const struct clksel dpll_core_m3x2_div[] = {
350         { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
351         { .parent = NULL },
352 };
353
354 /* XXX Missing round_rate, set_rate in ops */
355 DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
356                          OMAP4430_CM_DIV_M3_DPLL_CORE,
357                          OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
358                          OMAP4430_CM_DIV_M3_DPLL_CORE,
359                          OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
360                          dpll_core_m3x2_ck_parents, dpll_hsd_ops);
361
362 DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
363                           &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
364                           OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
365
366 static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
367         "sys_clkin_ck", "div_iva_hs_clk",
368 };
369
370 DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
371                0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
372                OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
373
374 /* DPLL_IVA */
375 static struct dpll_data dpll_iva_dd = {
376         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
377         .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
378         .clk_ref        = &sys_clkin_ck,
379         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
380         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
381         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
382         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
383         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
384         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
385         .enable_mask    = OMAP4430_DPLL_EN_MASK,
386         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
387         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
388         .max_multiplier = 2047,
389         .max_divider    = 128,
390         .min_divider    = 1,
391 };
392
393 static const char *dpll_iva_ck_parents[] = {
394         "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
395 };
396
397 static struct clk dpll_iva_ck;
398
399 static const struct clk_ops dpll_ck_ops = {
400         .enable         = &omap3_noncore_dpll_enable,
401         .disable        = &omap3_noncore_dpll_disable,
402         .recalc_rate    = &omap3_dpll_recalc,
403         .round_rate     = &omap2_dpll_round_rate,
404         .set_rate       = &omap3_noncore_dpll_set_rate,
405         .get_parent     = &omap2_init_dpll_parent,
406 };
407
408 static struct clk_hw_omap dpll_iva_ck_hw = {
409         .hw = {
410                 .clk = &dpll_iva_ck,
411         },
412         .dpll_data      = &dpll_iva_dd,
413         .ops            = &clkhwops_omap3_dpll,
414 };
415
416 DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
417
418 static const char *dpll_iva_x2_ck_parents[] = {
419         "dpll_iva_ck",
420 };
421
422 static struct clk dpll_iva_x2_ck;
423
424 static struct clk_hw_omap dpll_iva_x2_ck_hw = {
425         .hw = {
426                 .clk = &dpll_iva_x2_ck,
427         },
428 };
429
430 DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
431
432 DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
433                           0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
434                           OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
435
436 DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
437                           0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
438                           OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
439
440 /* DPLL_MPU */
441 static struct dpll_data dpll_mpu_dd = {
442         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
443         .clk_bypass     = &div_mpu_hs_clk,
444         .clk_ref        = &sys_clkin_ck,
445         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
446         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
447         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
448         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
449         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
450         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
451         .enable_mask    = OMAP4430_DPLL_EN_MASK,
452         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
453         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
454         .max_multiplier = 2047,
455         .max_divider    = 128,
456         .min_divider    = 1,
457 };
458
459 static const char *dpll_mpu_ck_parents[] = {
460         "sys_clkin_ck", "div_mpu_hs_clk"
461 };
462
463 static struct clk dpll_mpu_ck;
464
465 static struct clk_hw_omap dpll_mpu_ck_hw = {
466         .hw = {
467                 .clk = &dpll_mpu_ck,
468         },
469         .dpll_data      = &dpll_mpu_dd,
470         .ops            = &clkhwops_omap3_dpll,
471 };
472
473 DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
474
475 DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
476
477 DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
478                           OMAP4430_CM_DIV_M2_DPLL_MPU,
479                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
480
481 DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
482                         &dpll_abe_m3x2_ck, 0x0, 1, 2);
483
484 static const char *per_hsd_byp_clk_mux_ck_parents[] = {
485         "sys_clkin_ck", "per_hs_clk_div_ck",
486 };
487
488 DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
489                0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
490                OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
491
492 /* DPLL_PER */
493 static struct dpll_data dpll_per_dd = {
494         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
495         .clk_bypass     = &per_hsd_byp_clk_mux_ck,
496         .clk_ref        = &sys_clkin_ck,
497         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
498         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
499         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
500         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
501         .mult_mask      = OMAP4430_DPLL_MULT_MASK,
502         .div1_mask      = OMAP4430_DPLL_DIV_MASK,
503         .enable_mask    = OMAP4430_DPLL_EN_MASK,
504         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
505         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
506         .max_multiplier = 2047,
507         .max_divider    = 128,
508         .min_divider    = 1,
509 };
510
511 static const char *dpll_per_ck_parents[] = {
512         "sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
513 };
514
515 static struct clk dpll_per_ck;
516
517 static struct clk_hw_omap dpll_per_ck_hw = {
518         .hw = {
519                 .clk = &dpll_per_ck,
520         },
521         .dpll_data      = &dpll_per_dd,
522         .ops            = &clkhwops_omap3_dpll,
523 };
524
525 DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
526
527 DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
528                    OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
529                    OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
530
531 static const char *dpll_per_x2_ck_parents[] = {
532         "dpll_per_ck",
533 };
534
535 static struct clk dpll_per_x2_ck;
536
537 static struct clk_hw_omap dpll_per_x2_ck_hw = {
538         .hw = {
539                 .clk = &dpll_per_x2_ck,
540         },
541         .flags          = CLOCK_CLKOUTX2,
542         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
543         .ops            = &clkhwops_omap4_dpllmx,
544 };
545
546 DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
547
548 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
549                           0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
550                           OMAP4430_DPLL_CLKOUT_DIV_MASK);
551
552 static const char *dpll_per_m3x2_ck_parents[] = {
553         "dpll_per_x2_ck",
554 };
555
556 static const struct clksel dpll_per_m3x2_div[] = {
557         { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
558         { .parent = NULL },
559 };
560
561 /* XXX Missing round_rate, set_rate in ops */
562 DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
563                          OMAP4430_CM_DIV_M3_DPLL_PER,
564                          OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
565                          OMAP4430_CM_DIV_M3_DPLL_PER,
566                          OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
567                          dpll_per_m3x2_ck_parents, dpll_hsd_ops);
568
569 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
570                           0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
571                           OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
572
573 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
574                           0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
575                           OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
576
577 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
578                           0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
579                           OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
580
581 DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
582                           0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
583                           OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
584
585 DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
586                         &dpll_abe_m3x2_ck, 0x0, 1, 3);
587
588 /* DPLL_USB */
589 static struct dpll_data dpll_usb_dd = {
590         .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
591         .clk_bypass     = &usb_hs_clk_div_ck,
592         .flags          = DPLL_J_TYPE,
593         .clk_ref        = &sys_clkin_ck,
594         .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
595         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
596         .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
597         .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
598         .mult_mask      = OMAP4430_DPLL_MULT_USB_MASK,
599         .div1_mask      = OMAP4430_DPLL_DIV_0_7_MASK,
600         .enable_mask    = OMAP4430_DPLL_EN_MASK,
601         .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
602         .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
603         .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
604         .max_multiplier = 4095,
605         .max_divider    = 256,
606         .min_divider    = 1,
607 };
608
609 static const char *dpll_usb_ck_parents[] = {
610         "sys_clkin_ck", "usb_hs_clk_div_ck"
611 };
612
613 static struct clk dpll_usb_ck;
614
615 static const struct clk_ops dpll_usb_ck_ops = {
616         .enable         = &omap3_noncore_dpll_enable,
617         .disable        = &omap3_noncore_dpll_disable,
618         .recalc_rate    = &omap3_dpll_recalc,
619         .round_rate     = &omap2_dpll_round_rate,
620         .set_rate       = &omap3_noncore_dpll_set_rate,
621         .get_parent     = &omap2_init_dpll_parent,
622         .init           = &omap2_init_clk_clkdm,
623 };
624
625 static struct clk_hw_omap dpll_usb_ck_hw = {
626         .hw = {
627                 .clk = &dpll_usb_ck,
628         },
629         .dpll_data      = &dpll_usb_dd,
630         .clkdm_name     = "l3_init_clkdm",
631         .ops            = &clkhwops_omap3_dpll,
632 };
633
634 DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
635
636 static const char *dpll_usb_clkdcoldo_ck_parents[] = {
637         "dpll_usb_ck",
638 };
639
640 static struct clk dpll_usb_clkdcoldo_ck;
641
642 static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
643 };
644
645 static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
646         .hw = {
647                 .clk = &dpll_usb_clkdcoldo_ck,
648         },
649         .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
650         .ops            = &clkhwops_omap4_dpllmx,
651 };
652
653 DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
654                   dpll_usb_clkdcoldo_ck_ops);
655
656 DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
657                           OMAP4430_CM_DIV_M2_DPLL_USB,
658                           OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
659
660 static const char *ducati_clk_mux_ck_parents[] = {
661         "div_core_ck", "dpll_per_m6x2_ck",
662 };
663
664 DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
665                OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
666                OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
667
668 DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
669                         0x0, 1, 16);
670
671 DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
672                         1, 4);
673
674 DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
675                         0x0, 1, 8);
676
677 static const struct clk_div_table func_48m_fclk_rates[] = {
678         { .div = 4, .val = 0 },
679         { .div = 8, .val = 1 },
680         { .div = 0 },
681 };
682 DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
683                          0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
684                          OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
685                          NULL);
686
687 DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
688                         0x0, 1, 4);
689
690 static const struct clk_div_table func_64m_fclk_rates[] = {
691         { .div = 2, .val = 0 },
692         { .div = 4, .val = 1 },
693         { .div = 0 },
694 };
695 DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
696                          0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
697                          OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
698                          NULL);
699
700 static const struct clk_div_table func_96m_fclk_rates[] = {
701         { .div = 2, .val = 0 },
702         { .div = 4, .val = 1 },
703         { .div = 0 },
704 };
705 DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
706                          0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
707                          OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
708                          NULL);
709
710 static const struct clk_div_table init_60m_fclk_rates[] = {
711         { .div = 1, .val = 0 },
712         { .div = 8, .val = 1 },
713         { .div = 0 },
714 };
715 DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
716                          0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
717                          OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
718                          0x0, init_60m_fclk_rates, NULL);
719
720 DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
721                    OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
722                    OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
723
724 DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
725                    OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
726                    OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
727
728 DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
729                         0x0, 1, 16);
730
731 static const char *l4_wkup_clk_mux_ck_parents[] = {
732         "sys_clkin_ck", "lp_clk_div_ck",
733 };
734
735 DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
736                OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
737                OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
738
739 static const struct clk_div_table ocp_abe_iclk_rates[] = {
740         { .div = 2, .val = 0 },
741         { .div = 1, .val = 1 },
742         { .div = 0 },
743 };
744 DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
745                          OMAP4430_CM1_ABE_AESS_CLKCTRL,
746                          OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
747                          OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
748                          0x0, ocp_abe_iclk_rates, NULL);
749
750 DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
751                         0x0, 1, 4);
752
753 DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
754                    OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
755                    OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
756
757 DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
758                    OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
759                    OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
760
761 static const char *dbgclk_mux_ck_parents[] = {
762         "sys_clkin_ck"
763 };
764
765 static struct clk dbgclk_mux_ck;
766 DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
767 DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
768                   dpll_usb_clkdcoldo_ck_ops);
769
770 /* Leaf clocks controlled by modules */
771
772 DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
773                 OMAP4430_CM_L4SEC_AES1_CLKCTRL,
774                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
775
776 DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
777                 OMAP4430_CM_L4SEC_AES2_CLKCTRL,
778                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
779
780 DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
781                 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
782                 OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
783
784 static const struct clk_div_table div_ts_ck_rates[] = {
785         { .div = 8, .val = 0 },
786         { .div = 16, .val = 1 },
787         { .div = 32, .val = 2 },
788         { .div = 0 },
789 };
790 DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
791                          0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
792                          OMAP4430_CLKSEL_24_25_SHIFT,
793                          OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
794                          NULL);
795
796 DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
797                 OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
798                 OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
799                 0x0, NULL);
800
801 static const char *dmic_sync_mux_ck_parents[] = {
802         "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
803 };
804
805 DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
806                0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
807                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
808                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
809
810 static const struct clksel func_dmic_abe_gfclk_sel[] = {
811         { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
812         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
813         { .parent = &slimbus_clk, .rates = div_1_2_rates },
814         { .parent = NULL },
815 };
816
817 static const char *func_dmic_abe_gfclk_parents[] = {
818         "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
819 };
820
821 DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
822                     OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
823                     func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
824
825 DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
826                 OMAP4430_CM_DSS_DSS_CLKCTRL,
827                 OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
828
829 DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
830                 OMAP4430_CM_DSS_DSS_CLKCTRL,
831                 OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
832
833 DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, 0x0,
834                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
835                 0x0, NULL);
836
837 DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
838                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
839                 0x0, NULL);
840
841 DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
842                 OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
843                 0x0, NULL);
844
845 DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
846                    OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
847                    OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
848
849 DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
850                 OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
851                 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
852
853 DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
854                 OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
855                 0x0, NULL);
856
857 DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
858                 OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
859                 OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
860
861 DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
862                 OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
863                 0x0, NULL);
864
865 DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
866                 OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
867                 0x0, NULL);
868
869 DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
870                 OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
871                 0x0, NULL);
872
873 static const struct clksel sgx_clk_mux_sel[] = {
874         { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
875         { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
876         { .parent = NULL },
877 };
878
879 static const char *sgx_clk_mux_parents[] = {
880         "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
881 };
882
883 DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
884                     OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
885                     sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
886
887 DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
888                    OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
889                    OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
890                    NULL);
891
892 DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
893                 OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
894                 0x0, NULL);
895
896 DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
897                OMAP4430_CM1_ABE_MCASP_CLKCTRL,
898                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
899                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
900
901 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
902         { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
903         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
904         { .parent = &slimbus_clk, .rates = div_1_2_rates },
905         { .parent = NULL },
906 };
907
908 static const char *func_mcasp_abe_gfclk_parents[] = {
909         "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
910 };
911
912 DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
913                     OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
914                     func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
915
916 DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
917                OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
918                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
919                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
920
921 static const struct clksel func_mcbsp1_gfclk_sel[] = {
922         { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
923         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
924         { .parent = &slimbus_clk, .rates = div_1_2_rates },
925         { .parent = NULL },
926 };
927
928 static const char *func_mcbsp1_gfclk_parents[] = {
929         "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
930 };
931
932 DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
933                     OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
934                     OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
935                     func_dmic_abe_gfclk_ops);
936
937 DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
938                OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
939                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
940                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
941
942 static const struct clksel func_mcbsp2_gfclk_sel[] = {
943         { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
944         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
945         { .parent = &slimbus_clk, .rates = div_1_2_rates },
946         { .parent = NULL },
947 };
948
949 static const char *func_mcbsp2_gfclk_parents[] = {
950         "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
951 };
952
953 DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
954                     OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
955                     OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
956                     func_dmic_abe_gfclk_ops);
957
958 DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
959                OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
960                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
961                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
962
963 static const struct clksel func_mcbsp3_gfclk_sel[] = {
964         { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
965         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
966         { .parent = &slimbus_clk, .rates = div_1_2_rates },
967         { .parent = NULL },
968 };
969
970 static const char *func_mcbsp3_gfclk_parents[] = {
971         "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
972 };
973
974 DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
975                     OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
976                     OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
977                     func_dmic_abe_gfclk_ops);
978
979 static const char *mcbsp4_sync_mux_ck_parents[] = {
980         "func_96m_fclk", "per_abe_nc_fclk",
981 };
982
983 DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
984                OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
985                OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
986                OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
987
988 static const struct clksel per_mcbsp4_gfclk_sel[] = {
989         { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
990         { .parent = &pad_clks_ck, .rates = div_1_1_rates },
991         { .parent = NULL },
992 };
993
994 static const char *per_mcbsp4_gfclk_parents[] = {
995         "mcbsp4_sync_mux_ck", "pad_clks_ck",
996 };
997
998 DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
999                     OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1000                     OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
1001                     func_dmic_abe_gfclk_ops);
1002
1003 static const struct clksel hsmmc1_fclk_sel[] = {
1004         { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1005         { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1006         { .parent = NULL },
1007 };
1008
1009 static const char *hsmmc1_fclk_parents[] = {
1010         "func_64m_fclk", "func_96m_fclk",
1011 };
1012
1013 DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1014                     OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1015                     hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1016
1017 DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
1018                     OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1019                     hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
1020
1021 DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
1022                 OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1023                 OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
1024
1025 DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
1026                 OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
1027                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1028
1029 DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
1030                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1031                 OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
1032
1033 DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
1034                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1035                 OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
1036
1037 DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
1038                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1039                 OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
1040
1041 DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
1042                 OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
1043                 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
1044
1045 DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
1046                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1047                 OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
1048
1049 DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
1050                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1051                 OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
1052
1053 DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
1054                 &pad_slimbus_core_clks_ck, 0x0,
1055                 OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
1056                 OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
1057
1058 DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1059                 0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1060                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1061
1062 DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1063                 0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1064                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1065
1066 DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
1067                 0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1068                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1069
1070 static const struct clksel dmt1_clk_mux_sel[] = {
1071         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1072         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1073         { .parent = NULL },
1074 };
1075
1076 DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
1077                     OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
1078                     abe_dpll_bypass_clk_mux_ck_parents,
1079                     func_dmic_abe_gfclk_ops);
1080
1081 DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1082                     OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
1083                     abe_dpll_bypass_clk_mux_ck_parents,
1084                     func_dmic_abe_gfclk_ops);
1085
1086 DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1087                     OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
1088                     abe_dpll_bypass_clk_mux_ck_parents,
1089                     func_dmic_abe_gfclk_ops);
1090
1091 DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1092                     OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
1093                     abe_dpll_bypass_clk_mux_ck_parents,
1094                     func_dmic_abe_gfclk_ops);
1095
1096 DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1097                     OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
1098                     abe_dpll_bypass_clk_mux_ck_parents,
1099                     func_dmic_abe_gfclk_ops);
1100
1101 DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1102                     OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
1103                     abe_dpll_bypass_clk_mux_ck_parents,
1104                     func_dmic_abe_gfclk_ops);
1105
1106 static const struct clksel timer5_sync_mux_sel[] = {
1107         { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1108         { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1109         { .parent = NULL },
1110 };
1111
1112 static const char *timer5_sync_mux_parents[] = {
1113         "syc_clk_div_ck", "sys_32k_ck",
1114 };
1115
1116 DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1117                     OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
1118                     timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1119
1120 DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1121                     OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
1122                     timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1123
1124 DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1125                     OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
1126                     timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1127
1128 DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
1129                     OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
1130                     timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
1131
1132 DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
1133                     OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
1134                     abe_dpll_bypass_clk_mux_ck_parents,
1135                     func_dmic_abe_gfclk_ops);
1136
1137 static struct clk usb_host_fs_fck;
1138
1139 static const char *usb_host_fs_fck_parent_names[] = {
1140         "func_48mc_fclk",
1141 };
1142
1143 static const struct clk_ops usb_host_fs_fck_ops = {
1144         .enable         = &omap2_dflt_clk_enable,
1145         .disable        = &omap2_dflt_clk_disable,
1146         .is_enabled     = &omap2_dflt_clk_is_enabled,
1147 };
1148
1149 static struct clk_hw_omap usb_host_fs_fck_hw = {
1150         .hw = {
1151                 .clk = &usb_host_fs_fck,
1152         },
1153         .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
1154         .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
1155         .clkdm_name     = "l3_init_clkdm",
1156 };
1157
1158 DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
1159                   usb_host_fs_fck_ops);
1160
1161 static const char *utmi_p1_gfclk_parents[] = {
1162         "init_60m_fclk", "xclk60mhsp1_ck",
1163 };
1164
1165 DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
1166                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1167                OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
1168                0x0, NULL);
1169
1170 DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
1171                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1172                 OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
1173
1174 static const char *utmi_p2_gfclk_parents[] = {
1175         "init_60m_fclk", "xclk60mhsp2_ck",
1176 };
1177
1178 DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
1179                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1180                OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
1181                0x0, NULL);
1182
1183 DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
1184                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1185                 OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
1186
1187 DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1188                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1189                 OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
1190
1191 DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
1192                 &dpll_usb_m2_ck, 0x0,
1193                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1194                 OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
1195
1196 DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
1197                 &init_60m_fclk, 0x0,
1198                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1199                 OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
1200
1201 DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
1202                 &init_60m_fclk, 0x0,
1203                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1204                 OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
1205
1206 DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
1207                 &dpll_usb_m2_ck, 0x0,
1208                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1209                 OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
1210
1211 DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
1212                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1213                 OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
1214
1215 DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
1216                 OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
1217                 OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
1218
1219 static const char *otg_60m_gfclk_parents[] = {
1220         "utmi_phy_clkout_ck", "xclk60motg_ck",
1221 };
1222
1223 DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
1224                OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
1225                OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
1226
1227 DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
1228                 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1229                 OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
1230
1231 DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
1232                 OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
1233                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1234
1235 DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
1236                 OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
1237                 OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
1238
1239 DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1240                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1241                 OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
1242
1243 DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1244                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1245                 OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
1246
1247 DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
1248                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1249                 OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
1250
1251 DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
1252                 OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
1253                 OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
1254
1255 static const struct clk_div_table usim_ck_rates[] = {
1256         { .div = 14, .val = 0 },
1257         { .div = 18, .val = 1 },
1258         { .div = 0 },
1259 };
1260 DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
1261                          OMAP4430_CM_WKUP_USIM_CLKCTRL,
1262                          OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
1263                          0x0, usim_ck_rates, NULL);
1264
1265 DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
1266                 OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
1267                 0x0, NULL);
1268
1269 /* Remaining optional clocks */
1270 static const char *pmd_stm_clock_mux_ck_parents[] = {
1271         "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
1272 };
1273
1274 DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1275                OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
1276                OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
1277
1278 DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
1279                OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1280                OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
1281                OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
1282
1283 DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
1284                    &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1285                    OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
1286                    OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
1287                    NULL);
1288
1289 static const char *trace_clk_div_ck_parents[] = {
1290         "pmd_trace_clk_mux_ck",
1291 };
1292
1293 static const struct clksel trace_clk_div_div[] = {
1294         { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
1295         { .parent = NULL },
1296 };
1297
1298 static struct clk trace_clk_div_ck;
1299
1300 static const struct clk_ops trace_clk_div_ck_ops = {
1301         .recalc_rate    = &omap2_clksel_recalc,
1302         .set_rate       = &omap2_clksel_set_rate,
1303         .round_rate     = &omap2_clksel_round_rate,
1304         .init           = &omap2_init_clk_clkdm,
1305         .enable         = &omap2_clkops_enable_clkdm,
1306         .disable        = &omap2_clkops_disable_clkdm,
1307 };
1308
1309 static struct clk_hw_omap trace_clk_div_ck_hw = {
1310         .hw = {
1311                 .clk = &trace_clk_div_ck,
1312         },
1313         .clkdm_name     = "emu_sys_clkdm",
1314         .clksel         = trace_clk_div_div,
1315         .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
1316         .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
1317 };
1318
1319 DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
1320                   trace_clk_div_ck_ops);
1321
1322 /* SCRM aux clk nodes */
1323
1324 static const struct clksel auxclk_src_sel[] = {
1325         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1326         { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
1327         { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
1328         { .parent = NULL },
1329 };
1330
1331 static const char *auxclk_src_ck_parents[] = {
1332         "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
1333 };
1334
1335 static const struct clk_ops auxclk_src_ck_ops = {
1336         .enable         = &omap2_dflt_clk_enable,
1337         .disable        = &omap2_dflt_clk_disable,
1338         .is_enabled     = &omap2_dflt_clk_is_enabled,
1339         .recalc_rate    = &omap2_clksel_recalc,
1340         .get_parent     = &omap2_clksel_find_parent_index,
1341 };
1342
1343 DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
1344                          OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
1345                          OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
1346                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1347
1348 DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
1349                    OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1350                    0x0, NULL);
1351
1352 DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
1353                          OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
1354                          OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
1355                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1356
1357 DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
1358                    OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1359                    0x0, NULL);
1360
1361 DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
1362                          OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
1363                          OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
1364                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1365
1366 DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
1367                    OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1368                    0x0, NULL);
1369
1370 DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
1371                          OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
1372                          OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
1373                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1374
1375 DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
1376                    OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1377                    0x0, NULL);
1378
1379 DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
1380                          OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
1381                          OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
1382                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1383
1384 DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
1385                    OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1386                    0x0, NULL);
1387
1388 DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
1389                          OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
1390                          OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
1391                          auxclk_src_ck_parents, auxclk_src_ck_ops);
1392
1393 DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
1394                    OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
1395                    0x0, NULL);
1396
1397 static const char *auxclkreq_ck_parents[] = {
1398         "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
1399         "auxclk5_ck",
1400 };
1401
1402 DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
1403                OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1404                0x0, NULL);
1405
1406 DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
1407                OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1408                0x0, NULL);
1409
1410 DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
1411                OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1412                0x0, NULL);
1413
1414 DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
1415                OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1416                0x0, NULL);
1417
1418 DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
1419                OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1420                0x0, NULL);
1421
1422 DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
1423                OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
1424                0x0, NULL);
1425
1426 /*
1427  * clkdev
1428  */
1429
1430 static struct omap_clk omap44xx_clks[] = {
1431         CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
1432         CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck,       CK_443X),
1433         CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
1434         CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
1435         CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
1436         CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk,       CK_443X),
1437         CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
1438         CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
1439         CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
1440         CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
1441         CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
1442         CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
1443         CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
1444         CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
1445         CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
1446         CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
1447         CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
1448         CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
1449         CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
1450         CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
1451         CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
1452         CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
1453         CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
1454         CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
1455         CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
1456         CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
1457         CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
1458         CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
1459         CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
1460         CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
1461         CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
1462         CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
1463         CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
1464         CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
1465         CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
1466         CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
1467         CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
1468         CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
1469         CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
1470         CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
1471         CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
1472         CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
1473         CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
1474         CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
1475         CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
1476         CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
1477         CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
1478         CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
1479         CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
1480         CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
1481         CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
1482         CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
1483         CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
1484         CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
1485         CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
1486         CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
1487         CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
1488         CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
1489         CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
1490         CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
1491         CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
1492         CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
1493         CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
1494         CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
1495         CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
1496         CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
1497         CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
1498         CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
1499         CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
1500         CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
1501         CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
1502         CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
1503         CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
1504         CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
1505         CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
1506         CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
1507         CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
1508         CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
1509         CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
1510         CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
1511         CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
1512         CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
1513         CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
1514         CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
1515         CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
1516         CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
1517         CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
1518         CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
1519         CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
1520         CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
1521         CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
1522         CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
1523         CLK(NULL,       "func_dmic_abe_gfclk",                  &func_dmic_abe_gfclk,   CK_443X),
1524         CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
1525         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
1526         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
1527         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
1528         CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
1529         CLK("omapdss_dss",      "ick",                  &dss_fck,       CK_443X),
1530         CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
1531         CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
1532         CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
1533         CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
1534         CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
1535         CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
1536         CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
1537         CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux,   CK_443X),
1538         CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
1539         CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
1540         CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
1541         CLK(NULL,       "func_mcasp_abe_gfclk",                 &func_mcasp_abe_gfclk,  CK_443X),
1542         CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
1543         CLK(NULL,       "func_mcbsp1_gfclk",                    &func_mcbsp1_gfclk,     CK_443X),
1544         CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
1545         CLK(NULL,       "func_mcbsp2_gfclk",                    &func_mcbsp2_gfclk,     CK_443X),
1546         CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
1547         CLK(NULL,       "func_mcbsp3_gfclk",                    &func_mcbsp3_gfclk,     CK_443X),
1548         CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
1549         CLK(NULL,       "per_mcbsp4_gfclk",                     &per_mcbsp4_gfclk,      CK_443X),
1550         CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk,   CK_443X),
1551         CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk,   CK_443X),
1552         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
1553         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
1554         CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
1555         CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
1556         CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
1557         CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
1558         CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
1559         CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
1560         CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
1561         CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
1562         CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
1563         CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
1564         CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux,  CK_443X),
1565         CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux,  CK_443X),
1566         CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux,  CK_443X),
1567         CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux,   CK_443X),
1568         CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux,   CK_443X),
1569         CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux,   CK_443X),
1570         CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux,       CK_443X),
1571         CLK(NULL,       "timer6_sync_mux",                      &timer6_sync_mux,       CK_443X),
1572         CLK(NULL,       "timer7_sync_mux",                      &timer7_sync_mux,       CK_443X),
1573         CLK(NULL,       "timer8_sync_mux",                      &timer8_sync_mux,       CK_443X),
1574         CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux,   CK_443X),
1575         CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
1576         CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
1577         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
1578         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
1579         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
1580         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
1581         CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
1582         CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
1583         CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
1584         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
1585         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
1586         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
1587         CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
1588         CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
1589         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
1590         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
1591         CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
1592         CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick,        CK_443X),
1593         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
1594         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
1595         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
1596         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
1597         CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
1598         CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
1599         CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
1600         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
1601         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
1602         CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
1603         CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
1604         CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
1605         CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
1606         CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
1607         CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
1608         CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
1609         CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
1610         CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
1611         CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
1612         CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
1613         CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
1614         CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
1615         CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
1616         CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
1617         CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
1618         CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
1619         CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
1620         CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
1621         CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
1622         CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
1623         CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
1624         CLK("omap-gpmc",        "fck",                  &dummy_ck,      CK_443X),
1625         CLK("omap_i2c.1",       "ick",                  &dummy_ck,      CK_443X),
1626         CLK("omap_i2c.2",       "ick",                  &dummy_ck,      CK_443X),
1627         CLK("omap_i2c.3",       "ick",                  &dummy_ck,      CK_443X),
1628         CLK("omap_i2c.4",       "ick",                  &dummy_ck,      CK_443X),
1629         CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
1630         CLK("omap_hsmmc.0",     "ick",                  &dummy_ck,      CK_443X),
1631         CLK("omap_hsmmc.1",     "ick",                  &dummy_ck,      CK_443X),
1632         CLK("omap_hsmmc.2",     "ick",                  &dummy_ck,      CK_443X),
1633         CLK("omap_hsmmc.3",     "ick",                  &dummy_ck,      CK_443X),
1634         CLK("omap_hsmmc.4",     "ick",                  &dummy_ck,      CK_443X),
1635         CLK("omap-mcbsp.1",     "ick",                  &dummy_ck,      CK_443X),
1636         CLK("omap-mcbsp.2",     "ick",                  &dummy_ck,      CK_443X),
1637         CLK("omap-mcbsp.3",     "ick",                  &dummy_ck,      CK_443X),
1638         CLK("omap-mcbsp.4",     "ick",                  &dummy_ck,      CK_443X),
1639         CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
1640         CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
1641         CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
1642         CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
1643         CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
1644         CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
1645         CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
1646         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
1647         CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
1648         CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
1649         CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
1650         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
1651         CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
1652         /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
1653         CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1654         CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1655         CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1656         CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1657         CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1658         CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1659         CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1660         CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1661         CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1662         CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1663         CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1664         CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1665         CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1666         CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1667         CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1668         CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1669         CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1670         CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
1671         CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1672         CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1673         CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1674         CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
1675         CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
1676 };
1677
1678 int __init omap4xxx_clk_init(void)
1679 {
1680         u32 cpu_clkflg;
1681         struct omap_clk *c;
1682         int rc;
1683
1684         if (cpu_is_omap443x()) {
1685                 cpu_mask = RATE_IN_4430;
1686                 cpu_clkflg = CK_443X;
1687         } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
1688                 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
1689                 cpu_clkflg = CK_446X | CK_443X;
1690
1691                 if (cpu_is_omap447x())
1692                         pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
1693         } else {
1694                 return 0;
1695         }
1696
1697         for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
1698                                                                         c++) {
1699                 if (c->cpu & cpu_clkflg) {
1700                         clkdev_add(&c->lk);
1701                         if (!__clk_init(NULL, c->lk.clk))
1702                                 omap2_init_clk_hw_omap_clocks(c->lk.clk);
1703                 }
1704         }
1705
1706         omap2_clk_disable_autoidle_all();
1707
1708         /*
1709          * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
1710          * state when turning the ABE clock domain. Workaround this by
1711          * locking the ABE DPLL on boot.
1712          * Lock the ABE DPLL in any case to avoid issues with audio.
1713          */
1714         rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
1715         if (!rc)
1716                 rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
1717         if (rc)
1718                 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
1719
1720         /*
1721          * Lock USB DPLL on OMAP4 devices so that the L3INIT power
1722          * domain can transition to retention state when not in use.
1723          */
1724         rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
1725         if (rc)
1726                 pr_err("%s: failed to configure USB DPLL!\n", __func__);
1727
1728         return 0;
1729 }