Remove obsolete #include <linux/config.h>
[linux-3.10.git] / arch / arm / mach-omap1 / serial.c
1 /*
2  * linux/arch/arm/mach-omap1/id.c
3  *
4  * OMAP1 CPU identification code
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/delay.h>
15 #include <linux/serial.h>
16 #include <linux/tty.h>
17 #include <linux/serial_8250.h>
18 #include <linux/serial_reg.h>
19 #include <linux/clk.h>
20
21 #include <asm/io.h>
22 #include <asm/mach-types.h>
23
24 #include <asm/arch/board.h>
25 #include <asm/arch/mux.h>
26 #include <asm/arch/gpio.h>
27 #include <asm/arch/fpga.h>
28 #ifdef CONFIG_PM
29 #include <asm/arch/pm.h>
30 #endif
31
32 static struct clk * uart1_ck;
33 static struct clk * uart2_ck;
34 static struct clk * uart3_ck;
35
36 static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
37                                           int offset)
38 {
39         offset <<= up->regshift;
40         return (unsigned int)__raw_readb(up->membase + offset);
41 }
42
43 static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
44                                     int value)
45 {
46         offset <<= p->regshift;
47         __raw_writeb(value, p->membase + offset);
48 }
49
50 /*
51  * Internal UARTs need to be initialized for the 8250 autoconfig to work
52  * properly. Note that the TX watermark initialization may not be needed
53  * once the 8250.c watermark handling code is merged.
54  */
55 static void __init omap_serial_reset(struct plat_serial8250_port *p)
56 {
57         omap_serial_outp(p, UART_OMAP_MDR1, 0x07);      /* disable UART */
58         omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
59         omap_serial_outp(p, UART_OMAP_MDR1, 0x00);      /* enable UART */
60
61         if (!cpu_is_omap1510()) {
62                 omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
63                 while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
64         }
65 }
66
67 static struct plat_serial8250_port serial_platform_data[] = {
68         {
69                 .membase        = (char*)IO_ADDRESS(OMAP_UART1_BASE),
70                 .mapbase        = (unsigned long)OMAP_UART1_BASE,
71                 .irq            = INT_UART1,
72                 .flags          = UPF_BOOT_AUTOCONF,
73                 .iotype         = UPIO_MEM,
74                 .regshift       = 2,
75                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
76         },
77         {
78                 .membase        = (char*)IO_ADDRESS(OMAP_UART2_BASE),
79                 .mapbase        = (unsigned long)OMAP_UART2_BASE,
80                 .irq            = INT_UART2,
81                 .flags          = UPF_BOOT_AUTOCONF,
82                 .iotype         = UPIO_MEM,
83                 .regshift       = 2,
84                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
85         },
86         {
87                 .membase        = (char*)IO_ADDRESS(OMAP_UART3_BASE),
88                 .mapbase        = (unsigned long)OMAP_UART3_BASE,
89                 .irq            = INT_UART3,
90                 .flags          = UPF_BOOT_AUTOCONF,
91                 .iotype         = UPIO_MEM,
92                 .regshift       = 2,
93                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
94         },
95         { },
96 };
97
98 static struct platform_device serial_device = {
99         .name                   = "serial8250",
100         .id                     = PLAT8250_DEV_PLATFORM,
101         .dev                    = {
102                 .platform_data  = serial_platform_data,
103         },
104 };
105
106 /*
107  * Note that on Innovator-1510 UART2 pins conflict with USB2.
108  * By default UART2 does not work on Innovator-1510 if you have
109  * USB OHCI enabled. To use UART2, you must disable USB2 first.
110  */
111 void __init omap_serial_init(void)
112 {
113         int i;
114         const struct omap_uart_config *info;
115
116         if (cpu_is_omap730()) {
117                 serial_platform_data[0].regshift = 0;
118                 serial_platform_data[1].regshift = 0;
119                 serial_platform_data[0].irq = INT_730_UART_MODEM_1;
120                 serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
121         }
122
123         if (cpu_is_omap1510()) {
124                 serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
125                 serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
126                 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
127         }
128
129         info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
130         if (info == NULL)
131                 return;
132
133         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
134                 unsigned char reg;
135
136                 if (!((1 << i) & info->enabled_uarts)) {
137                         serial_platform_data[i].membase = NULL;
138                         serial_platform_data[i].mapbase = 0;
139                         continue;
140                 }
141
142                 switch (i) {
143                 case 0:
144                         uart1_ck = clk_get(NULL, "uart1_ck");
145                         if (IS_ERR(uart1_ck))
146                                 printk("Could not get uart1_ck\n");
147                         else {
148                                 clk_enable(uart1_ck);
149                                 if (cpu_is_omap1510())
150                                         clk_set_rate(uart1_ck, 12000000);
151                         }
152                         if (cpu_is_omap1510()) {
153                                 omap_cfg_reg(UART1_TX);
154                                 omap_cfg_reg(UART1_RTS);
155                                 if (machine_is_omap_innovator()) {
156                                         reg = fpga_read(OMAP1510_FPGA_POWER);
157                                         reg |= OMAP1510_FPGA_PCR_COM1_EN;
158                                         fpga_write(reg, OMAP1510_FPGA_POWER);
159                                         udelay(10);
160                                 }
161                         }
162                         break;
163                 case 1:
164                         uart2_ck = clk_get(NULL, "uart2_ck");
165                         if (IS_ERR(uart2_ck))
166                                 printk("Could not get uart2_ck\n");
167                         else {
168                                 clk_enable(uart2_ck);
169                                 if (cpu_is_omap1510())
170                                         clk_set_rate(uart2_ck, 12000000);
171                                 else
172                                         clk_set_rate(uart2_ck, 48000000);
173                         }
174                         if (cpu_is_omap1510()) {
175                                 omap_cfg_reg(UART2_TX);
176                                 omap_cfg_reg(UART2_RTS);
177                                 if (machine_is_omap_innovator()) {
178                                         reg = fpga_read(OMAP1510_FPGA_POWER);
179                                         reg |= OMAP1510_FPGA_PCR_COM2_EN;
180                                         fpga_write(reg, OMAP1510_FPGA_POWER);
181                                         udelay(10);
182                                 }
183                         }
184                         break;
185                 case 2:
186                         uart3_ck = clk_get(NULL, "uart3_ck");
187                         if (IS_ERR(uart3_ck))
188                                 printk("Could not get uart3_ck\n");
189                         else {
190                                 clk_enable(uart3_ck);
191                                 if (cpu_is_omap1510())
192                                         clk_set_rate(uart3_ck, 12000000);
193                         }
194                         if (cpu_is_omap1510()) {
195                                 omap_cfg_reg(UART3_TX);
196                                 omap_cfg_reg(UART3_RX);
197                         }
198                         break;
199                 }
200                 omap_serial_reset(&serial_platform_data[i]);
201         }
202 }
203
204 #ifdef CONFIG_OMAP_SERIAL_WAKE
205
206 static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id,
207                                               struct pt_regs *regs)
208 {
209         /* Need to do something with serial port right after wake-up? */
210         return IRQ_HANDLED;
211 }
212
213 /*
214  * Reroutes serial RX lines to GPIO lines for the duration of
215  * sleep to allow waking up the device from serial port even
216  * in deep sleep.
217  */
218 void omap_serial_wake_trigger(int enable)
219 {
220         if (!cpu_is_omap16xx())
221                 return;
222
223         if (uart1_ck != NULL) {
224                 if (enable)
225                         omap_cfg_reg(V14_16XX_GPIO37);
226                 else
227                         omap_cfg_reg(V14_16XX_UART1_RX);
228         }
229         if (uart2_ck != NULL) {
230                 if (enable)
231                         omap_cfg_reg(R9_16XX_GPIO18);
232                 else
233                         omap_cfg_reg(R9_16XX_UART2_RX);
234         }
235         if (uart3_ck != NULL) {
236                 if (enable)
237                         omap_cfg_reg(L14_16XX_GPIO49);
238                 else
239                         omap_cfg_reg(L14_16XX_UART3_RX);
240         }
241 }
242
243 static void __init omap_serial_set_port_wakeup(int gpio_nr)
244 {
245         int ret;
246
247         ret = omap_request_gpio(gpio_nr);
248         if (ret < 0) {
249                 printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
250                        gpio_nr);
251                 return;
252         }
253         omap_set_gpio_direction(gpio_nr, 1);
254         ret = request_irq(OMAP_GPIO_IRQ(gpio_nr), &omap_serial_wake_interrupt,
255                           SA_TRIGGER_RISING, "serial wakeup", NULL);
256         if (ret) {
257                 omap_free_gpio(gpio_nr);
258                 printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
259                        gpio_nr);
260                 return;
261         }
262         enable_irq_wake(OMAP_GPIO_IRQ(gpio_nr));
263 }
264
265 static int __init omap_serial_wakeup_init(void)
266 {
267         if (!cpu_is_omap16xx())
268                 return 0;
269
270         if (uart1_ck != NULL)
271                 omap_serial_set_port_wakeup(37);
272         if (uart2_ck != NULL)
273                 omap_serial_set_port_wakeup(18);
274         if (uart3_ck != NULL)
275                 omap_serial_set_port_wakeup(49);
276
277         return 0;
278 }
279 late_initcall(omap_serial_wakeup_init);
280
281 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
282
283 static int __init omap_init(void)
284 {
285         return platform_device_register(&serial_device);
286 }
287 arch_initcall(omap_init);