Linux-2.6.12-rc2
[linux-3.10.git] / arch / arm / mach-ixp4xx / common.c
1 /*
2  * arch/arm/mach-ixp4xx/common.c
3  *
4  * Generic code shared across all IXP4XX platforms
5  *
6  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
7  *
8  * Copyright 2002 (c) Intel Corporation
9  * Copyright 2003-2004 (c) MontaVista, Software, Inc. 
10  * 
11  * This file is licensed under  the terms of the GNU General Public 
12  * License version 2. This program is licensed "as is" without any 
13  * warranty of any kind, whether express or implied.
14  */
15
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/mm.h>
19 #include <linux/init.h>
20 #include <linux/serial.h>
21 #include <linux/sched.h>
22 #include <linux/tty.h>
23 #include <linux/serial_core.h>
24 #include <linux/bootmem.h>
25 #include <linux/interrupt.h>
26 #include <linux/bitops.h>
27 #include <linux/time.h>
28 #include <linux/timex.h>
29
30 #include <asm/hardware.h>
31 #include <asm/uaccess.h>
32 #include <asm/io.h>
33 #include <asm/pgtable.h>
34 #include <asm/page.h>
35 #include <asm/irq.h>
36
37 #include <asm/mach/map.h>
38 #include <asm/mach/irq.h>
39 #include <asm/mach/time.h>
40
41 enum ixp4xx_irq_type {
42         IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
43 };
44 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type);
45
46 /*************************************************************************
47  * GPIO acces functions
48  *************************************************************************/
49
50 /*
51  * Configure GPIO line for input, interrupt, or output operation
52  *
53  * TODO: Enable/disable the irq_desc based on interrupt or output mode.
54  * TODO: Should these be named ixp4xx_gpio_?
55  */
56 void gpio_line_config(u8 line, u32 style)
57 {
58         static const int gpio2irq[] = {
59                 6, 7, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29
60         };
61         u32 enable;
62         volatile u32 *int_reg;
63         u32 int_style;
64         enum ixp4xx_irq_type irq_type;
65
66         enable = *IXP4XX_GPIO_GPOER;
67
68         if (style & IXP4XX_GPIO_OUT) {
69                 enable &= ~((1) << line);
70         } else if (style & IXP4XX_GPIO_IN) {
71                 enable |= ((1) << line);
72
73                 switch (style & IXP4XX_GPIO_INTSTYLE_MASK)
74                 {
75                 case (IXP4XX_GPIO_ACTIVE_HIGH):
76                         int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
77                         irq_type = IXP4XX_IRQ_LEVEL;
78                         break;
79                 case (IXP4XX_GPIO_ACTIVE_LOW):
80                         int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
81                         irq_type = IXP4XX_IRQ_LEVEL;
82                         break;
83                 case (IXP4XX_GPIO_RISING_EDGE):
84                         int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
85                         irq_type = IXP4XX_IRQ_EDGE;
86                         break;
87                 case (IXP4XX_GPIO_FALLING_EDGE):
88                         int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
89                         irq_type = IXP4XX_IRQ_EDGE;
90                         break;
91                 case (IXP4XX_GPIO_TRANSITIONAL):
92                         int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
93                         irq_type = IXP4XX_IRQ_EDGE;
94                         break;
95                 default:
96                         int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
97                         irq_type = IXP4XX_IRQ_LEVEL;
98                         break;
99                 }
100
101                 if (style & IXP4XX_GPIO_INTSTYLE_MASK)
102                         ixp4xx_config_irq(gpio2irq[line], irq_type);
103
104                 if (line >= 8) {        /* pins 8-15 */ 
105                         line -= 8;
106                         int_reg = IXP4XX_GPIO_GPIT2R;
107                 }
108                 else {                  /* pins 0-7 */
109                         int_reg = IXP4XX_GPIO_GPIT1R;
110                 }
111
112                 /* Clear the style for the appropriate pin */
113                 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR << 
114                                 (line * IXP4XX_GPIO_STYLE_SIZE));
115
116                 /* Set the new style */
117                 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
118         }
119
120         *IXP4XX_GPIO_GPOER = enable;
121 }
122
123 EXPORT_SYMBOL(gpio_line_config);
124
125 /*************************************************************************
126  * IXP4xx chipset I/O mapping
127  *************************************************************************/
128 static struct map_desc ixp4xx_io_desc[] __initdata = {
129         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
130                 .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
131                 .physical       = IXP4XX_PERIPHERAL_BASE_PHYS,
132                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
133                 .type           = MT_DEVICE
134         }, {    /* Expansion Bus Config Registers */
135                 .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
136                 .physical       = IXP4XX_EXP_CFG_BASE_PHYS,
137                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
138                 .type           = MT_DEVICE
139         }, {    /* PCI Registers */
140                 .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
141                 .physical       = IXP4XX_PCI_CFG_BASE_PHYS,
142                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
143                 .type           = MT_DEVICE
144         }
145 };
146
147 void __init ixp4xx_map_io(void)
148 {
149         iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
150 }
151
152
153 /*************************************************************************
154  * IXP4xx chipset IRQ handling
155  *
156  * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
157  *       (be it PCI or something else) configures that GPIO line
158  *       as an IRQ.
159  **************************************************************************/
160 static void ixp4xx_irq_mask(unsigned int irq)
161 {
162         if (cpu_is_ixp46x() && irq >= 32)
163                 *IXP4XX_ICMR2 &= ~(1 << (irq - 32));
164         else
165                 *IXP4XX_ICMR &= ~(1 << irq);
166 }
167
168 static void ixp4xx_irq_unmask(unsigned int irq)
169 {
170         if (cpu_is_ixp46x() && irq >= 32)
171                 *IXP4XX_ICMR2 |= (1 << (irq - 32));
172         else
173                 *IXP4XX_ICMR |= (1 << irq);
174 }
175
176 static void ixp4xx_irq_ack(unsigned int irq)
177 {
178         static int irq2gpio[32] = {
179                 -1, -1, -1, -1, -1, -1,  0,  1,
180                 -1, -1, -1, -1, -1, -1, -1, -1,
181                 -1, -1, -1,  2,  3,  4,  5,  6,
182                  7,  8,  9, 10, 11, 12, -1, -1,
183         };
184         int line = (irq < 32) ? irq2gpio[irq] : -1;
185
186         if (line >= 0)
187                 gpio_line_isr_clear(line);
188 }
189
190 /*
191  * Level triggered interrupts on GPIO lines can only be cleared when the
192  * interrupt condition disappears.
193  */
194 static void ixp4xx_irq_level_unmask(unsigned int irq)
195 {
196         ixp4xx_irq_ack(irq);
197         ixp4xx_irq_unmask(irq);
198 }
199
200 static struct irqchip ixp4xx_irq_level_chip = {
201         .ack    = ixp4xx_irq_mask,
202         .mask   = ixp4xx_irq_mask,
203         .unmask = ixp4xx_irq_level_unmask,
204 };
205
206 static struct irqchip ixp4xx_irq_edge_chip = {
207         .ack    = ixp4xx_irq_ack,
208         .mask   = ixp4xx_irq_mask,
209         .unmask = ixp4xx_irq_unmask,
210 };
211
212 static void ixp4xx_config_irq(unsigned irq, enum ixp4xx_irq_type type)
213 {
214         switch (type) {
215         case IXP4XX_IRQ_LEVEL:
216                 set_irq_chip(irq, &ixp4xx_irq_level_chip);
217                 set_irq_handler(irq, do_level_IRQ);
218                 break;
219         case IXP4XX_IRQ_EDGE:
220                 set_irq_chip(irq, &ixp4xx_irq_edge_chip);
221                 set_irq_handler(irq, do_edge_IRQ);
222                 break;
223         }
224         set_irq_flags(irq, IRQF_VALID);
225 }
226
227 void __init ixp4xx_init_irq(void)
228 {
229         int i = 0;
230
231         /* Route all sources to IRQ instead of FIQ */
232         *IXP4XX_ICLR = 0x0;
233
234         /* Disable all interrupt */
235         *IXP4XX_ICMR = 0x0; 
236
237         if (cpu_is_ixp46x()) {
238                 /* Route upper 32 sources to IRQ instead of FIQ */
239                 *IXP4XX_ICLR2 = 0x00;
240
241                 /* Disable upper 32 interrupts */
242                 *IXP4XX_ICMR2 = 0x00;
243         }
244
245         /* Default to all level triggered */
246         for(i = 0; i < NR_IRQS; i++)
247                 ixp4xx_config_irq(i, IXP4XX_IRQ_LEVEL);
248 }
249
250
251 /*************************************************************************
252  * IXP4xx timer tick
253  * We use OS timer1 on the CPU for the timer tick and the timestamp 
254  * counter as a source of real clock ticks to account for missed jiffies.
255  *************************************************************************/
256
257 static unsigned volatile last_jiffy_time;
258
259 #define CLOCK_TICKS_PER_USEC    ((CLOCK_TICK_RATE + USEC_PER_SEC/2) / USEC_PER_SEC)
260
261 /* IRQs are disabled before entering here from do_gettimeofday() */
262 static unsigned long ixp4xx_gettimeoffset(void)
263 {
264         u32 elapsed;
265
266         elapsed = *IXP4XX_OSTS - last_jiffy_time;
267
268         return elapsed / CLOCK_TICKS_PER_USEC;
269 }
270
271 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
272 {
273         write_seqlock(&xtime_lock);
274
275         /* Clear Pending Interrupt by writing '1' to it */
276         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
277
278         /*
279          * Catch up with the real idea of time
280          */
281         while ((*IXP4XX_OSTS - last_jiffy_time) > LATCH) {
282                 timer_tick(regs);
283                 last_jiffy_time += LATCH;
284         }
285
286         write_sequnlock(&xtime_lock);
287
288         return IRQ_HANDLED;
289 }
290
291 static struct irqaction ixp4xx_timer_irq = {
292         .name           = "IXP4xx Timer Tick",
293         .flags          = SA_INTERRUPT,
294         .handler        = ixp4xx_timer_interrupt
295 };
296
297 static void __init ixp4xx_timer_init(void)
298 {
299         /* Clear Pending Interrupt by writing '1' to it */
300         *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
301
302         /* Setup the Timer counter value */
303         *IXP4XX_OSRT1 = (LATCH & ~IXP4XX_OST_RELOAD_MASK) | IXP4XX_OST_ENABLE;
304
305         /* Reset time-stamp counter */
306         *IXP4XX_OSTS = 0;
307         last_jiffy_time = 0;
308
309         /* Connect the interrupt handler and enable the interrupt */
310         setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
311 }
312
313 struct sys_timer ixp4xx_timer = {
314         .init           = ixp4xx_timer_init,
315         .offset         = ixp4xx_gettimeoffset,
316 };
317
318 static struct resource ixp46x_i2c_resources[] = {
319         [0] = {
320                 .start  = 0xc8011000,
321                 .end    = 0xc801101c,
322                 .flags  = IORESOURCE_MEM,
323         },
324         [1] = {
325                 .start  = IRQ_IXP4XX_I2C,
326                 .end    = IRQ_IXP4XX_I2C,
327                 .flags  = IORESOURCE_IRQ
328         }
329 };
330
331 /*
332  * I2C controller. The IXP46x uses the same block as the IOP3xx, so
333  * we just use the same device name.
334  */
335 static struct platform_device ixp46x_i2c_controller = {
336         .name           = "IOP3xx-I2C",
337         .id             = 0,
338         .num_resources  = 2,
339         .resource       = ixp46x_i2c_resources
340 };
341
342 static struct platform_device *ixp46x_devices[] __initdata = {
343         &ixp46x_i2c_controller
344 };
345
346 void __init ixp4xx_sys_init(void)
347 {
348         if (cpu_is_ixp46x()) {
349                 platform_add_devices(ixp46x_devices,
350                                 ARRAY_SIZE(ixp46x_devices));
351         }
352 }
353