Linux-2.6.12-rc2
[linux-3.10.git] / arch / arm / mach-ixp2000 / ixdp2x01.c
1 /*
2  * arch/arm/mach-ixp2000/ixdp2x01.c
3  *
4  * Code common to Intel IXDP2401 and IXDP2801 platforms
5  *
6  * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com>
7  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8  *
9  * Copyright (C) 2002-2003 Intel Corp.
10  * Copyright (C) 2003-2004 MontaVista Software, Inc.
11  *
12  *  This program is free software; you can redistribute  it and/or modify it
13  *  under  the terms of  the GNU General  Public License as published by the
14  *  Free Software Foundation;  either version 2 of the  License, or (at your
15  *  option) any later version.
16  */
17
18 #include <linux/config.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/mm.h>
22 #include <linux/sched.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/pci.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/delay.h>
29 #include <linux/serial.h>
30 #include <linux/tty.h>
31 #include <linux/serial_core.h>
32 #include <linux/device.h>
33
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/pgtable.h>
37 #include <asm/page.h>
38 #include <asm/system.h>
39 #include <asm/hardware.h>
40 #include <asm/mach-types.h>
41
42 #include <asm/mach/pci.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
46 #include <asm/mach/arch.h>
47 #include <asm/mach/flash.h>
48
49 /*************************************************************************
50  * IXDP2x01 IRQ Handling
51  *************************************************************************/
52 static void ixdp2x01_irq_mask(unsigned int irq)
53 {
54         ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG,
55                                 IXP2000_BOARD_IRQ_MASK(irq));
56 }
57
58 static void ixdp2x01_irq_unmask(unsigned int irq)
59 {
60         ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG,
61                                 IXP2000_BOARD_IRQ_MASK(irq));
62 }
63
64 static u32 valid_irq_mask;
65
66 static void ixdp2x01_irq_handler(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
67 {
68         u32 ex_interrupt;
69         int i;
70
71         desc->chip->mask(irq);
72
73         ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask;
74
75         if (!ex_interrupt) {
76                 printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n");
77                 return;
78         }
79
80         for (i = 0; i < IXP2000_BOARD_IRQS; i++) {
81                 if (ex_interrupt & (1 << i)) {
82                         struct irqdesc *cpld_desc;
83                         int cpld_irq = IXP2000_BOARD_IRQ(0) + i;
84                         cpld_desc = irq_desc + cpld_irq;
85                         cpld_desc->handle(cpld_irq, cpld_desc, regs);
86                 }
87         }
88
89         desc->chip->unmask(irq);
90 }
91
92 static struct irqchip ixdp2x01_irq_chip = {
93         .mask   = ixdp2x01_irq_mask,
94         .ack    = ixdp2x01_irq_mask,
95         .unmask = ixdp2x01_irq_unmask
96 };
97
98 /*
99  * We only do anything if we are the master NPU on the board.
100  * The slave NPU only has the ethernet chip going directly to
101  * the PCIB interrupt input.
102  */
103 void __init ixdp2x01_init_irq(void)
104 {
105         int irq = 0;
106
107         /* initialize chip specific interrupts */
108         ixp2000_init_irq();
109
110         if (machine_is_ixdp2401())
111                 valid_irq_mask = IXDP2401_VALID_IRQ_MASK;
112         else
113                 valid_irq_mask = IXDP2801_VALID_IRQ_MASK;
114
115         /* Mask all interrupts from CPLD, disable simulation */
116         ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff);
117         ixp2000_reg_write(IXDP2X01_INT_SIM_REG, 0);
118
119         for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
120                 if (irq & valid_irq_mask) {
121                         set_irq_chip(irq, &ixdp2x01_irq_chip);
122                         set_irq_handler(irq, do_level_IRQ);
123                         set_irq_flags(irq, IRQF_VALID);
124                 } else {
125                         set_irq_flags(irq, 0);
126                 }
127         }
128
129         /* Hook into PCI interrupts */
130         set_irq_chained_handler(IRQ_IXP2000_PCIB, &ixdp2x01_irq_handler);
131 }
132
133
134 /*************************************************************************
135  * IXDP2x01 memory map and serial ports
136  *************************************************************************/
137 static struct map_desc ixdp2x01_io_desc __initdata = {
138         .virtual        = IXDP2X01_VIRT_CPLD_BASE, 
139         .physical       = IXDP2X01_PHYS_CPLD_BASE,
140         .length         = IXDP2X01_CPLD_REGION_SIZE,
141         .type           = MT_DEVICE
142 };
143
144 static struct uart_port ixdp2x01_serial_ports[2] = {
145         {
146                 .membase        = (char *)(IXDP2X01_UART1_VIRT_BASE),
147                 .mapbase        = (unsigned long)IXDP2X01_UART1_PHYS_BASE,
148                 .irq            = IRQ_IXDP2X01_UART1,
149                 .flags          = UPF_SKIP_TEST,
150                 .iotype         = UPIO_MEM32,
151                 .regshift       = 2,
152                 .uartclk        = IXDP2X01_UART_CLK,
153                 .line           = 1,
154                 .type           = PORT_16550A,
155                 .fifosize       = 16
156         }, {
157                 .membase        = (char *)(IXDP2X01_UART2_VIRT_BASE),
158                 .mapbase        = (unsigned long)IXDP2X01_UART2_PHYS_BASE,
159                 .irq            = IRQ_IXDP2X01_UART2,
160                 .flags          = UPF_SKIP_TEST,
161                 .iotype         = UPIO_MEM32,
162                 .regshift       = 2,
163                 .uartclk        = IXDP2X01_UART_CLK,
164                 .line           = 2,
165                 .type           = PORT_16550A,
166                 .fifosize       = 16
167         }, 
168 };
169
170 static void __init ixdp2x01_map_io(void)
171 {
172         ixp2000_map_io();       
173
174         iotable_init(&ixdp2x01_io_desc, 1);
175
176         early_serial_setup(&ixdp2x01_serial_ports[0]);
177         early_serial_setup(&ixdp2x01_serial_ports[1]);
178 }
179
180
181 /*************************************************************************
182  * IXDP2x01 timer tick configuration
183  *************************************************************************/
184 static unsigned int ixdp2x01_clock;
185
186 static int __init ixdp2x01_clock_setup(char *str)
187 {
188         ixdp2x01_clock = simple_strtoul(str, NULL, 10);
189
190         return 1;
191 }
192
193 __setup("ixdp2x01_clock=", ixdp2x01_clock_setup);
194
195 static void __init ixdp2x01_timer_init(void)
196 {
197         if (!ixdp2x01_clock)
198                 ixdp2x01_clock = 50000000;
199
200         ixp2000_init_time(ixdp2x01_clock);
201 }
202
203 static struct sys_timer ixdp2x01_timer = {
204         .init           = ixdp2x01_timer_init,
205         .offset         = ixp2000_gettimeoffset,
206 };
207
208 /*************************************************************************
209  * IXDP2x01 PCI
210  *************************************************************************/
211 void __init ixdp2x01_pci_preinit(void)
212 {
213         ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000);
214         ixp2000_pci_preinit();
215 }
216
217 #define DEVPIN(dev, pin) ((pin) | ((dev) << 3))
218
219 static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
220 {
221         u8 bus = dev->bus->number;
222         u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin);
223         struct pci_bus *tmp_bus = dev->bus;
224
225         /* Primary bus, no interrupts here */
226         if (bus == 0) {
227                 return -1;
228         }
229
230         /* Lookup first leaf in bus tree */
231         while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) {
232                 tmp_bus = tmp_bus->parent;
233         }
234
235         /* Select between known bridges */
236         switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) {
237         /* Device is located after first MB bridge */
238         case 0x0008:
239                 if (tmp_bus == dev->bus) {
240                         /* Device is located directy after first MB bridge */
241                         switch (devpin) {
242                         case DEVPIN(1, 1):      /* Onboard 82546 ch 0 */
243                                 if (machine_is_ixdp2401())
244                                         return IRQ_IXDP2401_INTA_82546;
245                                 return -1;
246                         case DEVPIN(1, 2):      /* Onboard 82546 ch 1 */
247                                 if (machine_is_ixdp2401())
248                                         return IRQ_IXDP2401_INTB_82546;
249                                 return -1;
250                         case DEVPIN(0, 1):      /* PMC INTA# */
251                                 return IRQ_IXDP2X01_SPCI_PMC_INTA;
252                         case DEVPIN(0, 2):      /* PMC INTB# */
253                                 return IRQ_IXDP2X01_SPCI_PMC_INTB;
254                         case DEVPIN(0, 3):      /* PMC INTC# */
255                                 return IRQ_IXDP2X01_SPCI_PMC_INTC;
256                         case DEVPIN(0, 4):      /* PMC INTD# */
257                                 return IRQ_IXDP2X01_SPCI_PMC_INTD;
258                         }
259                 }
260                 break;
261         case 0x0010:
262                 if (tmp_bus == dev->bus) {
263                         /* Device is located directy after second MB bridge */
264                         /* Secondary bus of second bridge */
265                         switch (devpin) {
266                         case DEVPIN(0, 1):      /* DB#0 */
267                                 return IRQ_IXDP2X01_SPCI_DB_0;
268                         case DEVPIN(1, 1):      /* DB#1 */
269                                 return IRQ_IXDP2X01_SPCI_DB_1;
270                         }
271                 } else {
272                         /* Device is located indirectly after second MB bridge */
273                         /* Not supported now */
274                 }
275                 break;
276         }
277
278         return -1;
279 }
280
281
282 static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys)
283 {
284         sys->mem_offset = 0xe0000000;
285
286         if (machine_is_ixdp2801())
287                 sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16);
288
289         return ixp2000_pci_setup(nr, sys);
290 }
291
292 struct hw_pci ixdp2x01_pci __initdata = {
293         .nr_controllers = 1,
294         .setup          = ixdp2x01_pci_setup,
295         .preinit        = ixdp2x01_pci_preinit,
296         .scan           = ixp2000_pci_scan_bus,
297         .map_irq        = ixdp2x01_pci_map_irq,
298 };
299
300 int __init ixdp2x01_pci_init(void)
301 {
302
303         pci_common_init(&ixdp2x01_pci);
304         return 0;
305 }
306
307 subsys_initcall(ixdp2x01_pci_init);
308
309 /*************************************************************************
310  * IXDP2x01 Machine Intialization
311  *************************************************************************/
312 static struct flash_platform_data ixdp2x01_flash_platform_data = {
313         .map_name       = "cfi_probe",
314         .width          = 1,
315 };
316
317 static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs)
318 {
319         ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
320                 ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN));
321         return (ofs & IXDP2X01_FLASH_WINDOW_MASK);
322 }
323
324 static struct ixp2000_flash_data ixdp2x01_flash_data = {
325         .platform_data  = &ixdp2x01_flash_platform_data,
326         .bank_setup     = ixdp2x01_flash_bank_setup
327 };
328
329 static struct resource ixdp2x01_flash_resource = {
330         .start          = 0xc4000000,
331         .end            = 0xc4000000 + 0x01ffffff,
332         .flags          = IORESOURCE_MEM,
333 };
334
335 static struct platform_device ixdp2x01_flash = {
336         .name           = "IXP2000-Flash",
337         .id             = 0,
338         .dev            = {
339                 .platform_data = &ixdp2x01_flash_data,
340         },
341         .num_resources  = 1,
342         .resource       = &ixdp2x01_flash_resource,
343 };
344
345 static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = {
346         .sda_pin        = IXDP2X01_GPIO_SDA,
347         .scl_pin        = IXDP2X01_GPIO_SCL,
348 };
349
350 static struct platform_device ixdp2x01_i2c_controller = {
351         .name           = "IXP2000-I2C",
352         .id             = 0,
353         .dev            = {
354                 .platform_data = &ixdp2x01_i2c_gpio_pins,
355         },
356         .num_resources  = 0
357 };
358
359 static struct platform_device *ixdp2x01_devices[] __initdata = {
360         &ixdp2x01_flash,
361         &ixdp2x01_i2c_controller
362 };
363
364 static void __init ixdp2x01_init_machine(void)
365 {
366         ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG,
367                 (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN));
368         
369         ixdp2x01_flash_data.nr_banks =
370                 ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1);
371
372         platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices));
373 }
374
375
376 #ifdef CONFIG_ARCH_IXDP2401
377 MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
378         MAINTAINER("MontaVista Software, Inc.")
379         BOOT_MEM(0x00000000, IXP2000_UART_PHYS_BASE, IXP2000_UART_VIRT_BASE)
380         BOOT_PARAMS(0x00000100)
381         MAPIO(ixdp2x01_map_io)
382         INITIRQ(ixdp2x01_init_irq)
383         .timer          = &ixdp2x01_timer,
384         INIT_MACHINE(ixdp2x01_init_machine)
385 MACHINE_END
386 #endif
387
388 #ifdef CONFIG_ARCH_IXDP2801
389 MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
390         MAINTAINER("MontaVista Software, Inc.")
391         BOOT_MEM(0x00000000, IXP2000_UART_PHYS_BASE, IXP2000_UART_VIRT_BASE)
392         BOOT_PARAMS(0x00000100)
393         MAPIO(ixdp2x01_map_io)
394         INITIRQ(ixdp2x01_init_irq)
395         .timer          = &ixdp2x01_timer,
396         INIT_MACHINE(ixdp2x01_init_machine)
397 MACHINE_END
398 #endif
399
400