rtc: mxc_rtc: remove cpu_is_xxx by using platform_device_id
[linux-3.10.git] / arch / arm / mach-imx / clk-imx27.c
1 #include <linux/clk.h>
2 #include <linux/io.h>
3 #include <linux/module.h>
4 #include <linux/clkdev.h>
5 #include <linux/err.h>
6 #include <linux/clk-provider.h>
7 #include <linux/of.h>
8
9 #include <mach/hardware.h>
10
11 #include "clk.h"
12 #include "common.h"
13
14 #define IO_ADDR_CCM(off)        (MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR + (off)))
15
16 /* Register offsets */
17 #define CCM_CSCR                IO_ADDR_CCM(0x0)
18 #define CCM_MPCTL0              IO_ADDR_CCM(0x4)
19 #define CCM_MPCTL1              IO_ADDR_CCM(0x8)
20 #define CCM_SPCTL0              IO_ADDR_CCM(0xc)
21 #define CCM_SPCTL1              IO_ADDR_CCM(0x10)
22 #define CCM_OSC26MCTL           IO_ADDR_CCM(0x14)
23 #define CCM_PCDR0               IO_ADDR_CCM(0x18)
24 #define CCM_PCDR1               IO_ADDR_CCM(0x1c)
25 #define CCM_PCCR0               IO_ADDR_CCM(0x20)
26 #define CCM_PCCR1               IO_ADDR_CCM(0x24)
27 #define CCM_CCSR                IO_ADDR_CCM(0x28)
28 #define CCM_PMCTL               IO_ADDR_CCM(0x2c)
29 #define CCM_PMCOUNT             IO_ADDR_CCM(0x30)
30 #define CCM_WKGDCTL             IO_ADDR_CCM(0x34)
31
32 #define CCM_CSCR_UPDATE_DIS     (1 << 31)
33 #define CCM_CSCR_SSI2           (1 << 23)
34 #define CCM_CSCR_SSI1           (1 << 22)
35 #define CCM_CSCR_VPU            (1 << 21)
36 #define CCM_CSCR_MSHC           (1 << 20)
37 #define CCM_CSCR_SPLLRES        (1 << 19)
38 #define CCM_CSCR_MPLLRES        (1 << 18)
39 #define CCM_CSCR_SP             (1 << 17)
40 #define CCM_CSCR_MCU            (1 << 16)
41 #define CCM_CSCR_OSC26MDIV      (1 << 4)
42 #define CCM_CSCR_OSC26M         (1 << 3)
43 #define CCM_CSCR_FPM            (1 << 2)
44 #define CCM_CSCR_SPEN           (1 << 1)
45 #define CCM_CSCR_MPEN           (1 << 0)
46
47 /* i.MX27 TO 2+ */
48 #define CCM_CSCR_ARM_SRC        (1 << 15)
49
50 #define CCM_SPCTL1_LF           (1 << 15)
51 #define CCM_SPCTL1_BRMO         (1 << 6)
52
53 static const char *vpu_sel_clks[] = { "spll", "mpll_main2", };
54 static const char *cpu_sel_clks[] = { "mpll_main2", "mpll", };
55 static const char *clko_sel_clks[] = {
56         "ckil", "prem", "ckih", "ckih",
57         "ckih", "mpll", "spll", "cpu_div",
58         "ahb", "ipg", "per1_div", "per2_div",
59         "per3_div", "per4_div", "ssi1_div", "ssi2_div",
60         "nfc_div", "mshc_div", "vpu_div", "60m",
61         "32k", "usb_div", "dptc",
62 };
63
64 static const char *ssi_sel_clks[] = { "spll", "mpll", };
65
66 enum mx27_clks {
67         dummy, ckih, ckil, mpll, spll, mpll_main2, ahb, ipg, nfc_div, per1_div,
68         per2_div, per3_div, per4_div, vpu_sel, vpu_div, usb_div, cpu_sel,
69         clko_sel, cpu_div, clko_div, ssi1_sel, ssi2_sel, ssi1_div, ssi2_div,
70         clko_en, ssi2_ipg_gate, ssi1_ipg_gate, slcdc_ipg_gate, sdhc3_ipg_gate,
71         sdhc2_ipg_gate, sdhc1_ipg_gate, scc_ipg_gate, sahara_ipg_gate,
72         rtc_ipg_gate, pwm_ipg_gate, owire_ipg_gate, lcdc_ipg_gate,
73         kpp_ipg_gate, iim_ipg_gate, i2c2_ipg_gate, i2c1_ipg_gate,
74         gpt6_ipg_gate, gpt5_ipg_gate, gpt4_ipg_gate, gpt3_ipg_gate,
75         gpt2_ipg_gate, gpt1_ipg_gate, gpio_ipg_gate, fec_ipg_gate,
76         emma_ipg_gate, dma_ipg_gate, cspi3_ipg_gate, cspi2_ipg_gate,
77         cspi1_ipg_gate, nfc_baud_gate, ssi2_baud_gate, ssi1_baud_gate,
78         vpu_baud_gate, per4_gate, per3_gate, per2_gate, per1_gate,
79         usb_ahb_gate, slcdc_ahb_gate, sahara_ahb_gate, lcdc_ahb_gate,
80         vpu_ahb_gate, fec_ahb_gate, emma_ahb_gate, emi_ahb_gate, dma_ahb_gate,
81         csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
82         uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
83         uart2_ipg_gate, uart1_ipg_gate, clk_max
84 };
85
86 static struct clk *clk[clk_max];
87
88 int __init mx27_clocks_init(unsigned long fref)
89 {
90         int i;
91
92         clk[dummy] = imx_clk_fixed("dummy", 0);
93         clk[ckih] = imx_clk_fixed("ckih", fref);
94         clk[ckil] = imx_clk_fixed("ckil", 32768);
95         clk[mpll] = imx_clk_pllv1("mpll", "ckih", CCM_MPCTL0);
96         clk[spll] = imx_clk_pllv1("spll", "ckih", CCM_SPCTL0);
97         clk[mpll_main2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3);
98
99         if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
100                 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2);
101                 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2);
102         } else {
103                 clk[ahb] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4);
104                 clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
105         }
106
107         clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
108         clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
109         clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
110         clk[per3_div] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6);
111         clk[per4_div] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6);
112         clk[vpu_sel] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks));
113         clk[vpu_div] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 3);
114         clk[usb_div] = imx_clk_divider("usb_div", "spll", CCM_CSCR, 28, 3);
115         clk[cpu_sel] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks));
116         clk[clko_sel] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
117         if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
118                 clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2);
119         else
120                 clk[cpu_div] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3);
121         clk[clko_div] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3);
122         clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
123         clk[ssi2_sel] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks));
124         clk[ssi1_div] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6);
125         clk[ssi2_div] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 3);
126         clk[clko_en] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0);
127         clk[ssi2_ipg_gate] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0);
128         clk[ssi1_ipg_gate] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1);
129         clk[slcdc_ipg_gate] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2);
130         clk[sdhc3_ipg_gate] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3);
131         clk[sdhc2_ipg_gate] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4);
132         clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
133         clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
134         clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
135         clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
136         clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
137         clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
138         clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
139         clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
140         clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
141         clk[i2c2_ipg_gate] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17);
142         clk[i2c1_ipg_gate] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18);
143         clk[gpt6_ipg_gate] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19);
144         clk[gpt5_ipg_gate] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20);
145         clk[gpt4_ipg_gate] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21);
146         clk[gpt3_ipg_gate] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22);
147         clk[gpt2_ipg_gate] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23);
148         clk[gpt1_ipg_gate] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24);
149         clk[gpio_ipg_gate] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25);
150         clk[fec_ipg_gate] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26);
151         clk[emma_ipg_gate] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27);
152         clk[dma_ipg_gate] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28);
153         clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
154         clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
155         clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
156         clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
157         clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
158         clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
159         clk[vpu_baud_gate] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1,  6);
160         clk[per4_gate] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1,  7);
161         clk[per3_gate] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1,  8);
162         clk[per2_gate] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1,  9);
163         clk[per1_gate] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10);
164         clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
165         clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
166         clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
167         clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
168         clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
169         clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
170         clk[emma_ahb_gate] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18);
171         clk[emi_ahb_gate] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19);
172         clk[dma_ahb_gate] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20);
173         clk[csi_ahb_gate] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21);
174         clk[brom_ahb_gate] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22);
175         clk[ata_ahb_gate] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23);
176         clk[wdog_ipg_gate] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24);
177         clk[usb_ipg_gate] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25);
178         clk[uart6_ipg_gate] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26);
179         clk[uart5_ipg_gate] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27);
180         clk[uart4_ipg_gate] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28);
181         clk[uart3_ipg_gate] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29);
182         clk[uart2_ipg_gate] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30);
183         clk[uart1_ipg_gate] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31);
184
185         for (i = 0; i < ARRAY_SIZE(clk); i++)
186                 if (IS_ERR(clk[i]))
187                         pr_err("i.MX27 clk %d: register failed with %ld\n",
188                                 i, PTR_ERR(clk[i]));
189
190         clk_register_clkdev(clk[uart1_ipg_gate], "ipg", "imx21-uart.0");
191         clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.0");
192         clk_register_clkdev(clk[uart2_ipg_gate], "ipg", "imx21-uart.1");
193         clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.1");
194         clk_register_clkdev(clk[uart3_ipg_gate], "ipg", "imx21-uart.2");
195         clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.2");
196         clk_register_clkdev(clk[uart4_ipg_gate], "ipg", "imx21-uart.3");
197         clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.3");
198         clk_register_clkdev(clk[uart5_ipg_gate], "ipg", "imx21-uart.4");
199         clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.4");
200         clk_register_clkdev(clk[uart6_ipg_gate], "ipg", "imx21-uart.5");
201         clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
202         clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
203         clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
204         clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
205         clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1");
206         clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
207         clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2");
208         clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3");
209         clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3");
210         clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4");
211         clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
212         clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
213         clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
214         clk_register_clkdev(clk[pwm_ipg_gate], NULL, "mxc_pwm.0");
215         clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.0");
216         clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "mxc-mmc.0");
217         clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.1");
218         clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.1");
219         clk_register_clkdev(clk[per2_gate], "per", "mxc-mmc.2");
220         clk_register_clkdev(clk[sdhc2_ipg_gate], "ipg", "mxc-mmc.2");
221         clk_register_clkdev(clk[cspi1_ipg_gate], NULL, "imx27-cspi.0");
222         clk_register_clkdev(clk[cspi2_ipg_gate], NULL, "imx27-cspi.1");
223         clk_register_clkdev(clk[cspi3_ipg_gate], NULL, "imx27-cspi.2");
224         clk_register_clkdev(clk[per3_gate], "per", "imx-fb.0");
225         clk_register_clkdev(clk[lcdc_ipg_gate], "ipg", "imx-fb.0");
226         clk_register_clkdev(clk[lcdc_ahb_gate], "ahb", "imx-fb.0");
227         clk_register_clkdev(clk[csi_ahb_gate], "ahb", "mx2-camera.0");
228         clk_register_clkdev(clk[usb_div], "per", "fsl-usb2-udc");
229         clk_register_clkdev(clk[usb_ipg_gate], "ipg", "fsl-usb2-udc");
230         clk_register_clkdev(clk[usb_ahb_gate], "ahb", "fsl-usb2-udc");
231         clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
232         clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.0");
233         clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.0");
234         clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1");
235         clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.1");
236         clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.1");
237         clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
238         clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
239         clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
240         clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
241         clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
242         clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
243         clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
244         clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
245         clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx-dma");
246         clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx-dma");
247         clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
248         clk_register_clkdev(clk[fec_ahb_gate], "ahb", "imx27-fec.0");
249         clk_register_clkdev(clk[wdog_ipg_gate], NULL, "imx2-wdt.0");
250         clk_register_clkdev(clk[i2c1_ipg_gate], NULL, "imx21-i2c.0");
251         clk_register_clkdev(clk[i2c2_ipg_gate], NULL, "imx21-i2c.1");
252         clk_register_clkdev(clk[owire_ipg_gate], NULL, "mxc_w1.0");
253         clk_register_clkdev(clk[kpp_ipg_gate], NULL, "imx-keypad");
254         clk_register_clkdev(clk[emma_ahb_gate], "emma-ahb", "mx2-camera.0");
255         clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "mx2-camera.0");
256         clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
257         clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
258         clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
259         clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
260         clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
261         clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
262         clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
263         clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
264         clk_register_clkdev(clk[cpu_div], "cpu", NULL);
265         clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
266         clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
267         clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
268
269         mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
270
271         clk_prepare_enable(clk[emi_ahb_gate]);
272
273         imx_print_silicon_rev("i.MX27", mx27_revision());
274
275         return 0;
276 }
277
278 #ifdef CONFIG_OF
279 int __init mx27_clocks_init_dt(void)
280 {
281         struct device_node *np;
282         u32 fref = 26000000; /* default */
283
284         for_each_compatible_node(np, NULL, "fixed-clock") {
285                 if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
286                         continue;
287
288                 if (!of_property_read_u32(np, "clock-frequency", &fref))
289                         break;
290         }
291
292         return mx27_clocks_init(fref);
293 }
294 #endif