arch/arm/mach-davinci/cpuidle.c

   1 /*
   2  * CPU idle for DaVinci SoCs
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
   5  *
   6  * Derived from Marvell Kirkwood CPU idle code
   7  * (arch/arm/mach-kirkwood/cpuidle.c)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/cpuidle.h>
  18 #include <linux/io.h>
  19 #include <asm/proc-fns.h>
  20
  21 #include <mach/cpuidle.h>
  22 #include <mach/memory.h>
  23
  24 #define DAVINCI_CPUIDLE_MAX_STATES      2
  25
  26 struct davinci_ops {
  27         void (*enter) (u32 flags);
  28         void (*exit) (u32 flags);
  29         u32 flags;
  30 };
  31
  32 /* fields in davinci_ops.flags */
  33 #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
  34
  35 static struct cpuidle_driver davinci_idle_driver = {
  36         .name   = "cpuidle-davinci",
  37         .owner  = THIS_MODULE,
  38 };
  39
  40 static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
  41 static void __iomem *ddr2_reg_base;
  42
  43 static void davinci_save_ddr_power(int enter, bool pdown)
  44 {
  45         u32 val;
  46
  47         val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
  48
  49         if (enter) {
  50                 if (pdown)
  51                         val |= DDR2_SRPD_BIT;
  52                 else
  53                         val &= ~DDR2_SRPD_BIT;
  54                 val |= DDR2_LPMODEN_BIT;
  55         } else {
  56                 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
  57         }
  58
  59         __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
  60 }
  61
  62 static void davinci_c2state_enter(u32 flags)
  63 {
  64         davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
  65 }
  66
  67 static void davinci_c2state_exit(u32 flags)
  68 {
  69         davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
  70 }
  71
  72 static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
  73         [1] = {
  74                 .enter  = davinci_c2state_enter,
  75                 .exit   = davinci_c2state_exit,
  76         },
  77 };
  78
  79 /* Actual code that puts the SoC in different idle states */
  80 static int davinci_enter_idle(struct cpuidle_device *dev,
  81                                                 int index)
  82 {
  83         struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
  84         struct davinci_ops *ops = cpuidle_get_statedata(state_usage);
  85         struct timeval before, after;
  86         int idle_time;
  87
  88         local_irq_disable();
  89         do_gettimeofday(&before);
  90
  91         if (ops && ops->enter)
  92                 ops->enter(ops->flags);
  93         /* Wait for interrupt state */
  94         cpu_do_idle();
  95         if (ops && ops->exit)
  96                 ops->exit(ops->flags);
  97
  98         do_gettimeofday(&after);
  99         local_irq_enable();
 100         idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
 101                         (after.tv_usec - before.tv_usec);
 102
 103         dev->last_residency = idle_time;
 104
 105         return index;
 106 }
 107
 108 static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 109 {
 110         int ret;
 111         struct cpuidle_device *device;
 112         struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
 113
 114         device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
 115
 116         if (!pdata) {
 117                 dev_err(&pdev->dev, "cannot get platform data\n");
 118                 return -ENOENT;
 119         }
 120
 121         ddr2_reg_base = pdata->ddr2_ctlr_base;
 122
 123         ret = cpuidle_register_driver(&davinci_idle_driver);
 124         if (ret) {
 125                 dev_err(&pdev->dev, "failed to register driver\n");
 126                 return ret;
 127         }
 128
 129         /* Wait for interrupt state */
 130         device->states[0].enter = davinci_enter_idle;
 131         device->states[0].exit_latency = 1;
 132         device->states[0].target_residency = 10000;
 133         device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
 134         strcpy(device->states[0].name, "WFI");
 135         strcpy(device->states[0].desc, "Wait for interrupt");
 136
 137         /* Wait for interrupt and DDR self refresh state */
 138         device->states[1].enter = davinci_enter_idle;
 139         device->states[1].exit_latency = 10;
 140         device->states[1].target_residency = 10000;
 141         device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
 142         strcpy(device->states[1].name, "DDR SR");
 143         strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
 144         if (pdata->ddr2_pdown)
 145                 davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
 146         cpuidle_set_statedata(&device->states_usage[1], &davinci_states[1]);
 147
 148         device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
 149
 150         ret = cpuidle_register_device(device);
 151         if (ret) {
 152                 dev_err(&pdev->dev, "failed to register device\n");
 153                 cpuidle_unregister_driver(&davinci_idle_driver);
 154                 return ret;
 155         }
 156
 157         return 0;
 158 }
 159
 160 static struct platform_driver davinci_cpuidle_driver = {
 161         .driver = {
 162                 .name   = "cpuidle-davinci",
 163                 .owner  = THIS_MODULE,
 164         },
 165 };
 166
 167 static int __init davinci_cpuidle_init(void)
 168 {
 169         return platform_driver_probe(&davinci_cpuidle_driver,
 170                                                 davinci_cpuidle_probe);
 171 }
 172 device_initcall(davinci_cpuidle_init);
 173