2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
25 #include "entry-header.S"
28 * Interrupt handling. Preserves r7, r8, r9
31 get_irqnr_preamble r5, lr
32 1: get_irqnr_and_base r0, r6, r5, lr
35 @ routine called with r0 = irq number, r1 = struct pt_regs *
44 * this macro assumes that irqstat (r6) and base (r5) are
45 * preserved from get_irqnr_and_base above
47 test_for_ipi r0, r6, r5, lr
52 #ifdef CONFIG_LOCAL_TIMERS
53 test_for_ltirq r0, r6, r5, lr
63 .section .kprobes.text,"ax",%progbits
69 * Invalid mode handlers
71 .macro inv_entry, reason
72 sub sp, sp, #S_FRAME_SIZE
73 ARM( stmib sp, {r1 - lr} )
74 THUMB( stmia sp, {r0 - r12} )
75 THUMB( str sp, [sp, #S_SP] )
76 THUMB( str lr, [sp, #S_LR] )
81 inv_entry BAD_PREFETCH
83 ENDPROC(__pabt_invalid)
88 ENDPROC(__dabt_invalid)
93 ENDPROC(__irq_invalid)
96 inv_entry BAD_UNDEFINSTR
99 @ XXX fall through to common_invalid
103 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
109 add r0, sp, #S_PC @ here for interlock avoidance
110 mov r7, #-1 @ "" "" "" ""
111 str r4, [sp] @ save preserved r0
112 stmia r0, {r5 - r7} @ lr_<exception>,
113 @ cpsr_<exception>, "old_r0"
117 ENDPROC(__und_invalid)
123 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
124 #define SPFIX(code...) code
126 #define SPFIX(code...)
129 .macro svc_entry, stack_hole=0
131 UNWIND(.save {r0 - pc} )
132 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
133 #ifdef CONFIG_THUMB2_KERNEL
134 SPFIX( str r0, [sp] ) @ temporarily saved
136 SPFIX( tst r0, #4 ) @ test original stack alignment
137 SPFIX( ldr r0, [sp] ) @ restored
141 SPFIX( subeq sp, sp, #4 )
145 add r5, sp, #S_SP - 4 @ here for interlock avoidance
146 mov r4, #-1 @ "" "" "" ""
147 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
148 SPFIX( addeq r0, r0, #4 )
149 str r1, [sp, #-4]! @ save the "real" r0 copied
150 @ from the exception stack
155 @ We are now ready to fill in the remaining blanks on the stack:
159 @ r2 - lr_<exception>, already fixed up for correct return/restart
160 @ r3 - spsr_<exception>
161 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
171 @ get ready to re-enable interrupts if appropriate
175 biceq r9, r9, #PSR_I_BIT
178 @ Call the processor-specific abort handler:
180 @ r2 - aborted context pc
181 @ r3 - aborted context cpsr
183 @ The abort handler must return the aborted address in r0, and
184 @ the fault status register in r1. r9 must be preserved.
189 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
191 bl CPU_DABORT_HANDLER
195 @ set desired IRQ state, then call main handler
202 @ IRQs off again before pulling preserved data off the stack
207 @ restore SPSR and restart the instruction
210 svc_exit r2 @ return from exception
218 #ifdef CONFIG_TRACE_IRQFLAGS
219 bl trace_hardirqs_off
221 #ifdef CONFIG_PREEMPT
223 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
224 add r7, r8, #1 @ increment it
225 str r7, [tsk, #TI_PREEMPT]
229 #ifdef CONFIG_PREEMPT
230 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
231 ldr r0, [tsk, #TI_FLAGS] @ get flags
232 teq r8, #0 @ if preempt count != 0
233 movne r0, #0 @ force flags to 0
234 tst r0, #_TIF_NEED_RESCHED
237 ldr r4, [sp, #S_PSR] @ irqs are already disabled
238 #ifdef CONFIG_TRACE_IRQFLAGS
240 bleq trace_hardirqs_on
242 svc_exit r4 @ return from exception
248 #ifdef CONFIG_PREEMPT
251 1: bl preempt_schedule_irq @ irq en/disable is done inside
252 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
253 tst r0, #_TIF_NEED_RESCHED
254 moveq pc, r8 @ go again
260 #ifdef CONFIG_KPROBES
261 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
262 @ it obviously needs free stack space which then will belong to
270 @ call emulation code, which returns using r9 if it has emulated
271 @ the instruction, or the more conventional lr if we are to treat
272 @ this as a real undefined instruction
280 mov r0, sp @ struct pt_regs *regs
284 @ IRQs off again before pulling preserved data off the stack
289 @ restore SPSR and restart the instruction
291 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
292 svc_exit r2 @ return from exception
301 @ re-enable interrupts if appropriate
305 biceq r9, r9, #PSR_I_BIT
308 @ set args, then call main handler
310 @ r0 - address of faulting instruction
311 @ r1 - pointer to registers on stack
314 mov r0, r2 @ pass address of aborted instruction.
317 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
319 CPU_PABORT_HANDLER(r0, r2)
321 msr cpsr_c, r9 @ Maybe enable interrupts
323 bl do_PrefetchAbort @ call abort handler
326 @ IRQs off again before pulling preserved data off the stack
331 @ restore SPSR and restart the instruction
334 svc_exit r2 @ return from exception
351 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
354 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
355 #error "sizeof(struct pt_regs) must be a multiple of 8"
360 UNWIND(.cantunwind ) @ don't unwind the user space
361 sub sp, sp, #S_FRAME_SIZE
362 ARM( stmib sp, {r1 - r12} )
363 THUMB( stmia sp, {r0 - r12} )
366 add r0, sp, #S_PC @ here for interlock avoidance
367 mov r4, #-1 @ "" "" "" ""
369 str r1, [sp] @ save the "real" r0 copied
370 @ from the exception stack
373 @ We are now ready to fill in the remaining blanks on the stack:
375 @ r2 - lr_<exception>, already fixed up for correct return/restart
376 @ r3 - spsr_<exception>
377 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
379 @ Also, separately save sp_usr and lr_usr
382 ARM( stmdb r0, {sp, lr}^ )
383 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
386 @ Enable the alignment trap while in kernel mode
391 @ Clear FP to mark the first stack frame
396 .macro kuser_cmpxchg_check
397 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
399 #warning "NPTL on non MMU needs fixing"
401 @ Make sure our user space atomic helper is restarted
402 @ if it was interrupted in a critical region. Here we
403 @ perform a quick test inline since it should be false
404 @ 99.9999% of the time. The rest is done out of line.
406 blhs kuser_cmpxchg_fixup
417 @ Call the processor-specific abort handler:
419 @ r2 - aborted context pc
420 @ r3 - aborted context cpsr
422 @ The abort handler must return the aborted address in r0, and
423 @ the fault status register in r1.
428 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
430 bl CPU_DABORT_HANDLER
434 @ IRQs on, then call the main handler
438 adr lr, BSYM(ret_from_exception)
448 #ifdef CONFIG_TRACE_IRQFLAGS
449 bl trace_hardirqs_off
452 #ifdef CONFIG_PREEMPT
453 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
454 add r7, r8, #1 @ increment it
455 str r7, [tsk, #TI_PREEMPT]
459 #ifdef CONFIG_PREEMPT
460 ldr r0, [tsk, #TI_PREEMPT]
461 str r8, [tsk, #TI_PREEMPT]
463 ARM( strne r0, [r0, -r0] )
464 THUMB( movne r0, #0 )
465 THUMB( strne r0, [r0] )
467 #ifdef CONFIG_TRACE_IRQFLAGS
483 @ fall through to the emulation code, which returns using r9 if
484 @ it has emulated the instruction, or the more conventional lr
485 @ if we are to treat this as a real undefined instruction
489 adr r9, BSYM(ret_from_exception)
490 adr lr, BSYM(__und_usr_unknown)
491 tst r3, #PSR_T_BIT @ Thumb mode?
492 itet eq @ explicit IT needed for the 1f label
493 subeq r4, r2, #4 @ ARM instr at LR - 4
494 subne r4, r2, #2 @ Thumb instr at LR - 2
496 #ifdef CONFIG_CPU_ENDIAN_BE8
497 reveq r0, r0 @ little endian instruction
501 #if __LINUX_ARM_ARCH__ >= 7
503 ARM( ldrht r5, [r4], #2 )
504 THUMB( ldrht r5, [r4] )
505 THUMB( add r4, r4, #2 )
506 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
507 cmp r0, #0xe800 @ 32bit instruction if xx != 0
508 blo __und_usr_unknown
510 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
511 orr r0, r0, r5, lsl #16
519 @ fallthrough to call_fpe
523 * The out of line fixup for the ldrt above.
525 .section .fixup, "ax"
528 .section __ex_table,"a"
530 #if __LINUX_ARM_ARCH__ >= 7
537 * Check whether the instruction is a co-processor instruction.
538 * If yes, we need to call the relevant co-processor handler.
540 * Note that we don't do a full check here for the co-processor
541 * instructions; all instructions with bit 27 set are well
542 * defined. The only instructions that should fault are the
543 * co-processor instructions. However, we have to watch out
544 * for the ARM6/ARM7 SWI bug.
546 * NEON is a special case that has to be handled here. Not all
547 * NEON instructions are co-processor instructions, so we have
548 * to make a special case of checking for them. Plus, there's
549 * five groups of them, so we have a table of mask/opcode pairs
550 * to check against, and if any match then we branch off into the
553 * Emulators may wish to make use of the following registers:
554 * r0 = instruction opcode.
556 * r9 = normal "successful" return address
557 * r10 = this threads thread_info structure.
558 * lr = unrecognised instruction return address
561 @ Fall-through from Thumb-2 __und_usr
564 adr r6, .LCneon_thumb_opcodes
569 adr r6, .LCneon_arm_opcodes
571 ldr r7, [r6], #4 @ mask value
572 cmp r7, #0 @ end mask?
575 ldr r7, [r6], #4 @ opcode bits matching in mask
576 cmp r8, r7 @ NEON instruction?
580 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
581 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
582 b do_vfp @ let VFP handler handle this
585 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
586 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
587 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
588 and r8, r0, #0x0f000000 @ mask out op-code bits
589 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
592 get_thread_info r10 @ get current thread
593 and r8, r0, #0x00000f00 @ mask out CP number
594 THUMB( lsr r8, r8, #8 )
596 add r6, r10, #TI_USED_CP
597 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
598 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
600 @ Test if we need to give access to iWMMXt coprocessors
601 ldr r5, [r10, #TI_FLAGS]
602 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
603 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
604 bcs iwmmxt_task_enable
606 ARM( add pc, pc, r8, lsr #6 )
607 THUMB( lsl r8, r8, #2 )
612 W(b) do_fpe @ CP#1 (FPE)
613 W(b) do_fpe @ CP#2 (FPE)
616 b crunch_task_enable @ CP#4 (MaverickCrunch)
617 b crunch_task_enable @ CP#5 (MaverickCrunch)
618 b crunch_task_enable @ CP#6 (MaverickCrunch)
628 W(b) do_vfp @ CP#10 (VFP)
629 W(b) do_vfp @ CP#11 (VFP)
631 W(mov) pc, lr @ CP#10 (VFP)
632 W(mov) pc, lr @ CP#11 (VFP)
634 W(mov) pc, lr @ CP#12
635 W(mov) pc, lr @ CP#13
636 W(mov) pc, lr @ CP#14 (Debug)
637 W(mov) pc, lr @ CP#15 (Control)
643 .word 0xfe000000 @ mask
644 .word 0xf2000000 @ opcode
646 .word 0xff100000 @ mask
647 .word 0xf4000000 @ opcode
649 .word 0x00000000 @ mask
650 .word 0x00000000 @ opcode
652 .LCneon_thumb_opcodes:
653 .word 0xef000000 @ mask
654 .word 0xef000000 @ opcode
656 .word 0xff100000 @ mask
657 .word 0xf9000000 @ opcode
659 .word 0x00000000 @ mask
660 .word 0x00000000 @ opcode
666 add r10, r10, #TI_FPSTATE @ r10 = workspace
667 ldr pc, [r4] @ Call FP module USR entry point
670 * The FP module is called with these registers set:
673 * r9 = normal "successful" return address
675 * lr = unrecognised FP instruction return address
688 adr lr, BSYM(ret_from_exception)
690 ENDPROC(__und_usr_unknown)
697 mov r0, r2 @ pass address of aborted instruction.
700 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
702 CPU_PABORT_HANDLER(r0, r2)
704 enable_irq @ Enable interrupts
706 bl do_PrefetchAbort @ call abort handler
710 * This is the return code to user mode for abort handlers
712 ENTRY(ret_from_exception)
720 ENDPROC(ret_from_exception)
723 * Register switch for ARMv3 and ARMv4 processors
724 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
725 * previous and next are guaranteed not to be the same.
730 add ip, r1, #TI_CPU_SAVE
731 ldr r3, [r2, #TI_TP_VALUE]
732 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
733 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
734 THUMB( str sp, [ip], #4 )
735 THUMB( str lr, [ip], #4 )
737 ldr r6, [r2, #TI_CPU_DOMAIN]
739 #if __LINUX_ARM_ARCH__ >= 6
740 #ifdef CONFIG_CPU_32v6K
743 strex r5, r4, [ip] @ Clear exclusive monitor
746 #if defined(CONFIG_HAS_TLS_REG)
747 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
748 #elif !defined(CONFIG_TLS_REG_EMUL)
750 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
753 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
756 add r4, r2, #TI_CPU_SAVE
757 ldr r0, =thread_notify_head
758 mov r1, #THREAD_NOTIFY_SWITCH
759 bl atomic_notifier_call_chain
762 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
763 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
764 THUMB( ldr sp, [ip], #4 )
765 THUMB( ldr pc, [ip] )
774 * These are segment of kernel provided user code reachable from user space
775 * at a fixed address in kernel memory. This is used to provide user space
776 * with some operations which require kernel help because of unimplemented
777 * native feature and/or instructions in many ARM CPUs. The idea is for
778 * this code to be executed directly in user mode for best efficiency but
779 * which is too intimate with the kernel counter part to be left to user
780 * libraries. In fact this code might even differ from one CPU to another
781 * depending on the available instruction set and restrictions like on
782 * SMP systems. In other words, the kernel reserves the right to change
783 * this code as needed without warning. Only the entry points and their
784 * results are guaranteed to be stable.
786 * Each segment is 32-byte aligned and will be moved to the top of the high
787 * vector page. New segments (if ever needed) must be added in front of
788 * existing ones. This mechanism should be used only for things that are
789 * really small and justified, and not be abused freely.
791 * User space is expected to implement those things inline when optimizing
792 * for a processor that has the necessary native support, but only if such
793 * resulting binaries are already to be incompatible with earlier ARM
794 * processors due to the use of unsupported instructions other than what
795 * is provided here. In other words don't make binaries unable to run on
796 * earlier processors just for the sake of not using these kernel helpers
797 * if your compiled code is not going to use the new instructions for other
803 #ifdef CONFIG_ARM_THUMB
811 .globl __kuser_helper_start
812 __kuser_helper_start:
815 * Reference prototype:
817 * void __kernel_memory_barrier(void)
821 * lr = return address
831 * Definition and user space usage example:
833 * typedef void (__kernel_dmb_t)(void);
834 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
836 * Apply any needed memory barrier to preserve consistency with data modified
837 * manually and __kuser_cmpxchg usage.
839 * This could be used as follows:
841 * #define __kernel_dmb() \
842 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
843 * : : : "r0", "lr","cc" )
846 __kuser_memory_barrier: @ 0xffff0fa0
853 * Reference prototype:
855 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
862 * lr = return address
866 * r0 = returned value (zero or non-zero)
867 * C flag = set if r0 == 0, clear if r0 != 0
873 * Definition and user space usage example:
875 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
876 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
878 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
879 * Return zero if *ptr was changed or non-zero if no exchange happened.
880 * The C flag is also set if *ptr was changed to allow for assembly
881 * optimization in the calling code.
885 * - This routine already includes memory barriers as needed.
887 * For example, a user space atomic_add implementation could look like this:
889 * #define atomic_add(ptr, val) \
890 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
891 * register unsigned int __result asm("r1"); \
893 * "1: @ atomic_add\n\t" \
894 * "ldr r0, [r2]\n\t" \
895 * "mov r3, #0xffff0fff\n\t" \
896 * "add lr, pc, #4\n\t" \
897 * "add r1, r0, %2\n\t" \
898 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
900 * : "=&r" (__result) \
901 * : "r" (__ptr), "rIL" (val) \
902 * : "r0","r3","ip","lr","cc","memory" ); \
906 __kuser_cmpxchg: @ 0xffff0fc0
908 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
911 * Poor you. No fast solution possible...
912 * The kernel itself must perform the operation.
913 * A special ghost syscall is used for that (see traps.c).
916 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
921 #elif __LINUX_ARM_ARCH__ < 6
926 * The only thing that can break atomicity in this cmpxchg
927 * implementation is either an IRQ or a data abort exception
928 * causing another process/thread to be scheduled in the middle
929 * of the critical sequence. To prevent this, code is added to
930 * the IRQ and data abort exception handlers to set the pc back
931 * to the beginning of the critical section if it is found to be
932 * within that critical section (see kuser_cmpxchg_fixup).
934 1: ldr r3, [r2] @ load current val
935 subs r3, r3, r0 @ compare with oldval
936 2: streq r1, [r2] @ store newval if eq
937 rsbs r0, r3, #0 @ set return val and C flag
942 @ Called from kuser_cmpxchg_check macro.
943 @ r2 = address of interrupted insn (must be preserved).
944 @ sp = saved regs. r7 and r8 are clobbered.
945 @ 1b = first critical insn, 2b = last critical insn.
946 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
948 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
950 rsbcss r8, r8, #(2b - 1b)
951 strcs r7, [sp, #S_PC]
956 #warning "NPTL on non MMU needs fixing"
965 mcr p15, 0, r0, c7, c10, 5 @ dmb
973 /* beware -- each __kuser slot must be 8 instructions max */
975 b __kuser_memory_barrier
985 * Reference prototype:
987 * int __kernel_get_tls(void)
991 * lr = return address
1001 * Definition and user space usage example:
1003 * typedef int (__kernel_get_tls_t)(void);
1004 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
1006 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
1008 * This could be used as follows:
1010 * #define __kernel_get_tls() \
1011 * ({ register unsigned int __val asm("r0"); \
1012 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
1013 * : "=r" (__val) : : "lr","cc" ); \
1017 __kuser_get_tls: @ 0xffff0fe0
1019 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
1020 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
1022 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
1027 .word 0 @ pad up to __kuser_helper_version
1031 * Reference declaration:
1033 * extern unsigned int __kernel_helper_version;
1035 * Definition and user space usage example:
1037 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1039 * User space may read this to determine the curent number of helpers
1043 __kuser_helper_version: @ 0xffff0ffc
1044 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1046 .globl __kuser_helper_end
1054 * This code is copied to 0xffff0200 so we can use branches in the
1055 * vectors, rather than ldr's. Note that this code must not
1056 * exceed 0x300 bytes.
1058 * Common stub entry macro:
1059 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1061 * SP points to a minimal amount of processor-private memory, the address
1062 * of which is copied into r0 for the mode specific abort handler.
1064 .macro vector_stub, name, mode, correction=0
1069 sub lr, lr, #\correction
1073 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1076 stmia sp, {r0, lr} @ save r0, lr
1078 str lr, [sp, #8] @ save spsr
1081 @ Prepare for SVC32 mode. IRQs remain disabled.
1084 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1088 @ the branch table must immediately follow this code
1092 THUMB( ldr lr, [r0, lr, lsl #2] )
1094 ARM( ldr lr, [pc, lr, lsl #2] )
1095 movs pc, lr @ branch to handler in SVC mode
1096 ENDPROC(vector_\name)
1099 @ handler addresses follow this label
1103 .globl __stubs_start
1106 * Interrupt dispatcher
1108 vector_stub irq, IRQ_MODE, 4
1110 .long __irq_usr @ 0 (USR_26 / USR_32)
1111 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1112 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1113 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1114 .long __irq_invalid @ 4
1115 .long __irq_invalid @ 5
1116 .long __irq_invalid @ 6
1117 .long __irq_invalid @ 7
1118 .long __irq_invalid @ 8
1119 .long __irq_invalid @ 9
1120 .long __irq_invalid @ a
1121 .long __irq_invalid @ b
1122 .long __irq_invalid @ c
1123 .long __irq_invalid @ d
1124 .long __irq_invalid @ e
1125 .long __irq_invalid @ f
1128 * Data abort dispatcher
1129 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1131 vector_stub dabt, ABT_MODE, 8
1133 .long __dabt_usr @ 0 (USR_26 / USR_32)
1134 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1135 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1136 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1137 .long __dabt_invalid @ 4
1138 .long __dabt_invalid @ 5
1139 .long __dabt_invalid @ 6
1140 .long __dabt_invalid @ 7
1141 .long __dabt_invalid @ 8
1142 .long __dabt_invalid @ 9
1143 .long __dabt_invalid @ a
1144 .long __dabt_invalid @ b
1145 .long __dabt_invalid @ c
1146 .long __dabt_invalid @ d
1147 .long __dabt_invalid @ e
1148 .long __dabt_invalid @ f
1151 * Prefetch abort dispatcher
1152 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1154 vector_stub pabt, ABT_MODE, 4
1156 .long __pabt_usr @ 0 (USR_26 / USR_32)
1157 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1158 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1159 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1160 .long __pabt_invalid @ 4
1161 .long __pabt_invalid @ 5
1162 .long __pabt_invalid @ 6
1163 .long __pabt_invalid @ 7
1164 .long __pabt_invalid @ 8
1165 .long __pabt_invalid @ 9
1166 .long __pabt_invalid @ a
1167 .long __pabt_invalid @ b
1168 .long __pabt_invalid @ c
1169 .long __pabt_invalid @ d
1170 .long __pabt_invalid @ e
1171 .long __pabt_invalid @ f
1174 * Undef instr entry dispatcher
1175 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1177 vector_stub und, UND_MODE
1179 .long __und_usr @ 0 (USR_26 / USR_32)
1180 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1181 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1182 .long __und_svc @ 3 (SVC_26 / SVC_32)
1183 .long __und_invalid @ 4
1184 .long __und_invalid @ 5
1185 .long __und_invalid @ 6
1186 .long __und_invalid @ 7
1187 .long __und_invalid @ 8
1188 .long __und_invalid @ 9
1189 .long __und_invalid @ a
1190 .long __und_invalid @ b
1191 .long __und_invalid @ c
1192 .long __und_invalid @ d
1193 .long __und_invalid @ e
1194 .long __und_invalid @ f
1198 /*=============================================================================
1200 *-----------------------------------------------------------------------------
1201 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1202 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1203 * Basically to switch modes, we *HAVE* to clobber one register... brain
1204 * damage alert! I don't think that we can execute any code in here in any
1205 * other mode than FIQ... Ok you can switch to another mode, but you can't
1206 * get out of that mode without clobbering one register.
1212 /*=============================================================================
1213 * Address exception handler
1214 *-----------------------------------------------------------------------------
1215 * These aren't too critical.
1216 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1223 * We group all the following data together to optimise
1224 * for CPUs with separate I & D caches.
1234 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1236 .globl __vectors_start
1238 ARM( swi SYS_ERROR0 )
1241 W(b) vector_und + stubs_offset
1242 W(ldr) pc, .LCvswi + stubs_offset
1243 W(b) vector_pabt + stubs_offset
1244 W(b) vector_dabt + stubs_offset
1245 W(b) vector_addrexcptn + stubs_offset
1246 W(b) vector_irq + stubs_offset
1247 W(b) vector_fiq + stubs_offset
1249 .globl __vectors_end
1255 .globl cr_no_alignment