650ddf380261fe1dcab31161802d81148d4f33cd
[linux-3.10.git] / arch / arm / include / asm / hardware / cache-l2x0.h
1 /*
2  * arch/arm/include/asm/hardware/cache-l2x0.h
3  *
4  * Copyright (C) 2007 ARM Limited
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18  */
19
20 #ifndef __ASM_ARM_HARDWARE_L2X0_H
21 #define __ASM_ARM_HARDWARE_L2X0_H
22
23 #include <linux/errno.h>
24
25 #define L2X0_CACHE_ID                   0x000
26 #define L2X0_CACHE_TYPE                 0x004
27 #define L2X0_CTRL                       0x100
28 #define L2X0_AUX_CTRL                   0x104
29 #define L2X0_TAG_LATENCY_CTRL           0x108
30 #define L2X0_DATA_LATENCY_CTRL          0x10C
31 #define L2X0_EVENT_CNT_CTRL             0x200
32 #define L2X0_EVENT_CNT1_CFG             0x204
33 #define L2X0_EVENT_CNT0_CFG             0x208
34 #define L2X0_EVENT_CNT1_VAL             0x20C
35 #define L2X0_EVENT_CNT0_VAL             0x210
36 #define L2X0_INTR_MASK                  0x214
37 #define L2X0_MASKED_INTR_STAT           0x218
38 #define L2X0_RAW_INTR_STAT              0x21C
39 #define L2X0_INTR_CLEAR                 0x220
40 #define L2X0_CACHE_SYNC                 0x730
41 #define L2X0_DUMMY_REG                  0x740
42 #define L2X0_INV_LINE_PA                0x770
43 #define L2X0_INV_WAY                    0x77C
44 #define L2X0_CLEAN_LINE_PA              0x7B0
45 #define L2X0_CLEAN_LINE_IDX             0x7B8
46 #define L2X0_CLEAN_WAY                  0x7BC
47 #define L2X0_CLEAN_INV_LINE_PA          0x7F0
48 #define L2X0_CLEAN_INV_LINE_IDX         0x7F8
49 #define L2X0_CLEAN_INV_WAY              0x7FC
50 /*
51  * The lockdown registers repeat 8 times for L310, the L210 has only one
52  * D and one I lockdown register at 0x0900 and 0x0904.
53  */
54 #define L2X0_LOCKDOWN_WAY_D_BASE        0x900
55 #define L2X0_LOCKDOWN_WAY_I_BASE        0x904
56 #define L2X0_LOCKDOWN_STRIDE            0x08
57 #define L2X0_ADDR_FILTER_START          0xC00
58 #define L2X0_ADDR_FILTER_END            0xC04
59 #define L2X0_TEST_OPERATION             0xF00
60 #define L2X0_LINE_DATA                  0xF10
61 #define L2X0_LINE_TAG                   0xF30
62 #define L2X0_DEBUG_CTRL                 0xF40
63 #define L2X0_PREFETCH_CTRL              0xF60
64 #define L2X0_POWER_CTRL                 0xF80
65 #define   L2X0_DYNAMIC_CLK_GATING_EN    (1 << 1)
66 #define   L2X0_STNDBY_MODE_EN           (1 << 0)
67
68 /* Registers shifts and masks */
69 #define L2X0_CACHE_ID_REV_MASK          (0x3f)
70 #define L2X0_CACHE_ID_PART_MASK         (0xf << 6)
71 #define L2X0_CACHE_ID_PART_L210         (1 << 6)
72 #define L2X0_CACHE_ID_PART_L310         (3 << 6)
73 #define L2X0_CACHE_ID_RTL_MASK          0x3f
74 #define L2X0_CACHE_ID_RTL_R0P0          0x0
75 #define L2X0_CACHE_ID_RTL_R1P0          0x2
76 #define L2X0_CACHE_ID_RTL_R2P0          0x4
77 #define L2X0_CACHE_ID_RTL_R3P0          0x5
78 #define L2X0_CACHE_ID_RTL_R3P1          0x6
79 #define L2X0_CACHE_ID_RTL_R3P2          0x8
80
81 #define L2X0_AUX_CTRL_MASK                      0xc0000fff
82 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT     0
83 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK      0x7
84 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT     3
85 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK      (0x7 << 3)
86 #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT         6
87 #define L2X0_AUX_CTRL_TAG_LATENCY_MASK          (0x7 << 6)
88 #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT       9
89 #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK        (0x7 << 9)
90 #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT       16
91 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT            17
92 #define L2X0_AUX_CTRL_WAY_SIZE_MASK             (0x7 << 17)
93 #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT      22
94 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT         26
95 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT         27
96 #define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT       28
97 #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT      29
98 #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT         30
99
100 #define L2X0_LATENCY_CTRL_SETUP_SHIFT   0
101 #define L2X0_LATENCY_CTRL_RD_SHIFT      4
102 #define L2X0_LATENCY_CTRL_WR_SHIFT      8
103
104 #define L2X0_ADDR_FILTER_EN             1
105
106 #define L2X0_CTRL_EN                    1
107
108 #define L2X0_WAY_SIZE_SHIFT             3
109
110 #define REV_PL310_R2P0                          4
111
112 #ifndef __ASSEMBLY__
113 extern void l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask);
114 extern void l2x0_enable(void);
115 #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF)
116 extern int l2x0_of_init(u32 aux_val, u32 aux_mask);
117 #else
118 static inline int l2x0_of_init(u32 aux_val, u32 aux_mask)
119 {
120         return -ENODEV;
121 }
122 #endif
123
124 struct l2x0_regs {
125         unsigned long phy_base;
126         unsigned long aux_ctrl;
127         /*
128          * Whether the following registers need to be saved/restored
129          * depends on platform
130          */
131         unsigned long tag_latency;
132         unsigned long data_latency;
133         unsigned long filter_start;
134         unsigned long filter_end;
135         unsigned long prefetch_ctrl;
136         unsigned long pwr_ctrl;
137         unsigned long ctrl;
138 };
139
140 extern struct l2x0_regs l2x0_saved_regs;
141
142 #endif /* __ASSEMBLY__ */
143
144 #endif