ARM: DT: Add DT entry for PWMs and Backlight
[linux-3.10.git] / arch / arm / boot / dts / tegra124-soc.dtsi
1 / {
2         aliases {
3                 i2c0 = &i2c1;
4                 i2c1 = &i2c2;
5                 i2c2 = &i2c3;
6                 i2c3 = &i2c4;
7                 i2c4 = &i2c5;
8                 i2c5 = &i2c6;
9                 serial0 = &uarta;
10                 serial1 = &uartb;
11                 serial2 = &uartc;
12                 serial3 = &uartd;
13                 spi0 = &spi0;
14                 spi1 = &spi1;
15                 spi2 = &spi2;
16                 spi3 = &spi3;
17                 spi4 = &spi4;
18                 spi5 = &spi5;
19         };
20
21         gpio: gpio@6000d000 {
22                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
23                 reg = <0x6000d000 0x1000>;
24                 interrupts = <0 32 0x04
25                                 0 33 0x04
26                                 0 34 0x04
27                                 0 35 0x04
28                                 0 55 0x04
29                                 0 87 0x04
30                                 0 89 0x04
31                                 0 125 0x04>;
32                 #gpio-cells = <2>;
33                 gpio-controller;
34                 #interrupt-cells = <2>;
35                 interrupt-controller;
36         };
37
38         tegra_car: clock {
39                 compatible = "nvidia,tegra124-car";
40                 reg = <0x60006000 0x1000>;
41                 #clock-cells = <1>;
42         };
43
44         pwm: pwm {
45                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
46                 reg = <0x7000a000 0x100>;
47                 #pwm-cells = <2>;
48                 clocks = <&tegra_car 17>;
49         };
50
51         apbdma: dma@60020000 {
52                 compatible = "nvidia,tegra124-apbdma";
53                 reg = <0x60020000 0x1400>;
54                 interrupts = <0 104 0x04
55                               0 105 0x04
56                               0 106 0x04
57                               0 107 0x04
58                               0 108 0x04
59                               0 109 0x04
60                               0 110 0x04
61                               0 111 0x04
62                               0 112 0x04
63                               0 113 0x04
64                               0 114 0x04
65                               0 115 0x04
66                               0 116 0x04
67                               0 117 0x04
68                               0 118 0x04
69                               0 119 0x04
70                               0 128 0x04
71                               0 129 0x04
72                               0 130 0x04
73                               0 131 0x04
74                               0 132 0x04
75                               0 133 0x04
76                               0 134 0x04
77                               0 135 0x04
78                               0 136 0x04
79                               0 137 0x04
80                               0 138 0x04
81                               0 139 0x04
82                               0 140 0x04
83                               0 141 0x04
84                               0 142 0x04
85                               0 143 0x04>;
86         };
87
88         pinmux: pinmux {
89                 compatible = "nvidia,tegra124-pinmux";
90                 reg = <0x70000868 0x164         /* Pad control registers */
91                        0x70003000 0x434>;       /* Mux registers */
92                 status = "disable";
93         };
94
95         /*
96          * There are two serial driver i.e. 8250 based simple serial
97          * driver and APB DMA based serial driver for higher baudrate
98          * and performace. To enable the 8250 based driver, the compatible
99          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
100          * the APB DMA based serial driver, the comptible is
101          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
102          */
103         uarta: serial@70006000 {
104                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
105                 reg = <0x70006000 0x40>;
106                 reg-shift = <2>;
107                 interrupts = <0 36 0x04>;
108                 nvidia,dma-request-selector = <&apbdma 8>;
109                 nvidia,memory-clients = <14>;
110                 status = "disabled";
111         };
112
113         uartb: serial@70006040 {
114                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
115                 reg = <0x70006040 0x40>;
116                 reg-shift = <2>;
117                 interrupts = <0 37 0x04>;
118                 nvidia,dma-request-selector = <&apbdma 9>;
119                 nvidia,memory-clients = <14>;
120                 status = "disabled";
121         };
122
123         uartc: serial@70006200 {
124                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
125                 reg = <0x70006200 0x40>;
126                 reg-shift = <2>;
127                 interrupts = <0 46 0x04>;
128                 nvidia,dma-request-selector = <&apbdma 10>;
129                 nvidia,memory-clients = <14>;
130                 status = "disabled";
131         };
132
133         uartd: serial@70006300 {
134                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
135                 reg = <0x70006300 0x40>;
136                 reg-shift = <2>;
137                 interrupts = <0 90 0x04>;
138                 nvidia,dma-request-selector = <&apbdma 19>;
139                 nvidia,memory-clients = <14>;
140                 status = "disabled";
141         };
142
143         i2c1: i2c@7000c000 {
144                 #address-cells = <1>;
145                 #size-cells = <0>;
146                 compatible = "nvidia,tegra124-i2c";
147                 reg = <0x7000c000 0x100>;
148                 interrupts = <0 38 0x04>;
149                 scl-gpio = <&gpio 20 0>; /* gpio PC4 */
150                 sda-gpio = <&gpio 21 0>; /* gpio PC5 */
151                 nvidia,memory-clients = <14>;
152                 status = "disable";
153         };
154
155         i2c2: i2c@7000c400 {
156                 #address-cells = <1>;
157                 #size-cells = <0>;
158                 compatible = "nvidia,tegra124-i2c";
159                 reg = <0x7000c400 0x100>;
160                 interrupts = <0 84 0x04>;
161                 scl-gpio = <&gpio 157 0>; /* gpio PT5 */
162                 sda-gpio = <&gpio 158 0>; /* gpio PT6 */
163                 nvidia,memory-clients = <14>;
164                 status = "disable";
165         };
166
167         i2c3: i2c@7000c500 {
168                 #address-cells = <1>;
169                 #size-cells = <0>;
170                 compatible = "nvidia,tegra124-i2c";
171                 reg = <0x7000c500 0x100>;
172                 interrupts = <0 92 0x04>;
173                 scl-gpio = <&gpio 217 0>; /* gpio PBB1 */
174                 sda-gpio = <&gpio 218 0>; /* gpio PBB2 */
175                 nvidia,memory-clients = <14>;
176                 status = "disable";
177         };
178
179         i2c4: i2c@7000c700 {
180                 #address-cells = <1>;
181                 #size-cells = <0>;
182                 compatible = "nvidia,tegra124-i2c";
183                 reg = <0x7000c700 0x100>;
184                 interrupts = <0 120 0x04>;
185                 scl-gpio = <&gpio 172 0>; /* gpio PV4 */
186                 sda-gpio = <&gpio 173 0>; /* gpio PV5 */
187                 nvidia,memory-clients = <14>;
188                 status = "disable";
189         };
190
191         i2c5: i2c@7000d000 {
192                 #address-cells = <1>;
193                 #size-cells = <0>;
194                 compatible = "nvidia,tegra124-i2c";
195                 reg = <0x7000d000 0x100>;
196                 interrupts = <0 53 0x04>;
197                 scl-gpio = <&gpio 206 0>; /* gpio PZ6 */
198                 sda-gpio = <&gpio 207 0>; /* gpio PZ7 */
199                 nvidia,memory-clients = <14>;
200                 status = "disable";
201         };
202
203         i2c6: i2c@7000d100 {
204                 #address-cells = <1>;
205                 #size-cells = <0>;
206                 compatible = "nvidia,tegra124-i2c";
207                 reg = <0x7000d100 0x100>;
208                 interrupts = <0 63 0x04>;
209                 nvidia,memory-clients = <14>;
210                 status = "disable";
211         };
212
213         spi0: spi@7000d400 {
214                 compatible = "nvidia,tegra114-spi";
215                 reg = <0x7000d400 0x200>;
216                 interrupts = <0 59 0x04>;
217                 nvidia,dma-request-selector = <&apbdma 15>;
218                 nvidia,memory-clients = <14>;
219                 #address-cells = <1>;
220                 #size-cells = <0>;
221                 status = "disabled";
222         };
223
224         spi1: spi@7000d600 {
225                 compatible = "nvidia,tegra114-spi";
226                 reg = <0x7000d600 0x200>;
227                 interrupts = <0 82 0x04>;
228                 nvidia,dma-request-selector = <&apbdma 16>;
229                 nvidia,memory-clients = <14>;
230                 #address-cells = <1>;
231                 #size-cells = <0>;
232                 status = "disabled";
233         };
234
235         spi2: spi@7000d800 {
236                 compatible = "nvidia,tegra114-spi";
237                 reg = <0x7000d800 0x200>;
238                 interrupts = <0 83 0x04>;
239                 nvidia,dma-request-selector = <&apbdma 17>;
240                 nvidia,memory-clients = <14>;
241                 #address-cells = <1>;
242                 #size-cells = <0>;
243                 status = "disabled";
244         };
245
246         spi3: spi@7000da00 {
247                 compatible = "nvidia,tegra114-spi";
248                 reg = <0x7000da00 0x200>;
249                 interrupts = <0 93 0x04>;
250                 nvidia,dma-request-selector = <&apbdma 18>;
251                 nvidia,memory-clients = <14>;
252                 #address-cells = <1>;
253                 #size-cells = <0>;
254                 status = "disabled";
255         };
256
257         spi4: spi@7000dc00 {
258                 compatible = "nvidia,tegra114-spi";
259                 reg = <0x7000dc00 0x200>;
260                 interrupts = <0 94 0x04>;
261                 nvidia,dma-request-selector = <&apbdma 27>;
262                 nvidia,memory-clients = <14>;
263                 #address-cells = <1>;
264                 #size-cells = <0>;
265                 status = "disabled";
266         };
267
268         spi5: spi@7000de00 {
269                 compatible = "nvidia,tegra114-spi";
270                 reg = <0x7000de00 0x200>;
271                 interrupts = <0 79 0x04>;
272                 nvidia,dma-request-selector = <&apbdma 28>;
273                 nvidia,memory-clients = <14>;
274                 #address-cells = <1>;
275                 #size-cells = <0>;
276                 status = "disabled";
277         };
278
279         pmc {
280                 compatible = "nvidia,tegra124-pmc";
281                 reg = <0x7000e400 0x400>;
282                 clocks = <&tegra_car 261>, <&clk32k_in>;
283                 clock-names = "pclk", "clk32k_in";
284         };
285
286         clocks {
287                 compatible = "simple-bus";
288                 #address-cells = <1>;
289                 #size-cells = <0>;
290
291                 clk32k_in: clock {
292                         compatible = "fixed-clock";
293                         reg=<0>;
294                         #clock-cells = <0>;
295                         clock-frequency = <32768>;
296                 };
297         };
298
299         timer@60005000 {
300                 compatible = "nvidia,tegra-nvtimer";
301                 reg = <0x60005000 0x400>;
302                 interrupts = <0 0 0x04
303                               0 1 0x04
304                               0 41 0x04
305                               0 42 0x04
306                               0 121 0x04
307                               0 151 0x04
308                               0 152 0x04
309                               0 153 0x04
310                               0 154 0x04
311                               0 155 0x04
312                               0 122 0x04>;
313                 clocks = <&tegra_car 5>;
314         };
315
316         rtc {
317                 compatible = "nvidia,tegra-rtc";
318                 reg = <0x7000e000 0x100>;
319                 interrupts = <0 2 0x04>;
320                 clocks = <&tegra_car 4>;
321         };
322
323         tegra_ahub_apbif: ahub {
324                 compatible = "nvidia,tegra124-ahub";
325                 reg = <0x70300000 0x200>,
326                         <0x70300800 0x800>,
327                         <0x70300200 0x200>;
328                 interrupts = <0 103 0x04>;
329                 nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
330                         <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
331                         <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, <&apbdma 29>;
332                 status = "disabled";
333
334                 ranges;
335                 #address-cells = <1>;
336                 #size-cells = <1>;
337
338                 tegra_i2s0: i2s@70301000 {
339                         compatible = "nvidia,tegra124-i2s";
340                         reg = <0x70301000 0x100>;
341                         nvidia,ahub-cif-ids = <4 4>;
342                         status = "disabled";
343                 };
344
345                 tegra_i2s1: i2s@70301100 {
346                         compatible = "nvidia,tegra124-i2s";
347                         reg = <0x70301100 0x100>;
348                         nvidia,ahub-cif-ids = <5 5>;
349                         status = "disabled";
350                 };
351
352                 tegra_i2s2: i2s@70301200 {
353                         compatible = "nvidia,tegra124-i2s";
354                         reg = <0x70301200 0x100>;
355                         nvidia,ahub-cif-ids = <6 6>;
356                         status = "disabled";
357                 };
358
359                 tegra_i2s3: i2s@70301300 {
360                         compatible = "nvidia,tegra124-i2s";
361                         reg = <0x70301300 0x100>;
362                         nvidia,ahub-cif-ids = <7 7>;
363                         status = "disabled";
364                 };
365
366                 tegra_i2s4: i2s@70301400 {
367                         compatible = "nvidia,tegra124-i2s";
368                         reg = <0x70301400 0x100>;
369                         nvidia,ahub-cif-ids = <8 8>;
370                         status = "disabled";
371                 };
372
373                 tegra_amx0: amx@70303000 {
374                         compatible = "nvidia,tegra124-amx";
375                         reg = <0x70303000 0x100>;
376                         status = "disabled";
377                 };
378
379                 tegra_amx1: amx@70303100 {
380                         compatible = "nvidia,tegra124-amx";
381                         reg = <0x70303100 0x100>;
382                         status = "disabled";
383                 };
384
385                 tegra_adx0: adx@70303800 {
386                         compatible = "nvidia,tegra124-adx";
387                         reg = <0x70303800 0x100>;
388                         status = "disabled";
389                 };
390
391                 tegra_adx1: adx@70303900 {
392                         compatible = "nvidia,tegra124-adx";
393                         reg = <0x70303900 0x100>;
394                         status = "disabled";
395                 };
396         };
397 };