3067aef87abcfb8151b6af349501f07179c170d9
[linux-3.10.git] / arch / arm / boot / dts / tegra114.dtsi
1 /include/ "skeleton.dtsi"
2
3 / {
4         compatible = "nvidia,tegra114";
5         interrupt-parent = <&gic>;
6
7         aliases {
8                 i2c0 = &i2c1;
9                 i2c1 = &i2c2;
10                 i2c2 = &i2c3;
11                 i2c3 = &i2c4;
12                 i2c4 = &i2c5;
13                 spi0 = &spi0;
14                 spi1 = &spi1;
15                 spi2 = &spi2;
16                 spi3 = &spi3;
17                 spi4 = &spi4;
18                 spi5 = &spi5;
19                 serial0 = &uarta;
20                 serial1 = &uartb;
21                 serial2 = &uartc;
22                 serial3 = &uartd;
23         };
24
25         host1x {
26                 compatible = "nvidia,tegra114-host1x", "simple-bus";
27                 reg = <0x50000000 0x00024000>;
28                 interrupts = <0 65 0x04   /* mpcore syncpt */
29                               0 67 0x04>; /* mpcore general */
30                 nvidia,memory-clients = <6>;
31
32                 #address-cells = <1>;
33                 #size-cells = <1>;
34
35                 ranges = <0x54000000 0x54000000 0x01000000>;
36
37                 vi {
38                         compatible = "nvidia,tegra114-vi";
39                         reg = <0x54080000 0x00040000>;
40                         interrupts = <0 69 0x04>;
41                         nvidia,memory-clients = <18>;
42                 };
43
44                 epp {
45                         compatible = "nvidia,tegra114-epp";
46                         reg = <0x540c0000 0x00040000>;
47                         nvidia,memory-clients = <4>;
48                 };
49
50                 isp {
51                         compatible = "nvidia,tegra114-isp";
52                         reg = <0x54100000 0x00040000>;
53                         nvidia,memory-clients = <8>;
54                 };
55
56                 gr2d {
57                         compatible = "nvidia,tegra114-gr2d";
58                         reg = <0x54140000 0x00040000>;
59                         nvidia,memory-clients = <5>;
60                 };
61
62                 gr3d {
63                         compatible = "nvidia,tegra114-gr3d";
64                         reg = <0x54180000 0x00040000>;
65                         nvidia,memory-clients = <12>;
66                 };
67
68                 dc@54200000 {
69                         compatible = "nvidia,tegra114-dc";
70                         reg = <0x54200000 0x00040000>;
71                         interrupts = <0 73 0x04>;
72                         nvidia,memory-clients = <2>;
73
74                         rgb {
75                                 status = "disabled";
76                         };
77                 };
78
79                 dc@54240000 {
80                         compatible = "nvidia,tegra114-dc";
81                         reg = <0x54240000 0x00040000>;
82                         interrupts = <0 74 0x04>;
83                         nvidia,memory-clients = <3>;
84
85                         rgb {
86                                 status = "disabled";
87                         };
88                 };
89
90                 hdmi {
91                         compatible = "nvidia,tegra114-hdmi";
92                         reg = <0x54280000 0x00040000>;
93                         interrupts = <0 75 0x04>;
94                         status = "disabled";
95                 };
96
97                 tvo {
98                         compatible = "nvidia,tegra114-tvo";
99                         reg = <0x542c0000 0x00040000>;
100                         interrupts = <0 76 0x04>;
101                         status = "disabled";
102                 };
103
104                 dsi {
105                         compatible = "nvidia,tegra114-dsi";
106                         reg = <0x54300000 0x00040000>,
107                               <0x54400000 0x00040000>;
108                         status = "disabled";
109                 };
110
111                 msenc {
112                         compatible = "nvidia,tegra114-msenc";
113                         reg = <0x544c0000 0x00040000>;
114                         nvidia,memory-clients = <11>;
115                 };
116
117                 tsec {
118                         compatible = "nvidia,tegra114-tsec";
119                         reg = <0x54500000 0x00040000>;
120                         nvidia,memory-clients = <23>;
121                 };
122         };
123
124         gic: interrupt-controller {
125                 compatible = "arm,cortex-a15-gic";
126                 #interrupt-cells = <3>;
127                 interrupt-controller;
128                 reg = <0x50041000 0x1000>,
129                       <0x50042000 0x1000>,
130                       <0x50044000 0x2000>,
131                       <0x50046000 0x2000>;
132                 interrupts = <1 9 0xf04>;
133         };
134
135         lic: interrupt-controller@60004000 {
136                 compatible = "nvidia,tegra-gic";
137                 interrupt-controller;
138                 reg = <0x60004000 0x40>,
139                       <0x60004100 0x40>,
140                       <0x60004200 0x40>,
141                       <0x60004300 0x40>,
142                       <0x60004400 0x40>;
143         };
144
145         timer@60005000 {
146                 compatible = "nvidia,tegra-nvtimer";
147                 reg = <0x60005000 0x400>;
148                 interrupts = <0 0 0x04
149                               0 1 0x04
150                               0 41 0x04
151                               0 42 0x04
152                               0 121 0x04
153                               0 151 0x04
154                               0 152 0x04
155                               0 153 0x04
156                               0 154 0x04
157                               0 155 0x04
158                               0 122 0x04>;
159                 clocks = <&tegra_car 5>;
160         };
161
162         tegra_car: clock {
163                 compatible = "nvidia,tegra114-car";
164                 reg = <0x60006000 0x1000>;
165                 #clock-cells = <1>;
166         };
167
168         apbdma: dma {
169                 compatible = "nvidia,tegra114-apbdma";
170                 reg = <0x6000a000 0x1400>;
171                 interrupts = <0 104 0x04
172                               0 105 0x04
173                               0 106 0x04
174                               0 107 0x04
175                               0 108 0x04
176                               0 109 0x04
177                               0 110 0x04
178                               0 111 0x04
179                               0 112 0x04
180                               0 113 0x04
181                               0 114 0x04
182                               0 115 0x04
183                               0 116 0x04
184                               0 117 0x04
185                               0 118 0x04
186                               0 119 0x04
187                               0 128 0x04
188                               0 129 0x04
189                               0 130 0x04
190                               0 131 0x04
191                               0 132 0x04
192                               0 133 0x04
193                               0 134 0x04
194                               0 135 0x04
195                               0 136 0x04
196                               0 137 0x04
197                               0 138 0x04
198                               0 139 0x04
199                               0 140 0x04
200                               0 141 0x04
201                               0 142 0x04
202                               0 143 0x04>;
203                 clocks = <&tegra_car 34>;
204         };
205
206         ahb: ahb {
207                 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
208                 reg = <0x6000c004 0x14c>;
209         };
210
211         gpio: gpio {
212                 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
213                 reg = <0x6000d000 0x1000>;
214                 interrupts = <0 32 0x04
215                               0 33 0x04
216                               0 34 0x04
217                               0 35 0x04
218                               0 55 0x04
219                               0 87 0x04
220                               0 89 0x04
221                               0 125 0x04>;
222                 #gpio-cells = <2>;
223                 gpio-controller;
224                 #interrupt-cells = <2>;
225                 interrupt-controller;
226         };
227
228         vde {
229                 reg = <0x6001a000 0x3bff>;
230                 compatible = "nvidia,tegra114-vde";
231                 nvidia,memory-clients = <17>;
232         };
233
234         pinmux: pinmux {
235                 compatible = "nvidia,tegra114-pinmux";
236                 reg = <0x70000868 0x148         /* Pad control registers */
237                        0x70003000 0x40c>;       /* Mux registers */
238                 status = "disable";
239         };
240
241         /*
242          * There are two serial driver i.e. 8250 based simple serial
243          * driver and APB DMA based serial driver for higher baudrate
244          * and performace. To enable the 8250 based driver, the compatible
245          * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable
246          * the APB DMA based serial driver, the comptible is
247          * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart".
248          */
249         uarta: serial@70006000 {
250                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
251                 reg = <0x70006000 0x40>;
252                 reg-shift = <2>;
253                 interrupts = <0 36 0x04>;
254                 nvidia,dma-request-selector = <&apbdma 8>;
255                 status = "disabled";
256                 clocks = <&tegra_car 6>;
257         };
258
259         uartb: serial@70006040 {
260                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
261                 reg = <0x70006040 0x40>;
262                 reg-shift = <2>;
263                 interrupts = <0 37 0x04>;
264                 nvidia,dma-request-selector = <&apbdma 9>;
265                 status = "disabled";
266                 clocks = <&tegra_car 192>;
267         };
268
269         uartc: serial@70006200 {
270                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
271                 reg = <0x70006200 0x40>;
272                 reg-shift = <2>;
273                 interrupts = <0 46 0x04>;
274                 nvidia,dma-request-selector = <&apbdma 10>;
275                 status = "disabled";
276                 clocks = <&tegra_car 55>;
277         };
278
279         uartd: serial@70006300 {
280                 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
281                 reg = <0x70006300 0x40>;
282                 reg-shift = <2>;
283                 interrupts = <0 90 0x04>;
284                 nvidia,dma-request-selector = <&apbdma 19>;
285                 status = "disabled";
286                 clocks = <&tegra_car 65>;
287         };
288
289         pwm: pwm {
290                 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
291                 reg = <0x7000a000 0x100>;
292                 #pwm-cells = <2>;
293                 clocks = <&tegra_car 17>;
294                 status = "disabled";
295         };
296
297         i2c1: i2c@7000c000 {
298                 compatible = "nvidia,tegra114-i2c";
299                 reg = <0x7000c000 0x100>;
300                 interrupts = <0 38 0x04>;
301                 #address-cells = <1>;
302                 #size-cells = <0>;
303                 clocks = <&tegra_car 12>;
304                 clock-names = "div-clk";
305                 scl-gpio = <&gpio 20 0>; /* gpio PC4 */
306                 sda-gpio = <&gpio 21 0>; /* gpio PC5 */
307                 status = "disabled";
308         };
309
310         pmc {
311                 compatible = "nvidia,tegra114-pmc";
312                 reg = <0x7000e400 0x400>;
313                 clocks = <&tegra_car 261>, <&clk32k_in>;
314                 clock-names = "pclk", "clk32k_in";
315         };
316
317         i2c2: i2c@7000c400 {
318                 compatible = "nvidia,tegra114-i2c";
319                 reg = <0x7000c400 0x100>;
320                 interrupts = <0 84 0x04>;
321                 #address-cells = <1>;
322                 #size-cells = <0>;
323                 clocks = <&tegra_car 54>;
324                 clock-names = "div-clk";
325                 scl-gpio = <&gpio 157 0>; /* gpio PT5 */
326                 sda-gpio = <&gpio 158 0>; /* gpio PT6 */
327                 status = "disabled";
328         };
329
330         i2c3: i2c@7000c500 {
331                 compatible = "nvidia,tegra114-i2c";
332                 reg = <0x7000c500 0x100>;
333                 interrupts = <0 92 0x04>;
334                 #address-cells = <1>;
335                 #size-cells = <0>;
336                 clocks = <&tegra_car 67>;
337                 clock-names = "div-clk";
338                 scl-gpio = <&gpio 217 0>; /* gpio PBB1 */
339                 sda-gpio = <&gpio 218 0>; /* gpio PBB2 */
340                 status = "disabled";
341         };
342
343         i2c4: i2c@7000c700 {
344                 compatible = "nvidia,tegra114-i2c";
345                 reg = <0x7000c700 0x100>;
346                 interrupts = <0 120 0x04>;
347                 #address-cells = <1>;
348                 #size-cells = <0>;
349                 clocks = <&tegra_car 103>;
350                 clock-names = "div-clk";
351                 scl-gpio = <&gpio 172 0>; /* gpio PV4 */
352                 sda-gpio = <&gpio 173 0>; /* gpio PV5 */
353                 status = "disabled";
354         };
355
356         i2c5: i2c@7000d000 {
357                 compatible = "nvidia,tegra114-i2c";
358                 reg = <0x7000d000 0x100>;
359                 interrupts = <0 53 0x04>;
360                 #address-cells = <1>;
361                 #size-cells = <0>;
362                 clocks = <&tegra_car 47>;
363                 clock-names = "div-clk";
364                 scl-gpio = <&gpio 206 0>; /* gpio PZ6 */
365                 sda-gpio = <&gpio 207 0>; /* gpio PZ7 */
366                 status = "disabled";
367         };
368
369         spi0: spi@7000d400 {
370                 compatible = "nvidia,tegra114-spi";
371                 reg = <0x7000d400 0x200>;
372                 interrupts = <0 59 0x04>;
373                 nvidia,dma-request-selector = <&apbdma 15>;
374                 #address-cells = <1>;
375                 #size-cells = <0>;
376                 clocks = <&tegra_car 41>;
377                 clock-names = "spi";
378                 status = "disabled";
379         };
380
381         spi1: spi@7000d600 {
382                 compatible = "nvidia,tegra114-spi";
383                 reg = <0x7000d600 0x200>;
384                 interrupts = <0 82 0x04>;
385                 nvidia,dma-request-selector = <&apbdma 16>;
386                 #address-cells = <1>;
387                 #size-cells = <0>;
388                 clocks = <&tegra_car 44>;
389                 clock-names = "spi";
390                 status = "disabled";
391         };
392
393         spi2: spi@7000d800 {
394                 compatible = "nvidia,tegra114-spi";
395                 reg = <0x7000d800 0x200>;
396                 interrupts = <0 83 0x04>;
397                 nvidia,dma-request-selector = <&apbdma 17>;
398                 #address-cells = <1>;
399                 #size-cells = <0>;
400                 clocks = <&tegra_car 46>;
401                 clock-names = "spi";
402                 status = "disabled";
403         };
404
405         spi3: spi@7000da00 {
406                 compatible = "nvidia,tegra114-spi";
407                 reg = <0x7000da00 0x200>;
408                 interrupts = <0 93 0x04>;
409                 nvidia,dma-request-selector = <&apbdma 18>;
410                 #address-cells = <1>;
411                 #size-cells = <0>;
412                 clocks = <&tegra_car 68>;
413                 clock-names = "spi";
414                 status = "disabled";
415         };
416
417         spi4: spi@7000dc00 {
418                 compatible = "nvidia,tegra114-spi";
419                 reg = <0x7000dc00 0x200>;
420                 interrupts = <0 94 0x04>;
421                 nvidia,dma-request-selector = <&apbdma 27>;
422                 #address-cells = <1>;
423                 #size-cells = <0>;
424                 clocks = <&tegra_car 104>;
425                 clock-names = "spi";
426                 status = "disabled";
427         };
428
429         spi5: spi@7000de00 {
430                 compatible = "nvidia,tegra114-spi";
431                 reg = <0x7000de00 0x200>;
432                 interrupts = <0 79 0x04>;
433                 nvidia,dma-request-selector = <&apbdma 28>;
434                 #address-cells = <1>;
435                 #size-cells = <0>;
436                 clocks = <&tegra_car 105>;
437                 clock-names = "spi";
438                 status = "disabled";
439         };
440
441         rtc {
442                 compatible = "nvidia,tegra-rtc";
443                 reg = <0x7000e000 0x100>;
444                 interrupts = <0 2 0x04>;
445                 clocks = <&tegra_car 4>;
446         };
447
448         kbc {
449                 compatible = "nvidia,tegra114-kbc";
450                 reg = <0x7000e200 0x100>;
451                 interrupts = <0 85 0x04>;
452                 clocks = <&tegra_car 36>;
453                 status = "disabled";
454         };
455
456         pmc {
457                 compatible = "nvidia,tegra114-pmc";
458                 reg = <0x7000e400 0x400>;
459                 clocks = <&tegra_car 261>, <&clk32k_in>;
460                 clock-names = "pclk", "clk32k_in";
461         };
462
463         iommu {
464                 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
465                 reg = <0x7000f010 0x02c
466                        0x7000f1f0 0x010
467                        0x7000f228 0x074>;
468                 nvidia,#asids = <4>;
469                 dma-window = <0 0x40000000>;
470                 nvidia,swgroups = <0x18659fe>;
471                 nvidia,ahb = <&ahb>;
472         };
473
474         ahub {
475                 compatible = "nvidia,tegra30-ahub";
476                 reg = <0x70080000 0x200
477                        0x70080200 0x100>;
478                 interrupts = <0 103 0x04>;
479                 nvidia,dma-request-selector = <&apbdma 1>;
480                 status = "disabled";
481
482                 ranges;
483                 #address-cells = <1>;
484                 #size-cells = <1>;
485
486                 tegra_i2s0: i2s@70080300 {
487                         compatible = "nvidia,tegra30-i2s";
488                         reg = <0x70080300 0x100>;
489                         nvidia,ahub-cif-ids = <4 4>;
490                         status = "disabled";
491                 };
492
493                 tegra_i2s1: i2s@70080400 {
494                         compatible = "nvidia,tegra30-i2s";
495                         reg = <0x70080400 0x100>;
496                         nvidia,ahub-cif-ids = <5 5>;
497                         status = "disabled";
498                 };
499
500                 tegra_i2s2: i2s@70080500 {
501                         compatible = "nvidia,tegra30-i2s";
502                         reg = <0x70080500 0x100>;
503                         nvidia,ahub-cif-ids = <6 6>;
504                         status = "disabled";
505                 };
506
507                 tegra_i2s3: i2s@70080600 {
508                         compatible = "nvidia,tegra30-i2s";
509                         reg = <0x70080600 0x100>;
510                         nvidia,ahub-cif-ids = <7 7>;
511                         status = "disabled";
512                 };
513
514                 tegra_i2s4: i2s@70080700 {
515                         compatible = "nvidia,tegra30-i2s";
516                         reg = <0x70080700 0x100>;
517                         nvidia,ahub-cif-ids = <8 8>;
518                         status = "disabled";
519                 };
520
521                 tegra_dam0: dam@70080800 {
522                         compatible = "nvidia,tegra30-dam";
523                         reg = <0x70080800 0x100>;
524                         nvidia,ahub-dam-id = <0>;
525                         status = "disabled";
526                 };
527
528                 tegra_dam1: dam@70080900 {
529                         compatible = "nvidia,tegra30-dam";
530                         reg = <0x70080900 0x100>;
531                         nvidia,ahub-dam-id = <1>;
532                         status = "disabled";
533                 };
534
535                 tegra_dam2: dam@70080A00 {
536                         compatible = "nvidia,tegra30-dam";
537                         reg = <0x70080A00 0x100>;
538                         nvidia,ahub-dam-id = <2>;
539                         status = "disabled";
540                 };
541
542                 tegra_spdif: spdif@70080B00 {
543                         compatible = "nvidia,tegra30-spdif";
544                         reg = <0x70080B00 0x100>;
545                         status = "disabled";
546                 };
547         };
548
549         sdhci@78000000 {
550                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
551                 reg = <0x78000000 0x200>;
552                 interrupts = <0 14 0x04>;
553                 clocks = <&tegra_car 14>;
554                 nvidia,memory-clients = <14>;
555                 status = "disable";
556         };
557
558         sdhci@78000200 {
559                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
560                 reg = <0x78000200 0x200>;
561                 interrupts = <0 15 0x04>;
562                 clocks = <&tegra_car 9>;
563                 nvidia,memory-clients = <14>;
564                 status = "disable";
565         };
566
567         sdhci@78000400 {
568                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
569                 reg = <0x78000400 0x200>;
570                 interrupts = <0 19 0x04>;
571                 clocks = <&tegra_car 69>;
572                 nvidia,memory-clients = <14>;
573                 status = "disable";
574         };
575
576         sdhci@78000600 {
577                 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci";
578                 reg = <0x78000600 0x200>;
579                 interrupts = <0 31 0x04>;
580                 clocks = <&tegra_car 15>;
581                 nvidia,memory-clients = <14>;
582                 status = "disable";
583         };
584
585         cpus {
586                 #address-cells = <1>;
587                 #size-cells = <0>;
588
589                 cpu@0 {
590                         device_type = "cpu";
591                         compatible = "arm,cortex-a15";
592                         reg = <0>;
593                 };
594
595                 cpu@1 {
596                         device_type = "cpu";
597                         compatible = "arm,cortex-a15";
598                         reg = <1>;
599                 };
600
601                 cpu@2 {
602                         device_type = "cpu";
603                         compatible = "arm,cortex-a15";
604                         reg = <2>;
605                 };
606
607                 cpu@3 {
608                         device_type = "cpu";
609                         compatible = "arm,cortex-a15";
610                         reg = <3>;
611                 };
612         };
613
614         timer {
615                 compatible = "arm,armv7-timer";
616                 interrupts = <1 13 0xf08>,
617                              <1 14 0xf08>;
618                 clock-frequency = <12000000>;
619         };
620
621         camera {
622                 compatible = "nvidia,tegra114-camera", "nvidia,tegra20-camera";
623                 reg = <0x0 0x0>;
624                 status = "disable";
625         };
626
627         mipical {
628                 compatible = "nvidia,tegra114-mipical";
629                 reg = <0x700e3000 0x00040000>;
630         };
631
632         clocks {
633                 compatible = "simple-bus";
634                 #address-cells = <1>;
635                 #size-cells = <0>;
636
637                 clk32k_in: clock {
638                         compatible = "fixed-clock";
639                         reg=<0>;
640                         #clock-cells = <0>;
641                         clock-frequency = <32768>;
642                 };
643         };
644 };