Merge branch 'for_3.7/omap5_arch_timer' of git://github.com/SantoshShilimkar/linux...
[linux-3.10.git] / arch / arm / boot / dts / omap5.dtsi
1 /*
2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  * Based on "omap4.dtsi"
8  */
9
10 /*
11  * Carveout for multimedia usecases
12  * It should be the last 48MB of the first 512MB memory part
13  * In theory, it should not even exist. That zone should be reserved
14  * dynamically during the .reserve callback.
15  */
16 /memreserve/ 0x9d000000 0x03000000;
17
18 /include/ "skeleton.dtsi"
19
20 / {
21         compatible = "ti,omap5";
22         interrupt-parent = <&gic>;
23
24         aliases {
25                 serial0 = &uart1;
26                 serial1 = &uart2;
27                 serial2 = &uart3;
28                 serial3 = &uart4;
29                 serial4 = &uart5;
30                 serial5 = &uart6;
31         };
32
33         cpus {
34                 cpu@0 {
35                         compatible = "arm,cortex-a15";
36                         timer {
37                                 compatible = "arm,armv7-timer";
38                                 /* 14th PPI IRQ, active low level-sensitive */
39                                 interrupts = <1 14 0x308>;
40                                 clock-frequency = <6144000>;
41                         };
42                 };
43                 cpu@1 {
44                         compatible = "arm,cortex-a15";
45                         timer {
46                                 compatible = "arm,armv7-timer";
47                                 /* 14th PPI IRQ, active low level-sensitive */
48                                 interrupts = <1 14 0x308>;
49                                 clock-frequency = <6144000>;
50                         };
51                 };
52         };
53
54         /*
55          * The soc node represents the soc top level view. It is uses for IPs
56          * that are not memory mapped in the MPU view or for the MPU itself.
57          */
58         soc {
59                 compatible = "ti,omap-infra";
60                 mpu {
61                         compatible = "ti,omap5-mpu";
62                         ti,hwmods = "mpu";
63                 };
64         };
65
66         /*
67          * XXX: Use a flat representation of the OMAP3 interconnect.
68          * The real OMAP interconnect network is quite complex.
69          * Since that will not bring real advantage to represent that in DT for
70          * the moment, just use a fake OCP bus entry to represent the whole bus
71          * hierarchy.
72          */
73         ocp {
74                 compatible = "ti,omap4-l3-noc", "simple-bus";
75                 #address-cells = <1>;
76                 #size-cells = <1>;
77                 ranges;
78                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
79
80                 gic: interrupt-controller@48211000 {
81                         compatible = "arm,cortex-a15-gic";
82                         interrupt-controller;
83                         #interrupt-cells = <3>;
84                         reg = <0x48211000 0x1000>,
85                               <0x48212000 0x1000>;
86                 };
87
88                 gpio1: gpio@4ae10000 {
89                         compatible = "ti,omap4-gpio";
90                         ti,hwmods = "gpio1";
91                         gpio-controller;
92                         #gpio-cells = <2>;
93                         interrupt-controller;
94                         #interrupt-cells = <1>;
95                 };
96
97                 gpio2: gpio@48055000 {
98                         compatible = "ti,omap4-gpio";
99                         ti,hwmods = "gpio2";
100                         gpio-controller;
101                         #gpio-cells = <2>;
102                         interrupt-controller;
103                         #interrupt-cells = <1>;
104                 };
105
106                 gpio3: gpio@48057000 {
107                         compatible = "ti,omap4-gpio";
108                         ti,hwmods = "gpio3";
109                         gpio-controller;
110                         #gpio-cells = <2>;
111                         interrupt-controller;
112                         #interrupt-cells = <1>;
113                 };
114
115                 gpio4: gpio@48059000 {
116                         compatible = "ti,omap4-gpio";
117                         ti,hwmods = "gpio4";
118                         gpio-controller;
119                         #gpio-cells = <2>;
120                         interrupt-controller;
121                         #interrupt-cells = <1>;
122                 };
123
124                 gpio5: gpio@4805b000 {
125                         compatible = "ti,omap4-gpio";
126                         ti,hwmods = "gpio5";
127                         gpio-controller;
128                         #gpio-cells = <2>;
129                         interrupt-controller;
130                         #interrupt-cells = <1>;
131                 };
132
133                 gpio6: gpio@4805d000 {
134                         compatible = "ti,omap4-gpio";
135                         ti,hwmods = "gpio6";
136                         gpio-controller;
137                         #gpio-cells = <2>;
138                         interrupt-controller;
139                         #interrupt-cells = <1>;
140                 };
141
142                 gpio7: gpio@48051000 {
143                         compatible = "ti,omap4-gpio";
144                         ti,hwmods = "gpio7";
145                         gpio-controller;
146                         #gpio-cells = <2>;
147                         interrupt-controller;
148                         #interrupt-cells = <1>;
149                 };
150
151                 gpio8: gpio@48053000 {
152                         compatible = "ti,omap4-gpio";
153                         ti,hwmods = "gpio8";
154                         gpio-controller;
155                         #gpio-cells = <2>;
156                         interrupt-controller;
157                         #interrupt-cells = <1>;
158                 };
159
160                 i2c1: i2c@48070000 {
161                         compatible = "ti,omap4-i2c";
162                         #address-cells = <1>;
163                         #size-cells = <0>;
164                         ti,hwmods = "i2c1";
165                 };
166
167                 i2c2: i2c@48072000 {
168                         compatible = "ti,omap4-i2c";
169                         #address-cells = <1>;
170                         #size-cells = <0>;
171                         ti,hwmods = "i2c2";
172                 };
173
174                 i2c3: i2c@48060000 {
175                         compatible = "ti,omap4-i2c";
176                         #address-cells = <1>;
177                         #size-cells = <0>;
178                         ti,hwmods = "i2c3";
179                 };
180
181                 i2c4: i2c@4807A000 {
182                         compatible = "ti,omap4-i2c";
183                         #address-cells = <1>;
184                         #size-cells = <0>;
185                         ti,hwmods = "i2c4";
186                 };
187
188                 i2c5: i2c@4807C000 {
189                         compatible = "ti,omap4-i2c";
190                         #address-cells = <1>;
191                         #size-cells = <0>;
192                         ti,hwmods = "i2c5";
193                 };
194
195                 uart1: serial@4806a000 {
196                         compatible = "ti,omap4-uart";
197                         ti,hwmods = "uart1";
198                         clock-frequency = <48000000>;
199                 };
200
201                 uart2: serial@4806c000 {
202                         compatible = "ti,omap4-uart";
203                         ti,hwmods = "uart2";
204                         clock-frequency = <48000000>;
205                 };
206
207                 uart3: serial@48020000 {
208                         compatible = "ti,omap4-uart";
209                         ti,hwmods = "uart3";
210                         clock-frequency = <48000000>;
211                 };
212
213                 uart4: serial@4806e000 {
214                         compatible = "ti,omap4-uart";
215                         ti,hwmods = "uart4";
216                         clock-frequency = <48000000>;
217                 };
218
219                 uart5: serial@48066000 {
220                         compatible = "ti,omap5-uart";
221                         ti,hwmods = "uart5";
222                         clock-frequency = <48000000>;
223                 };
224
225                 uart6: serial@48068000 {
226                         compatible = "ti,omap6-uart";
227                         ti,hwmods = "uart6";
228                         clock-frequency = <48000000>;
229                 };
230
231                 mmc1: mmc@4809c000 {
232                         compatible = "ti,omap4-hsmmc";
233                         ti,hwmods = "mmc1";
234                         ti,dual-volt;
235                         ti,needs-special-reset;
236                 };
237
238                 mmc2: mmc@480b4000 {
239                         compatible = "ti,omap4-hsmmc";
240                         ti,hwmods = "mmc2";
241                         ti,needs-special-reset;
242                 };
243
244                 mmc3: mmc@480ad000 {
245                         compatible = "ti,omap4-hsmmc";
246                         ti,hwmods = "mmc3";
247                         ti,needs-special-reset;
248                 };
249
250                 mmc4: mmc@480d1000 {
251                         compatible = "ti,omap4-hsmmc";
252                         ti,hwmods = "mmc4";
253                         ti,needs-special-reset;
254                 };
255
256                 mmc5: mmc@480d5000 {
257                         compatible = "ti,omap4-hsmmc";
258                         ti,hwmods = "mmc5";
259                         ti,needs-special-reset;
260                 };
261
262                 keypad: keypad@4ae1c000 {
263                         compatible = "ti,omap4-keypad";
264                         ti,hwmods = "kbd";
265                 };
266
267                 mcpdm: mcpdm@40132000 {
268                         compatible = "ti,omap4-mcpdm";
269                         reg = <0x40132000 0x7f>, /* MPU private access */
270                               <0x49032000 0x7f>; /* L3 Interconnect */
271                         reg-names = "mpu", "dma";
272                         interrupts = <0 112 0x4>;
273                         interrupt-parent = <&gic>;
274                         ti,hwmods = "mcpdm";
275                 };
276
277                 dmic: dmic@4012e000 {
278                         compatible = "ti,omap4-dmic";
279                         reg = <0x4012e000 0x7f>, /* MPU private access */
280                               <0x4902e000 0x7f>; /* L3 Interconnect */
281                         reg-names = "mpu", "dma";
282                         interrupts = <0 114 0x4>;
283                         interrupt-parent = <&gic>;
284                         ti,hwmods = "dmic";
285                 };
286
287                 mcbsp1: mcbsp@40122000 {
288                         compatible = "ti,omap4-mcbsp";
289                         reg = <0x40122000 0xff>, /* MPU private access */
290                               <0x49022000 0xff>; /* L3 Interconnect */
291                         reg-names = "mpu", "dma";
292                         interrupts = <0 17 0x4>;
293                         interrupt-names = "common";
294                         interrupt-parent = <&gic>;
295                         ti,buffer-size = <128>;
296                         ti,hwmods = "mcbsp1";
297                 };
298
299                 mcbsp2: mcbsp@40124000 {
300                         compatible = "ti,omap4-mcbsp";
301                         reg = <0x40124000 0xff>, /* MPU private access */
302                               <0x49024000 0xff>; /* L3 Interconnect */
303                         reg-names = "mpu", "dma";
304                         interrupts = <0 22 0x4>;
305                         interrupt-names = "common";
306                         interrupt-parent = <&gic>;
307                         ti,buffer-size = <128>;
308                         ti,hwmods = "mcbsp2";
309                 };
310
311                 mcbsp3: mcbsp@40126000 {
312                         compatible = "ti,omap4-mcbsp";
313                         reg = <0x40126000 0xff>, /* MPU private access */
314                               <0x49026000 0xff>; /* L3 Interconnect */
315                         reg-names = "mpu", "dma";
316                         interrupts = <0 23 0x4>;
317                         interrupt-names = "common";
318                         interrupt-parent = <&gic>;
319                         ti,buffer-size = <128>;
320                         ti,hwmods = "mcbsp3";
321                 };
322         };
323 };