arm: mvebu: Use dw-apb-uart instead of ns16650 as UART driver
[linux-3.10.git] / arch / arm / boot / dts / armada-xp.dtsi
1 /*
2  * Device Tree Include file for Marvell Armada XP family SoC
3  *
4  * Copyright (C) 2012 Marvell
5  *
6  * Lior Amsalem <alior@marvell.com>
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9  * Ben Dooks <ben.dooks@codethink.co.uk>
10  *
11  * This file is licensed under the terms of the GNU General Public
12  * License version 2.  This program is licensed "as is" without any
13  * warranty of any kind, whether express or implied.
14  *
15  * Contains definitions specific to the Armada XP SoC that are not
16  * common to all Armada SoCs.
17  */
18
19 /include/ "armada-370-xp.dtsi"
20
21 / {
22         model = "Marvell Armada XP family SoC";
23         compatible = "marvell,armadaxp", "marvell,armada-370-xp";
24
25         L2: l2-cache {
26                 compatible = "marvell,aurora-system-cache";
27                 reg = <0xd0008000 0x1000>;
28                 cache-id-part = <0x100>;
29                 wt-override;
30         };
31
32         mpic: interrupt-controller@d0020000 {
33               reg = <0xd0020a00 0x1d0>,
34                     <0xd0021070 0x58>;
35         };
36
37         armada-370-xp-pmsu@d0022000 {
38                 compatible = "marvell,armada-370-xp-pmsu";
39                 reg = <0xd0022100 0x430>,
40                       <0xd0020800 0x20>;
41         };
42
43         soc {
44                 serial@d0012200 {
45                                 compatible = "snps,dw-apb-uart";
46                                 reg = <0xd0012200 0x100>;
47                                 reg-shift = <2>;
48                                 interrupts = <43>;
49                                 reg-io-width = <4>;
50                                 status = "disabled";
51                 };
52                 serial@d0012300 {
53                                 compatible = "snps,dw-apb-uart";
54                                 reg = <0xd0012300 0x100>;
55                                 reg-shift = <2>;
56                                 interrupts = <44>;
57                                 reg-io-width = <4>;
58                                 status = "disabled";
59                 };
60
61                 timer@d0020300 {
62                                 marvell,timer-25Mhz;
63                 };
64
65                 coreclk: mvebu-sar@d0018230 {
66                         compatible = "marvell,armada-xp-core-clock";
67                         reg = <0xd0018230 0x08>;
68                         #clock-cells = <1>;
69                 };
70
71                 cpuclk: clock-complex@d0018700 {
72                         #clock-cells = <1>;
73                         compatible = "marvell,armada-xp-cpu-clock";
74                         reg = <0xd0018700 0xA0>;
75                         clocks = <&coreclk 1>;
76                 };
77
78                 gateclk: clock-gating-control@d0018220 {
79                         compatible = "marvell,armada-xp-gating-clock";
80                         reg = <0xd0018220 0x4>;
81                         clocks = <&coreclk 0>;
82                         #clock-cells = <1>;
83                 };
84
85                 system-controller@d0018200 {
86                                 compatible = "marvell,armada-370-xp-system-controller";
87                                 reg = <0xd0018200 0x500>;
88                 };
89
90                 ethernet@d0030000 {
91                                 compatible = "marvell,armada-370-neta";
92                                 reg = <0xd0030000 0x2500>;
93                                 interrupts = <12>;
94                                 clocks = <&gateclk 2>;
95                                 status = "disabled";
96                 };
97
98                 ethernet@d0034000 {
99                                 compatible = "marvell,armada-370-neta";
100                                 reg = <0xd0034000 0x2500>;
101                                 interrupts = <14>;
102                                 clocks = <&gateclk 1>;
103                                 status = "disabled";
104                 };
105
106                 xor@d0060900 {
107                         compatible = "marvell,orion-xor";
108                         reg = <0xd0060900 0x100
109                                0xd0060b00 0x100>;
110                         clocks = <&gateclk 22>;
111                         status = "okay";
112
113                         xor10 {
114                                 interrupts = <51>;
115                                 dmacap,memcpy;
116                                 dmacap,xor;
117                         };
118                         xor11 {
119                                 interrupts = <52>;
120                                 dmacap,memcpy;
121                                 dmacap,xor;
122                                 dmacap,memset;
123                         };
124                 };
125
126                 xor@d00f0900 {
127                         compatible = "marvell,orion-xor";
128                         reg = <0xd00F0900 0x100
129                                0xd00F0B00 0x100>;
130                         clocks = <&gateclk 28>;
131                         status = "okay";
132
133                         xor00 {
134                                 interrupts = <94>;
135                                 dmacap,memcpy;
136                                 dmacap,xor;
137                         };
138                         xor01 {
139                                 interrupts = <95>;
140                                 dmacap,memcpy;
141                                 dmacap,xor;
142                                 dmacap,memset;
143                         };
144                 };
145         };
146 };