6 years agoregulator: palmas: implement sleep mode configuration
Laxman Dewangan [Mon, 18 Feb 2013 14:39:00 +0000]
regulator: palmas: implement sleep mode configuration

Palma is having different set of bits to configure sleep mode.
Implement the set_sleep_mode for core to configure these bits.

Change-Id: If78c95a3da5a1f875d8588a997c85f1bf01c9638
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/201793

6 years agoregulator: add support for sleep mode configuration
Laxman Dewangan [Mon, 18 Feb 2013 14:37:37 +0000]
regulator: add support for sleep mode configuration

Some of PMIC like Palma support different bits for configuring
rail's mode which is used in sleep mode of device.

Add support for configuring this mode bits.

Change-Id: Ib1bbc5164bf71c75c727dc759436e8dcf206f511
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/201792

6 years agoARM: tegra11: clock: Relax CPU rate increase warning check
Alex Frid [Sun, 17 Feb 2013 08:50:05 +0000]
ARM: tegra11: clock: Relax CPU rate increase warning check

Do not generate warning on CPU rate increase before dvfs regulators
are connected if target rate is below boot rate.

Change-Id: Ic8357f781029d4dab169b22a08333ff5b9472847
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/201539
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra: clock: Record boot rates for all clocks
Alex Frid [Sun, 17 Feb 2013 08:46:46 +0000]
ARM: tegra: clock: Record boot rates for all clocks

Change-Id: Ibb376c7251e453c207f8bbd6e7d65642eac8aea6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/201538
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

6 years agoARM: tegra11: clock: Fix boot over-clocking warnings
Alex Frid [Sun, 17 Feb 2013 08:39:45 +0000]
ARM: tegra11: clock: Fix boot over-clocking warnings

- Increase maximum rate for secondary PLLM output to the main PLLM
output limit
- Removed non supported sata clocks from the clock tree

Change-Id: I208df494a41ed620937086feb0271cd1dc85a5b6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/201537
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: Tegra: Roth: Update Memory Config
Matt Wagner [Fri, 15 Feb 2013 02:10:11 +0000]
ARM: Tegra: Roth: Update Memory Config

Change VTTGEN controls and add 900Mhz

Bug 1181038

Change-Id: Ie5a98c25cea6e0906f90cdde4413c4c2030bcf1b
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/200990
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agonvhost: tsec: make sure kfuse is pointed to hdmi.
Marvin Zhang [Thu, 14 Feb 2013 02:57:12 +0000]
nvhost: tsec: make sure kfuse is pointed to hdmi.

tsec needs to get pkey from kfuse by changing kfuse mux to tsec,
after tsec is done, it restores mux back to hdmi so that latter
can use it to load hdcp keys.

Bug 1235326

Change-Id: I52459a67159583f3f120fe8a8cbc1ea1ec4b13c7
Signed-off-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-on: http://git-master/r/200654
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agovideo: tegra: host: retune 3dfs algorithm for 114
Samuel Russell [Wed, 13 Feb 2013 23:43:59 +0000]
video: tegra: host: retune 3dfs algorithm for 114

Adjust the tuning of 3dfs for 114 chips to perform better for
increased POR clocks.

Bug 1220024
Bug 1232650
Bug 1231533

Change-Id: I2e5ff3e86c84fc2180c8500e6d109fe85410d833
Signed-off-by: Samuel Russell <samuelr@nvidia.com>
Reviewed-on: http://git-master/r/200582
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijay Gupta <vijayg@nvidia.com>
Tested-by: Vijay Gupta <vijayg@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoARM: tegra: pluto: Pass nominal core voltage
Pavan Kunapuli [Wed, 13 Feb 2013 10:56:30 +0000]
ARM: tegra: pluto: Pass nominal core voltage

Pass nominal core voltage value through mmc platform data to be used
for setting core voltage constraints during tuning.
Set sdmmc4 clk limit to 156MHz for HS200 mode.

Bug 1167519
Bug 1225343

Change-Id: Ibb93345bee9407ed12cfa2b2202016d9908b00d4
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/200410
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra: pluto: vdd_core consumers for sdmmc
Pavan Kunapuli [Wed, 13 Feb 2013 10:50:40 +0000]
ARM: tegra: pluto: vdd_core consumers for sdmmc

Adding vdd_core regulators for sdmmc1 and sdmmc4 to be used for
setting core voltage constraints during frequency tuning.

Bug 1167519
Bug 1225343

Change-Id: I6708256280a9aeeb0f174e4cdafcc67f7ed5ec17
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/200409
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra: dalmore: Pass nominal core voltage
Pavan Kunapuli [Wed, 13 Feb 2013 10:10:50 +0000]
ARM: tegra: dalmore: Pass nominal core voltage

Pass nominal core voltage data through sdhci platform data to be
used for setting core voltage constraints during frequency tuning.

Bug 1167519
Bug 1225343

Change-Id: I709b18c163178c24e819fcd940f71656780d94fa
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/200396
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra: Add support to parse power-config
Pradeep Goudagunta [Wed, 28 Nov 2012 05:04:58 +0000]
ARM: tegra: Add support to parse power-config

Add support to parse power-config from linux command line. Which
is used to configure power rails.

Bug 1235384

Change-Id: I93e15ff6aeb5121c47475a6c13d12fc81087aa49
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/198782
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agommc: tegra: Enable HS200 mode support
Pavan Kunapuli [Fri, 1 Feb 2013 17:02:38 +0000]
mmc: tegra: Enable HS200 mode support

Set MMC_CAP2_HS200 to enable HS200 mode support.
Increase sdmmc4 base clock frequency of T114 chip to 208MHz.

Bug 1225343

Change-Id: Ica171c8fe093f0c0ab35b4c46c2dcebaecf25134
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/196484
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agonvhdcp: return bksv_list for upstream protocol.
Marvin Zhang [Wed, 9 Jan 2013 19:04:04 +0000]
nvhdcp: return bksv_list for upstream protocol.

add returning bksv_list support from function get_nvhdcp_state.
upstream library gets bksv_list and passes it to tsec in order
to verify the validity of downstream devices.

Bug 1197884

Change-Id: I58ba2c5c4200ffb95ab9f929eecb1e9ebb60b5c9
Signed-off-by: Marvin Zhang <mzhang@nvidia.com>
Reviewed-on: http://git-master/r/190034
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: James Zhao <jamesz@nvidia.com>
Tested-by: James Zhao <jamesz@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agovideo: tegra: host: Enable stub runtime PM
Prashant Gaikwad [Mon, 18 Feb 2013 11:50:08 +0000]
video: tegra: host: Enable stub runtime PM

Add stub runtime_pm calls which go through the flow of enabling and
disabling but don't actually do anything with the device itself as
there's nothing useful we can do. This provides the core PM framework
with information about when the device is idle, enabling chip wide
power savings.

Bug 1010971

Change-Id: I8d9ccffa2ed39bc10b83848cee0d864dfd129dcb
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
(cherry picked from commit d1a55908606946d2727ae79d8b8d2201cc813965)
Reviewed-on: http://git-master/r/201882
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoEDP: makefile restructuring
Sivaram Nair [Mon, 18 Feb 2013 21:30:19 +0000]
EDP: makefile restructuring

CONFIG_EDP_FRAMEWORK is removed from the make file - it is already used
by the parent makefile, so it is not needed here.

Change-Id: Ibec618b6dda735f0ba54f466d17b364f12cd91fc
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/201841
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agommc: tegra: Restore tuned tap value in resume
Pavan Kunapuli [Mon, 18 Feb 2013 12:18:29 +0000]
mmc: tegra: Restore tuned tap value in resume

For devices that are powered on across suspend, restore the tuned
tap value during resume. In other cases, set the default tap value.

Bug 1237695

Change-Id: I38ba01931267d7e6c79b32a4855b4bb60a1ce003
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/201752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agopower: bq2419x: Clear EN_HIZ bit
Syed Rafiuddin [Mon, 18 Feb 2013 10:00:58 +0000]
power: bq2419x: Clear EN_HIZ bit

HIZ disables USBFET and stops battery charging.
WAR is to clear this bit on every hotplug event.

Bug 1237492

Change-Id: I5ec69d58a5187d223a723e848ab6ef8fa2360bf6
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/201363
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agovideo: tegra: dc: Bail out on incorrect window attributes
Raghavendra VK [Fri, 18 Jan 2013 19:16:11 +0000]
video: tegra: dc: Bail out on incorrect window attributes

bug 1066942

Change-Id: I139b6a340ba570ff020cc41ec6ad219c578e14f9
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/192455
(cherry picked from commit ba14b64bd23027a336fa70a2e2ee9264c36d4b94)
Reviewed-on: http://git-master/r/201261
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agovideo: tegra: dc: report correct device id in traces
Jon Mayo [Thu, 3 Jan 2013 18:09:52 +0000]
video: tegra: dc: report correct device id in traces

Display traces were reporting everything as dc0. This fixes that issue.

Change-Id: If1378a8777dbd83484b62f44c6138068ff06bd66
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/188357
(cherry picked from commit 131421550c664268df2036c41ccddb9db4463451)
Reviewed-on: http://git-master/r/201232

6 years agonet: wireless: bcmdhd: add multi rev support for bcm43341
Nagarjuna Kristam [Fri, 15 Feb 2013 07:00:37 +0000]
net: wireless: bcmdhd: add multi rev support for bcm43341

switch to appropriate nvram and firmware file based on cis data

Bug 1192564

Change-Id: Icbab7e254be3dd8354843066cd2d30018f466af9
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/201047
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agousb: gadget: tegra: check connect_type before SET_ADDRESS
Rohith Seelaboyina [Fri, 15 Feb 2013 08:34:38 +0000]
usb: gadget: tegra: check connect_type before SET_ADDRESS

connect_type is to be checked before assigning address
to the device

Bug 1225941

Change-Id: I25aa9106f33c0c0cb47829a6e5c995c645ecfcb1
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/201033
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoarm: tegra: macallan: Fix for delay in display on wakeup from LP0
Joshua Cha [Thu, 14 Feb 2013 07:44:53 +0000]
arm: tegra: macallan: Fix for delay in display on wakeup from LP0

Fix for delay in display to turn on while waking up from LP0

Bug 1223101

Change-Id: I0fb3f7f2785cfe21f16afb2c66207316b49ffb4f
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/200709
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agopower: max17048: show status as full when 100% charged
Syed Rafiuddin [Tue, 19 Feb 2013 08:40:59 +0000]
power: max17048: show status as full when 100% charged

Update status as full when state of charge is 100%
charged.

Bug 1234697

Change-Id: I7c113ef254b848e8374d5251a4cf7d6dcedcf022
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/200702
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra11: clock: Update emc to cpu rate ratio
Amit Kamath [Tue, 12 Feb 2013 12:38:18 +0000]
ARM: tegra11: clock: Update emc to cpu rate ratio

The gain for performance to frequency in not proportionate at higher
emc frequencies. Hence limiting the highest emc frequency for above
1.5 Ghz of cpu frequency.

Bug 1172722

Change-Id: I379a57f2d94f2442664bb580f9ce6048c5b69fe0
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/199980
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra11x: Fix sdram self-refresh entry/exit
Bo Yan [Fri, 15 Feb 2013 03:07:33 +0000]
ARM: tegra11x: Fix sdram self-refresh entry/exit

T114 has dual EMC, so program both channels.

Also make sure setting slave mode when configuring auto-cal in
slave channel

Change-Id: Ieb6148417e248aa380074bcd9e250311727dd1bc
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/201201
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agospi: tegra11: Update debug print
Vijay Mali [Tue, 12 Feb 2013 11:53:25 +0000]
spi: tegra11: Update debug print

dev_info -> dev_dbg

Change-Id: I28d4ee1b3c0d43f95ac073be0480cee865deefa9
Signed-off-by: Vijay Mali <vmali@nvidia.com>
Reviewed-on: http://git-master/r/199996
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoasoc: tegra: Protect against invalid gpio writes
Scott Peterson [Sat, 9 Feb 2013 01:14:17 +0000]
asoc: tegra: Protect against invalid gpio writes

Protect against calling gpio_direction_output()
with an innvalid gpio handle.

Bug 1233665

Change-Id: I00dc7a2a254c7f57ba2894328abd52324bcb304d
Signed-off-by: Scott Peterson <speterson@nvidia.com>
Reviewed-on: http://git-master/r/198978
Reviewed-by: Anshul Jain (SW) <anshulj@nvidia.com>
Reviewed-by: Matt Wagner <mwagner@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoarm:misc: Change tfa9887 driver debug spew
Scott Peterson [Sat, 9 Feb 2013 00:17:25 +0000]
arm:misc: Change tfa9887 driver debug spew

Changed the driver for the tfa8997 device so that
it only prints a message for the SetParam function
if there is an error and audio is playing. If audio
is not playing access to the device is not possible
so an error is expected.

Bug 1233775

Change-Id: I5e3b4f7958104d28c74dac730ea936efed567325
Signed-off-by: Scott Peterson <speterson@nvidia.com>
Reviewed-on: http://git-master/r/198963
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Niranjan Wartikar <nwartikar@nvidia.com>
Reviewed-by: Shaoming Feng <shaomingf@nvidia.com>

6 years agoaudio: a2220: Fix the wrong GPIO for reset
Bo Yan [Sat, 8 Dec 2012 03:06:31 +0000]
audio: a2220: Fix the wrong GPIO for reset

gpio number for reset is not specified in platform data, in fact, its
value is 0 after kzalloc.  Requesting gpio for this number is bad
because the pin for GPIO 0 is used for other purposes. The original
hack is to use a magic number 118 for reset GPIO, this still needs to
be fixed. Meanwhile, to unblock the work which requires GPIO 0,
do not request GPIO 0 in this module.

Change-Id: Ibe1c38e948603fcd1d9de1164d5f69b0804757d2
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/169562
(cherry picked from commit 2cf6fa583d1eb1f993cd1b7b5fe9cab8fcc55fb3)
Reviewed-on: http://git-master/r/201516
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>

6 years agoarm: tegra: Add raydium touch clock names for macallan
Hyongbin Kim [Fri, 15 Feb 2013 10:32:19 +0000]
arm: tegra: Add raydium touch clock names for macallan

This change is missing fix of http://git-master/r/172909 for macallan

Change-Id: I7af726ff97801ffa672125855abfea54760efbb7
Signed-off-by: Hyongbin Kim <hyongbink@nvidia.com>
Reviewed-on: http://git-master/r/201119
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>

6 years agoARM: tegra: roth: enable dma based spi transfer for Tegra114-A02 and later
Laxman Dewangan [Fri, 15 Feb 2013 09:50:57 +0000]
ARM: tegra: roth: enable dma based spi transfer for Tegra114-A02 and later

Tegra114-A02 and later SoCs have fixed the hw issue of dma based
spi transfer. Hence removing the limitation of not using dma based
transfer.

Change-Id: I622fc826e15ddd08cc07500217235662674b1dea
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/201098
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agovideo: tegra: dc: match HDMI mode aspect ratio
Jon Mayo [Fri, 15 Feb 2013 00:30:08 +0000]
video: tegra: dc: match HDMI mode aspect ratio

Bug 1227041
Bug 1232636

Change-Id: I49823f8c4f53332f1adbf677e44323a60bce38e2
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/201012

6 years agoarm: tegra: roth: Set initialized mode for panel
Rakesh Iyer [Thu, 14 Feb 2013 20:43:03 +0000]
arm: tegra: roth: Set initialized mode for panel

Set initialized mode only for roth panel. This excludes dalmore 5''.

Bug 1219004

Change-Id: I5944b8aa0770610d07ddc891be72cd22b5245f6a
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/200901
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agocdc_ncm: fix TCP window scaling issue for NCM driver
Steve Lin [Thu, 14 Feb 2013 22:08:05 +0000]
cdc_ncm: fix TCP window scaling issue for NCM driver

TCP network stack uses skb->truesize as hint to grow TCP window size.
However, the NCM driver uses skb_clone to push the ethernet packet to
the network stack. The skb->truesize is actually the memory allocated
for the whole transfer block, not the true packet size with overhead.
tcp_grow_window function doesn't handle this case properly so the
receiver window will not grow. This patch is to update the skb->truesize
in the cdc_ncm_rx_fixup function so the TCP stack can use it to grow the
window size as expected.

Bug 1207244
Bug 1235981

Change-Id: I7c48eb65e7f991d7eb0f2ef14c515134b9180ea4
Signed-off-by: Steve Lin <stlin@nvidia.com>
Reviewed-on: http://git-master/r/200895
Reviewed-by: David Norman <dnorman@nvidia.com>
Reviewed-by: Rick Song <ricks@nvidia.com>

6 years agoARM: tegra11: Include temperature offset to CPU EDP management
Diwakar Tundlam [Tue, 12 Feb 2013 19:55:09 +0000]
ARM: tegra11: Include temperature offset to CPU EDP management

Fixed setting of DOWN threshold by adjusting hysteresis correctly for
precision. Made temperatures array be at 4 degree intervals above 70C
because of 2C rounding required for soctherm temperature thresholds.

Bug 1233302

Change-Id: I2dc0966fdc3ba81d6e29b8dd0095b165bf2ae7bc
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/200216
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agopower: max17048: work schedule funtion
Darbha Sriharsha [Tue, 12 Feb 2013 05:21:19 +0000]
power: max17048: work schedule funtion

This change is intended to change the call to schedule_work function
to schedule_delayed_work instead as the argument passed is of type
"struct delayed_work" as opposed to "struct work_struct" and this
difference causes a compiler warning to be thrown up

Bug 1234460

Change-Id: I4142c6c7db5595475b380c0bf41fd9df9f48dd78
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/199874
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agopower: bq2419x: Removing disable fucntion
Darbha Sriharsha [Tue, 12 Feb 2013 04:55:17 +0000]
power: bq2419x: Removing disable fucntion

This change is intended to remove the function bq2419x_charger_disable
as it is never called and causes a compiler warning to be thrown up.

Bug 1234460

Change-Id: I109c1a48743fcae44a36c921a4f0d9834902023a
Signed-off-by: Darbha Sriharsha <dsriharsha@nvidia.com>
Reviewed-on: http://git-master/r/199871
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agotegra11: nvavp: clock: increase sclk boost frequency
Li Li [Mon, 4 Feb 2013 21:46:30 +0000]
tegra11: nvavp: clock: increase sclk boost frequency

25x16 panel requires higher slck frequency than 19x12. So increase the sclk
from 40MHz to 80MHz. This reuses the mechanism in existing avp driver. Previous
code is to boost sclk when display is turned on to prevent glitch audio. It's
general enough so not necessary to introduce another duplicate framework just
to boost sclk for similar performance issues.

And, this is only for runtime boosting. When system is idle with display off,
previous commit 9f82f47 (ARM: tegra11: clock: decrease sclk min limit) has
ensured that the sclk is at the lowest possible speed to save power.

Bug 1211941

Change-Id: I4a3c7b6ccfbb4681b644c68b829508c3660c800f
Signed-off-by: Li Li <lli5@nvidia.com>
Reviewed-on: http://git-master/r/197156
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Peter Zu <pzu@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agodrivers: net: wireless: bcmdhd: fix WPS association race condition
Narayan Reddy [Fri, 15 Feb 2013 09:26:52 +0000]
drivers: net: wireless: bcmdhd: fix WPS association race condition

When association failed, supplicant always sends re-association
rather than assoc. With this pattern, there is a potential
problem from wpa-supplicant with respect to WPS association
after provisioning. When supplicant requests disassociate, the
state of supplicant is changed to DISCONNECTED by disconnect
event from the cfg80211(driver) layer in normal case. However,
in this case (post provisioning assoc), supplicant requests
disassociate and send locally generated event to
itself and changes state to DISCONNECTED. Therefore, sometimes
the association request is coming to cfg80211/driver while
driver is processing disassociating (before link down event
come from the f/w). This conflict between disassociation processing
and association request make re-association request in the f/w and
resulted in association failure.

To avoid this conflict, supplicant should wait for the
disconnected event from the driver. Thus modified driver
to hold association request until disassociation is finished.
In most case, link event comes from f/w within 50 ms.

Bug 1232700

Change-Id: I7ac9b6edc3675dabc04131d562bb839187e73ad3
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: http://git-master/r/201116
Reviewed-by: Kyeong Kim <kyeongk@nvidia.com>
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: teagr11: power: Don't put PLLC in IDDQ on LP1 entry
Alex Frid [Fri, 15 Feb 2013 07:57:50 +0000]
ARM: teagr11: power: Don't put PLLC in IDDQ on LP1 entry

Change-Id: I5cfc4cb611b2610cfb84e64937c09cc5b994ad18
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/201058
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra: Fix CPU boot for non-SMP build
Bo Yan [Thu, 14 Feb 2013 19:12:51 +0000]
ARM: tegra: Fix CPU boot for non-SMP build

For non-SMP build, CONFIG_HAVE_ARM_SCU is not enabled, the current
sequence of CPU boot initialization is wrong. Fix this by checking
MIDR register, and only invalidate SCU tag if CONFIG_HAVE_ARM_SCU
is defined.

bug 1230270

Change-Id: I17bf0b45cd543c6b21030f7c07cf8568540afcdc
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/200844
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>

6 years agoARM: tegra: cpuquiet: Honor G->LP delay on last core down
Peter Boonstoppel [Thu, 31 Jan 2013 21:22:02 +0000]
ARM: tegra: cpuquiet: Honor G->LP delay on last core down

We cluster switch G->LP when 2 conditions are met:
1) we are in single core mode
2) CPU freq reaches idle_bottom_freq

After these 2 conditions are met, we wait for down_delay ms before
cluster switching. This patch ensures the timeout is also honored when
the first condition is met last.

Bug 1226607

Change-Id: Ic36f9cab09a5967b71409e44dbe89290f39cb26b
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/200537
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra: dalmore: Unmask HS200 mode support
Pavan Kunapuli [Thu, 14 Feb 2013 22:34:04 +0000]
ARM: tegra: dalmore: Unmask HS200 mode support

Unmasking HS200 mode support and setting 156MHz as the clock limit
for HS200 mode.

Bug 1225343

Change-Id: Id5949c1bb85046032eb3399fb1663f0587cabb87
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/200395
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rama Kandhala <rkandhala@nvidia.com>

6 years agoARM: tegra11: dvfs: Update switch between DFLL and PLL
Alex Frid [Tue, 12 Feb 2013 19:04:40 +0000]
ARM: tegra11: dvfs: Update switch between DFLL and PLL

Modified procedures for auto-switching between PLL and DFLL CPU clock
sources.

- On switch from PLL to DFLL do not allow legacy DVFS to set voltage
for target rate in one shot. Limit setting to minimum DFLL voltage,
and let DFLL to complete voltage ramp after the switch.

- Similarly on switch from DFLL to PLL, first use DFLL mode to lower
cpu voltage to DFLL minimum, leaving only delta down to target for
legacy DVFS.

This modifications speed up the transitions and make them safer, since
major change of voltage, rate, and consumed current happens in DFLL
mode.

Change-Id: I42eee166510bd74d046bc6b3cb232ca10233ead9
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/200382
Reviewed-by: Mandar Padmawar <mpadmawar@nvidia.com>
Tested-by: Mandar Padmawar <mpadmawar@nvidia.com>

6 years agoARM: tegra: macallan: bringup e1625 camera board
Charlie Huang [Tue, 12 Feb 2013 00:05:21 +0000]
ARM: tegra: macallan: bringup e1625 camera board

bug 1228759

Change-Id: I049dfd91a01b2706bfb1a094d771ee44962fe980
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/199782
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>

6 years agoarm: mach-tegra: resolve tegra_cpu_lock race condition
Sang-Hun Lee [Mon, 11 Feb 2013 01:48:24 +0000]
arm: mach-tegra: resolve tegra_cpu_lock race condition

Problem description:

 - lock used in cpuquiet, cpu-tegra3.c, tegra2-throttle.c, and tegra3_throttle
   originate from cpu-tegra.c, tegra_cpu_lock
 - edp_update_limit and tegra_auto_hotplug_governor need a protection from
   tegra_cpu_lock. These are also called by tegra_cpu_set_speed_cap
 - Some callers of tegra_cpu_set_speed_cap do not acquire tegra_cpu_lock,
   but some do

Fix description:

 - Create a locked variant and unlocked variant of tegra_cpu_set_speed_cap
   to make it explicit that tegra_cpu_lock is needed for tegra_cpu_set_speed_cap
 - Replace existing calls with new variants of tegra_cpu_set_speed_cap appropriately

Bug 1225764

Change-Id: I8aa6356df278375e3a9105023f66c8286e3fdbef
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/199238
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoARM: tegra11x: Fix time accounting in power down
Bo Yan [Thu, 14 Feb 2013 17:53:24 +0000]
ARM: tegra11x: Fix time accounting in power down

Include the time of Fmin@Vmin state in the time spent in power down.
After this change, the time spent in cpu powered down state as
reported by kernel cpuidle infrastructure will also include time
spent in Fmin@Vmin state. This makes sense because Fmin@Vmin currently
is implemented as a sub-state of "cpu powered down".

bug 1235206

Change-Id: I94b3829f70ebcefe6741e9f0d8c92936705f229c
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/200822
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoasoc: AIC3262: Enable headset mic
Vijay Mali [Thu, 14 Feb 2013 06:54:07 +0000]
asoc: AIC3262: Enable headset mic

Fix no upstream audio in voice call.

For bug 1236029

Change-Id: Ifeef0c03ab12c851e1f148ef9ffc5311e7eecea6
Signed-off-by: Vijay Mali <vmali@nvidia.com>
Reviewed-on: http://git-master/r/200700
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: enable unaligned_dma_buf_support
Rohith Seelaboyina [Thu, 14 Feb 2013 15:32:56 +0000]
ARM: tegra: enable unaligned_dma_buf_support

enable unalgined_dma_buf_support for boards in which
h/w fix is enabled.

Bug 1235943

Change-Id: Idaead18f21b554a9888f30ec9796125aabd4ab72
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/200471
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: usb_phy: Enable h/w mem_alignment and coherency
Rohith Seelaboyina [Fri, 15 Feb 2013 05:30:44 +0000]
ARM: tegra: usb_phy: Enable h/w mem_alignment and coherency

Remove the S/W WAR and enable the mem_alignment
and coherency in h/w.

Bug 1235943

Change-Id: Ic75ce854389ce40e3b3d48caeb309df3d18aeecc
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/200470
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agousb: gadget: tegra: Remove S/W WAR for mem_alignment
Rohith Seelaboyina [Thu, 14 Feb 2013 14:34:07 +0000]
usb: gadget: tegra: Remove S/W WAR for mem_alignment

Remove S/W WAR for mem_alignment and coherency on T114 A02
as  h/w fix is enabled in driver.

Bug 1235943

Change-Id: I8ec2839249669bfef4af715a7fa8b254f346ade2
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: http://git-master/r/200469
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agoARM: tegra: dalmore: vdd_core consumers for sdmmc
Pavan Kunapuli [Wed, 13 Feb 2013 10:01:27 +0000]
ARM: tegra: dalmore: vdd_core consumers for sdmmc

Adding vdd_core regulators for sdmmc1 and sdmmc4 to be used to set
core voltage constraints during frequency tuning.

Bug 1189241

Change-Id: I5708c4023947ece22947d8d97243e51733173aa3
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/200394
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoarm: tegra: baseband: add shutdown for safe down.
Shawn Joo [Wed, 2 Jan 2013 05:52:00 +0000]
arm: tegra: baseband: add shutdown for safe down.

when reboot or power off, baseband should be off safely by calling right shutdown process.
add shutdown callback.

Bug 1210566

Change-Id: I26cf97e73f5234df875407aeb8db8c67b317d778
Signed-off-by: Shawn Joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/188509
(cherry picked from commit 0febbb5fb8ca7a2e0cc44088b3a1f582437d9e78)
Reviewed-on: http://git-master/r/199082
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>

6 years agoARM: Tegra: Roth/Macallan: Remove wakeup_key callback
Matt Wagner [Thu, 14 Feb 2013 23:49:08 +0000]
ARM: Tegra: Roth/Macallan: Remove wakeup_key callback

We now handle this in the wakeup code.  Support is no longer needed here.

Bug 1220330

Change-Id: I0ad1ed928413da19089519b62dbc53f59e9f9718
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/200942
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoInput: gpio_keys: Remove Wakeup Key Handling
Matt Wagner [Thu, 14 Feb 2013 02:29:18 +0000]
Input: gpio_keys: Remove Wakeup Key Handling

This handling is done elsewhere and doesn't belong in gpio_keys anymore

Bug 1220330

Change-Id: Ibe74f650eedc2f2df93ea8b2c542ba8ad27d9ea2
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/200642
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agortc: palmas: Clear all interrupt of RTC during init
Laxman Dewangan [Thu, 14 Feb 2013 09:55:20 +0000]
rtc: palmas: Clear all interrupt of RTC during init

There is a false wakeup from Palma RTC in suspend state of system.
Following changes are done to fix this issue:
- Clear all intrruprs of RTC during initialization,
- make RTC interrupt as early resume and
- do not enable the interrupt in suspend, as the interrupt get
  enabled when user sets the alarm.

Add debug prints on rtc callbacks for tracing the activity happen with
RTC hardware to catch any false setting/alarm/wakeup.

bug 1227717

Change-Id: I18a5a0a845dcf036d6ffea8a350f5d32fef83e5d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/200736
Reviewed-by: Automatic_Commit_Validation_User

6 years agovideo: tegra: nvmap: flush deferred cache ops on delete
Kirill Artamonov [Wed, 13 Feb 2013 20:52:37 +0000]
video: tegra: nvmap: flush deferred cache ops on delete

We don't flush deferred cache ops if handle is deleted. Because of
that it can still be referenced in deferred queue after deletion
until full deferred queue flush. The situation is rare in real life,
because usually ops are flushed when handle is pinned or full
L1/L2 flush is triggered, The bug was exposed by nvmap stresstester.

Flush deferred cache ops if handle is deleted.

bug 1229518
bug 1236133

Change-Id: Icd888e63f3f11bc6bac137ac23c4a8d238fb406e
Signed-off-by: Kirill Artamonov <kartamonov@nvidia.com>
Reviewed-on: http://git-master/r/200519
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoARM: tegra: macallan: Enable sd_detect_in_suspend flag
Joshua Cha [Thu, 14 Feb 2013 08:13:20 +0000]
ARM: tegra: macallan: Enable sd_detect_in_suspend flag

card detection tasklet will be called to detect sd card

Bug 1231010

Change-Id: I7033dead51823b6a4490184e3ab5ae7567f13415
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/200715
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

6 years agoARM: tegra11: dvfs: Update DFLL minimum voltage
Alex Frid [Sun, 10 Feb 2013 05:29:06 +0000]
ARM: tegra11: dvfs: Update DFLL minimum voltage

Bug 1223242

Change-Id: I438b651a92de4121da69e82b8dbcef14980fc991
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/200381
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoARM: tegra11: dvfs: Update sdmmc4 dvfs table
Alex Frid [Fri, 8 Feb 2013 06:48:33 +0000]
ARM: tegra11: dvfs: Update sdmmc4 dvfs table

Bug 1161126

Change-Id: Ie223958eae722805c2b72214c1555aad64e27a39
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/198691
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agousb: xhci: tegra: fix pad programming
Ajay Gupta [Tue, 12 Feb 2013 00:37:52 +0000]
usb: xhci: tegra: fix pad programming

Fixes PAD programming for Dalmore board.

Change-Id: I8a0498c2399dd670d5bb752f34d3961498f88cce
Signed-off-by: Bharath Yadav <byadav@nvidia.com>
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/200518
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agousb: xhci: tegra: clear both ss and hs wake interrupt
Ajay Gupta [Tue, 12 Feb 2013 19:38:17 +0000]
usb: xhci: tegra: clear both ss and hs wake interrupt

This fixes soft lockup for CPU#0 issue seen with ELPG cycle run with
SS hub connected with SS, HS, FS and LS devices.

We need to clear both SS and HS wake interrupt in ELPG exit path.

Bug 1233377

Change-Id: I34881269a93414991ff89c31e63c6f7f3153009a
Signed-off-by: Bharath Yadav <byadav@nvidia.com>
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/200517
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

6 years agovideo: tegra: nvmap: Fix race condition in dupes dec
Krishna Reddy [Fri, 1 Feb 2013 20:29:54 +0000]
video: tegra: nvmap: Fix race condition in dupes dec

- Handle reference could be freed in the slow path. Hence, keep a copy
  of handle ptr.

Bug 1221693

Change-Id: Ia63df654c3f6f8eb2fcabbff13d413cf32251c42
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/196545
(cherry picked from commit d72027856afa7905bf3361648987abc7bef5f8c0)
Reviewed-on: http://git-master/r/200503
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: Tegra: Roth/Pluto/Dalmore: Clear fb2 if unspecified
Matt Wagner [Fri, 8 Feb 2013 21:34:23 +0000]
ARM: Tegra: Roth/Pluto/Dalmore: Clear fb2 if unspecified

Clear framebuffer2 if and only if framebuffer2 is not specified by the
bootloader. If the bootloader framebuffer2 is specified, then copy the
contents to kernel framebuffer2.

Bug 1229981

Change-Id: Ia3b8df61b2ff449f69dd738096ff80b46af4a57f
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/198903
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoconfig: tegra11: bluetooth support on dalmore
Mursalin Akon [Thu, 7 Feb 2013 20:01:45 +0000]
config: tegra11: bluetooth support on dalmore

This CL includes changes to
- move from built-in to module for all of the
bluetooth kernel components
- add support for couple of bluetooth HID devices

Bug 1223876

Change-Id: Ida7c899a5bea9702564e1e2ba6fd170d5b2ae9b0
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/198473
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

6 years agoARM: tegra: macallan: Upgrade CL-DVFS disable output ops
Joshua Cha [Thu, 14 Feb 2013 09:44:37 +0000]
ARM: tegra: macallan: Upgrade CL-DVFS disable output ops

Bug 1235511

Change-Id: I18eb9f077a2ae0c3ccf73f450e3831acdc3bd11c
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/200731
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: macallan: sensor: Fix regulator warning
Joshua Cha [Wed, 13 Feb 2013 04:49:31 +0000]
ARM: tegra: macallan: sensor: Fix regulator warning

Bug 1232855

Change-Id: Ibddbf1200dd7cf5344ea084854a64a50afd4a358
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/200342
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: roth: add missing pwrdet regulator entries
Bitan Biswas [Mon, 11 Feb 2013 14:43:10 +0000]
ARM: tegra: roth: add missing pwrdet regulator entries

bug 1233759

Change-Id: I2b6c191649210d6d58e37e3eb5da3b330b28b7f1
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/199454
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: dalmore/pluto: Mask eMMC HS200 mode
Pavan Kunapuli [Wed, 13 Feb 2013 11:19:54 +0000]
ARM: tegra: dalmore/pluto: Mask eMMC HS200 mode

Mask eMMC HS200 mode until all the dependent changes are merged.

Bug 1167519

Change-Id: I9d62cd4fbd5c23ac4c8c30c1d3b782c4ea634211
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/200412
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: dalmore: Re-enabling SD,SDIO UHS modes
Pavan Kunapuli [Wed, 13 Feb 2013 09:58:31 +0000]
ARM: tegra: dalmore: Re-enabling SD,SDIO UHS modes

Re-enabling SDR104 and other UHS modes for SD and SDIO cards
on dalmore.

Bug 1189241

Change-Id: If54dde78373e7d10ca526f52c70f644c3c6c7c5a
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/200392
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: dalmore: update emc tables
Ray Poudrier [Tue, 12 Feb 2013 18:26:05 +0000]
ARM: tegra: dalmore: update emc tables

Turn off VTTGEN for low frequencies

Bug 1208724

Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Change-Id: If6bf8d831c78e14449b777d1240497cfc351198b
Reviewed-on: http://git-master/r/200091
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoarm: tegra: roth: move back to step_wise governor
Sang-Hun Lee [Tue, 12 Feb 2013 02:12:48 +0000]
arm: tegra: roth: move back to step_wise governor

pid_thermal_gov is not stable yet. Move back to step_wise governor until
pid_thermal_gov is stabilized

Bug 1233407

Change-Id: I1a5ec9402ce691212ad9d619d7c345579727d402
Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/199806
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoThermal: pid_thermal_gov: change max_err_temp to 9000
Hyungwoo Yang [Mon, 11 Feb 2013 22:31:00 +0000]
Thermal: pid_thermal_gov: change max_err_temp to 9000

Change max_err_temp from 10000 to 90000

Change-Id: I103315d602121cd5bffc5ae6e57d01672acb1035
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/199717
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Edward Riegelsberger <eriegels@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agovideo: tegra: dc: provide debugfs to force hotplug
Jon Mayo [Sun, 10 Feb 2013 05:42:13 +0000]
video: tegra: dc: provide debugfs to force hotplug

debugfs node tegra_hdmi/hotplug controls the override.
0 for normal hpd, 1 for force on, -1 for force off

Change-Id: I41bfbcd26460924ed60bd27de68046ff77b1e869
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/199715
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agovideo: tegra: dc: Power on host1x for CSC, frame end interrupt
Raghavendra VK [Thu, 7 Feb 2013 23:40:16 +0000]
video: tegra: dc: Power on host1x for CSC, frame end interrupt

bug 1233236

Change-Id: I47ffa44e292c65e89914b58d88c52ffdcb35fdbc
Signed-off-by: Raghavendra VK <rvk@nvidia.com>
Reviewed-on: http://git-master/r/198567
(cherry picked from commit 7a7a53e9c832f07b2c784b73e817c31040658827)
Reviewed-on: http://git-master/r/199519
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Jon Mayo <jmayo@nvidia.com>

6 years agoARM: tegra: change thermal parameters
Hyungwoo Yang [Sun, 10 Feb 2013 07:04:10 +0000]
ARM: tegra: change thermal parameters

Changed thermal parameters like below
== CPU-therm ==
tegra-balanced : 84C -> 90C
tegra-heavy : 94C -> 100C
tegra-shutdown : 104C -> 102C

== Tskin ==
tskin trip point : 43C -> 45C
tskin passive delay : 5sec -> 15sec for T114, (5sec -> 30 for T30)
tc1 : 5 -> 10

Change-Id: Icc60773924d848261451f6d35b9a0c8c0ee5054e
Signed-off-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-on: http://git-master/r/199492
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: roth: vdd_core regulator for sdmmc4
Pavan Kunapuli [Mon, 11 Feb 2013 17:14:15 +0000]
ARM: tegra: roth: vdd_core regulator for sdmmc4

Adding vdd_core consumer for sdmmc4 to be used for taking care of
core voltage constraints during frequency tuning.

Bug 1225343

Change-Id: Iecbfe965709a2e859344890e94c94985411b0f4e
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/199488
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: roth: Set SDIO clock to 156MHz
Pavan Kunapuli [Mon, 11 Feb 2013 13:32:38 +0000]
ARM: tegra: roth: Set SDIO clock to 156MHz

Setting SDIO clock to 156MHz in SDR104 mode.

Bug 1167519

Change-Id: I6c9b181f0d23f0acb0520c930dcf3cf3e04f801a
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/199436
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: dalmore/Pluto/roth: set initial mode of all smps to NORMAL
Laxman Dewangan [Mon, 11 Feb 2013 13:17:05 +0000]
ARM: tegra: dalmore/Pluto/roth: set initial mode of all smps to NORMAL

The Palmas PMIC has OTP as 0xC8 on which it sets some of the rail
into PWM mode by default. This is not require to continue rail
configurations in PWM mode once system booted properly. Also keeping
rails in PWM mode consume more power. Hence to reduce the
power on these rails, configure initial mode of these rails to
be NORMAL.

bug 1231293
bug 1231109

Change-Id: I0618cf526085d885287197273d583a03129e2b5f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/199435
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoregulator: palmas: preserve mode configuration across enable/disable
Laxman Dewangan [Mon, 11 Feb 2013 13:13:56 +0000]
regulator: palmas: preserve mode configuration across enable/disable

If regulator rail is configured for a desired mode and
if this rail get disable and again enable then mode
get reset to normal.

Store the desired mode locally and when it enabled, use the stored
preconfigured mode for enabling regulator.

bug 1231293

Change-Id: I396d91609dd91a4f3c682e1279c6f851cda4b94f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/199434
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: roth: limit eMMC clock to 156MHz
Pavan Kunapuli [Fri, 1 Feb 2013 17:11:34 +0000]
ARM: tegra: roth: limit eMMC clock to 156MHz

Limiting eMMC clock to 156MHz in HS200 mode.
Passing nominal core voltage value through platform data to be used
during tuning for HS200 mode.

Bug 1225343

Change-Id: I1ff4065db505a2b3022a1d9fab10a05c5f3a1a31
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/196485
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agommc: tegra: Choose appropriate clk parent
rrajk [Fri, 1 Feb 2013 14:19:00 +0000]
mmc: tegra: Choose appropriate clk parent

choose either pll_c or pll_p as the clk source for sdmmc in order to
set a frequency as close as possible to desired clock rate.

Bug 1167519

Change-Id: Ic37b36864762e5abbcc8076e0ca853a0010d30ae
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/196487
Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com>
Tested-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agovideo: tegra: dc: setup HDMI infoframe and VIC
Jon Mayo [Tue, 12 Feb 2013 02:15:34 +0000]
video: tegra: dc: setup HDMI infoframe and VIC

Changes programming sequence when using the generic infoframe.

bug 1233022

Change-Id: I7108276164a4e97cfe27fcd03c1d03ff3a991909
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/200078
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

6 years agovideo: tegra: dsi: Dont program initialized panels
Rakesh Iyer [Wed, 6 Feb 2013 00:04:03 +0000]
video: tegra: dsi: Dont program initialized panels

Do not program some panels that the bootloader has already initialized.
This avoids periods of blanking during boot.

Bug 1219004

Change-Id: Ie08b20a0892d62dc1b960d37f709eda933e886cc
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/197685
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agocpuquiet: Remove synchronization from runnables_work_func()
Peter Boonstoppel [Thu, 24 Jan 2013 19:04:02 +0000]
cpuquiet: Remove synchronization from runnables_work_func()

runnables_stop() can deadlock when cancel_work_sync() waits for the
work function to end and the work function blocks on the same lock
held by runnables_stop().

Removing the locks from runnables_work_func() fixes this. This should
be safe because runnables_lock protects runnables_state and
runnables_work_func() only reads runnables_state. Also, the functions
that change state to DISABLED do a cancel_work_sync() to guarantee the
work function stopped running.

Bug 1215668

Change-Id: I70617b3b0fc81db8555869e67e3b11652af8d94c
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-on: http://git-master/r/195797
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agommc: tegra: Option to disable all UHS modes
Pavan Kunapuli [Wed, 13 Feb 2013 09:51:50 +0000]
mmc: tegra: Option to disable all UHS modes

Adding option to disable all the UHS modes - SDR12, SDR25, SDR50,
DDR50, SDR104, HS200.

Bug 1189241

Change-Id: I673cf5c819cb4c2ec0525f6e47b493ad1a4b7112
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/199931
Reviewed-by: Rama Kandhala <rkandhala@nvidia.com>

6 years agoARM: Tegra: Dalmore: Adding return statement.
pdabade [Tue, 12 Feb 2013 07:36:02 +0000]
ARM: Tegra: Dalmore: Adding return statement.

Adding return statement to avoid registration of platform device
twice for board E1613.

Change-Id: Ie0d630195f884ee0fc11d21d6aa6a32f2b0d4463
Signed-off-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-on: http://git-master/r/199900
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: enable dma based transfer
Kunal Agrawal [Mon, 11 Feb 2013 08:22:50 +0000]
ARM: tegra: enable dma based transfer

enable dma based transfer for T114 A02 SOC based board

Bug 1233632

Change-Id: I1bfe6ea6e82c535efce9a4bbceb7d7146c290dfc
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/199340
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agopower: max17048: fix charging status
Syed Rafiuddin [Mon, 11 Feb 2013 07:19:50 +0000]
power: max17048: fix charging status

state of charge suddenly jumps to 0% resolving
the same issue.

Bug 1214186

Change-Id: I234a369b86678c8ea177c368ff828930f5ccf73b
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/199267
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: roth: update with correct vreset value
Syed Rafiuddin [Mon, 11 Feb 2013 06:11:03 +0000]
ARM: tegra: roth: update with correct vreset value

use correct vreset value for max17048 fuel-gauge
driver.

Bug 1214186

Change-Id: I2bc69bfbd457152e8888907b17fba5369eb3907a
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/199266
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: Get cluster ID by reading MPIDR
Bo Yan [Sat, 15 Dec 2012 22:53:50 +0000]
ARM: tegra: Get cluster ID by reading MPIDR

This is to avoid MMIO access, thus save a few processor cycles.

Change-Id: Ib4a2aaf8e991885baab51cd74a37387e91cfb5a8
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/171656
(cherry picked from commit 10b7f4ccbf961cbde6b2dec5eb789c1d3beb0f75)
Reviewed-on: http://git-master/r/198890
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra11x: Remove redundant cpu_number calls
Bo Yan [Thu, 7 Feb 2013 00:30:50 +0000]
ARM: tegra11x: Remove redundant cpu_number calls

The "cpu_number" maps cpu number for slow cluster to "4", this can
be reused later, no need to call "cpu_number" every time.

Change-Id: Ib0636b80b587868e23a6b07a5cc9960e13d38353
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/198580
Reviewed-by: Riham Haidar <rhaidar@nvidia.com>
Tested-by: Riham Haidar <rhaidar@nvidia.com>

6 years agoARM: tegra: power-edp table
Diwakar Tundlam [Tue, 22 Jan 2013 20:48:25 +0000]
ARM: tegra: power-edp table

Added code for populating cpu power edp table during init. This is
needed for the AP+DRAM super system EDP client.

Bug 1159974

Change-Id: Ib632cd010627903374fc999f39759f7f54eee136
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
(cherry picked from commit 4ec0d4357df774cd32e18595b4fa5707679bfbd6)
Reviewed-on: http://git-master/r/198397
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoARM: tegra11: add frequency cap clocks
Sivaram Nair [Fri, 1 Feb 2013 09:39:10 +0000]
ARM: tegra11: add frequency cap clocks

Frequency cap clocks for EMC and CBUS are added for AP+DRAM EDP
super-client support.

Bug 1159974

Change-Id: I416cc363025e1ce94e4499300775576eb1cd8178
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
(cherry picked from commit 87d33aa536b156d6c69d1131c95f91ee86725c11)
Reviewed-on: http://git-master/r/198396
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoEDP: fixing bug with priority definitions
Sivaram Nair [Wed, 6 Feb 2013 16:06:32 +0000]
EDP: fixing bug with priority definitions

The min and max priority constants are defined incorrectly (in the wrong
order). This patch corrects it and updates the affected drivers and
platform data.

Change-Id: I94a628c4f4076d1c36dff1692f0427ad1f218fb5
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
(cherry picked from commit 3d2fe9f41fdd54d4c79b7202680e93de8debc8a1)
Reviewed-on: http://git-master/r/198395
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoinput: misc: mpu: Add I2C shutdown support
Erik Lilliebjerg [Wed, 16 Jan 2013 10:08:36 +0000]
input: misc: mpu: Add I2C shutdown support

Bug 1202588

Change-Id: I60f3b4e7f3bd4fdf76ad78e29596155edcf65b2f
Reviewed-on: http://git-master/r/191640
(cherry picked from commit 96b108f17e611f8d9c9aab1fb8e660ea6d559534)
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/197635
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoinput: touch: raydium: power sequence
David Jung [Wed, 6 Feb 2013 22:01:59 +0000]
input: touch: raydium: power sequence

Update Raydium touch driver for new
power sequence.

Bug 1228213

Change-Id: I20fd8fd94af36192120180b0ee91a3021c46a159
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Signed-off-by: David Jung <djung@nvidia.com>
Reviewed-on: http://git-master/r/198124
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoarm:tegra: remove clock enable in board file
Xiaohui Tao [Wed, 6 Feb 2013 00:07:58 +0000]
arm:tegra: remove clock enable in board file

Clock is controlled in raydium driver now. Remove
the clock enable in board file.

Bug 1228213

Change-Id: I6fa83adf3689fa9911544caba54340101af19ed7
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/197647
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: David Jung <djung@nvidia.com>
Tested-by: David Jung <djung@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoinput: touch: raydium: update power sequence
David Jung [Sun, 3 Feb 2013 00:58:14 +0000]
input: touch: raydium: update power sequence

Update power sequence for Raydium touch.

Bug 122813

Change-Id: I12b13e043c5853b1f886f51285525f2165da2ff4
Signed-off-by: David Jung <djung@nvidia.com>
Reviewed-on: http://git-master/r/196763
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>