Bo Yan [Tue, 2 Apr 2013 17:44:52 +0000 (10:44 -0700)]
nohz: stat: Fix CPU iowait time accounting
Since cpustat[CPUTIME_IOWAIT] is never connected to
ts->iowait_sleeptime, never read from cpustat[CPUTIME_IOWAIT] when
reporting stats in /proc/stat.
Note this was rejected by Michal Hocko when it was initially proposed
by Martin Schwidefsky in LKML, so if you want to upstream it, better
find an alternative (either completely disable cpustat[CPUTIME_IOWAIT]
for CONFIG_NO_HZ or somehow connect them to keep them in sync.)
Neil Zhang [Fri, 28 Dec 2012 10:00:26 +0000 (10:00 +0000)]
sched: remove redundant update_runtime notifier
migration_call() will do all the things that update_runtime() does.
So it seems update_runtime() is a redundant notifier, remove it.
Furthermore, there is potential risk that the current code will catch
BUG_ON at line 687 of rt.c when do cpu hotplug while there are realtime
threads running because of enable runtime twice.
Change-Id: I0fdad8d5a1cebb845d3f308b205dbd6517c3e4de Cc: bitbucket@online.de Signed-off-by: Neil Zhang <zhangwm@marvell.com>
Reviewed-on: http://git-master/r/215596 Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Tested-by: Peter Boonstoppel <pboonstoppel@nvidia.com> Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com> Reviewed-by: Paul Walmsley <pwalmsley@nvidia.com>
GVS: Gerrit_Virtual_Submit Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
This patch adds DMA_ATTR_SKIP_CPU_SYNC attribute to the DMA-mapping
subsystem.
This is the counter part of map_page_at() which just maps the
pre-allocate iova to a page. With this attribute, unmap_page() unmap
the link between iova and a page, leaving iova allocated.
Since there is no special characterization data for pll_m_out1,
maximum frequency of pll_m_out1 can be set to the maximum
frequency of the parent i.e pll_m. Maximum frequency for pll_m
is 900Mz.
video: tegra: host: reset enable flag before updating status
- whenever userspace disables 3d scaling via
echo 0 > enable_3d_scaling, it results into calling
podgov_enable which calls update_devfreq to set the
max frequency for a SOC
- update_devfreq ends up calling gov->get_target_freq
whose implementation checks if scaling is enabled or not
- if it is NOT enabled then it returns the max frequency
for that SOC
- however, since enable flag was made = 0 after updating
the dev-freq, it might end up giving away < max freq value
If there is a gap between xfer mode and command register writes, tegra SDMMC
controller can sometimes issue a spurious command before the CMD register is
written. To avoid this, these two registers need to be written together in a
single write operation.
The soctherm_oc pins are generally connected to the device
OC pins and sometimes this pins from device act as interrupt
line also.
In this case, it is require to act the tegra oc pin as SFIO and
route the interrupt call to device's isr.
Adding OC interrupt support so that soctherm can provide the interrupt
number and device can register with this irq number for handling their
interrupts.
Alex Frid [Sat, 30 Mar 2013 00:39:46 +0000 (17:39 -0700)]
ARM: tegra: clock: Make EMC BW request calculation common
Moved EMC bandwidth request calculation from Tegra11 specific code
to commmon tegra emc file.
Change-Id: Ia6f86cb0a4bf99328792baeeae027fa0931f2337 Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/215162
GVS: Gerrit_Virtual_Submit Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Alex Frid [Fri, 29 Mar 2013 23:47:51 +0000 (16:47 -0700)]
ARM: tegra11: clock: Remove ISO BW double scaling
ISO clients bandwidth requests were scaled up twice in a row: first
to meet iso share allocation, second to account for overall memory
bandwidth efficiency. This commit applies each scale separately and
choose maximum between the two.
Change-Id: Ic5e673ac02402736a2a1fa9e4ae990edef9a4bf7 Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/215161
GVS: Gerrit_Virtual_Submit Reviewed-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Change-Id: I0d300c89b87c6760411363c0f85d2cfbab0a719b Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/215131 Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit Reviewed-by: Robert Collins <rcollins@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Reviewed-by: Allen Martin <amartin@nvidia.com>
extcon: max77665: fix the USB host detection interrupt issue
Following are changes:
- Enable host cable interrupt detection.
- interrupt number through platform resource.
- ext connection name through platform data.
- remove unused code for simiplicity.
Return stored requested rate in DFLL get rate operation when target
is below dvco minimum, and output clock skipper is engaged. Skipper
output rates ladder is no longer constant, since dvco minimum rate
calibration was recently introduced. As a result get/set rate calls
in a loop while dvco minimum rate is fluctuating may cause rounding
spiral in either direction. Returning requested rate "as is" allows
to avoid such spiral.
This approach also helps in case when get/set rate loop is executed
across switch between DFLL and PLL. Therefore, now it is possible to
round target rate to the closest skipper output (before rounding up
was used to compensate PLL rounding down)
Kevin Huang [Fri, 25 Jan 2013 19:31:17 +0000 (11:31 -0800)]
video: tegra: dc: add advanced cursor support
Support advanced display cursor for t11x.
Change-Id: If5ef50401b8a2b2fd22500636d07506983aee0b5 Signed-off-by: Michael I Gold <gold@nvidia.com>
Reviewed-on: http://git-master/r/213743 Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com> Reviewed-by: Robert Morell <rmorell@nvidia.com>
Diwakar Tundlam [Tue, 19 Mar 2013 07:23:54 +0000 (00:23 -0700)]
arm: tegra: soctherm: Support configuring OC alarms
Added support to program throttling when OC alarms are triggered.
Support OC1-OC5 with CPU+GPU throttling with preset throttle depths.
Disable suspend cooling device when any OC alarm is configured.
Enhanced regs debug node to display more information about OC alarm
configuration and status.
Enable OC2 and OC4 handling for Dalmore and Pluto.
See Bug 1216535 for testing info to trigger throttling with OC4.
Catalin Marinas [Tue, 19 Feb 2013 16:34:29 +0000 (16:34 +0000)]
arm: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations)
On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down
all use of the old entries. This patch implements the erratum workaround
which consists of:
1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.
2. Send IPI to the CPUs that are running the same mm (and ASID) as the
one being invalidated (or all the online CPUs for global pages).
3. CPU receiving the IPI executes a DMB and CLREX (part of the exception
return code already).
The switch_mm() code includes a DMB operation since the IPI is only sent
to CPUs running the same ASID.
Change-Id: Ideb7f479910f7d4bf25182c84eb5e71691c42a93 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/209830 Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com> Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
In 52af9c6c ("ARM: 6943/1: mm: use TTBR1 instead of reserved context ID")
I updated the ASID rollover code to use only the kernel page tables
whilst updating the ASID.
Unfortunately, the code to restore the user page tables was part of a
later patch which isn't yet in mainline, so this leaves the code
quite broken.
We're also in the process of eliminating __ARCH_WANT_INTERRUPTS_ON_CTXSW
from ARM, so lets revert these until we can properly sort out what we're
doing with the context switching.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
(cherry picked from commit a0a54d37b4b1d1f55d1e81e8ffc223bb85472fa3)
Change-Id: Id3bd7c795bb84269b646e6a1344d1974d85bf094 Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/209825
GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
- Separated iso EMC shared users (display and camera) from other
bandwidth shared users
- Added shared user id flags to EMC shared users that may affect
maximum iso share allocation
- Determined EMC bw requirement as maximum of total bw requested
by all bw users, and iso bw scaled up to guarantee allocated share
Alex Frid [Tue, 26 Mar 2013 06:31:10 +0000 (23:31 -0700)]
ARM: tegra11: clock: Add emc use case table
Added initial table to specify iso bandwidth share dependency on emc
use cases. Just two use cases: display only and display + camera are
identified for now.
Alex Frid [Tue, 26 Mar 2013 05:30:32 +0000 (22:30 -0700)]
ARM: tegra: clock: Support variable iso share with emc usage
Added mechanism to determine maximum allowed iso bandwidth share
depending on emc usage. Each use case is identified by a combination
of shared emc user clocks turned on. The list of use cases and the
respective iso share percentage is to be provided by chip specific
tables.
This commit only added variable iso share APIs and emc shared users
enumeration. No platform specific tables are specified, and APIs are
not used.
Sang-Hun Lee [Thu, 21 Mar 2013 23:44:37 +0000 (16:44 -0700)]
tty: serial: tegra: wait for tasklets during shutdown
Problem description:
- Race between tegra_uart_tasklet_action and tegra_shutdown
- When uart_close calls tegra_shutdown, it removes tty_struct
from tty_port
Fix description:
- Wait for tasklets to complete within tegra_shutdown before
returning to the caller
Kerwin Wan [Thu, 28 Mar 2013 10:17:16 +0000 (18:17 +0800)]
arm: tegra: macallan: set vdd_rtc to 950mV during lp0
When vdd_rtc is set to 900mv, cpu will meet hard hang after
wake up from lp0. Hardware team should do WAT to get the proper margin
for vdd_rtc. Set vdd_rtc to 950mV to avoid this issue now.
Daniel Solomon [Thu, 28 Mar 2013 18:21:16 +0000 (11:21 -0700)]
ARM: tegra: Change NCT72 conversion rate for Dalmore
Reduce conversion rate to 4Hz on Dalmore. It was confirmed that
this is a sufficiently fast to detect crossing of key temperature
points during worst case temperature change rates.
Daniel Solomon [Thu, 28 Mar 2013 18:21:16 +0000 (11:21 -0700)]
ARM: tegra: Change NCT72 conversion rate for Pluto
Reduce conversion rate to 4Hz on Pluto. It was confirmed that
this is a sufficiently fast to detect crossing of key temperature
points during worst case temperature change rates.
joyw [Tue, 19 Mar 2013 10:20:03 +0000 (18:20 +0800)]
xhci: tegra: fix race between remote wake and host wake
A race condition has been discovered during stress testing remote wake
from LP0. Occasionally, remote wake doesn't get served soon enough and
later hub driver tries to do host initiate resume for the port. That
causes the port staying PLS=RESUME with PLC cleared.
This patch fix the race by letting remote wake being completed before
hub driver can resume port.
Sivaram Nair [Thu, 28 Mar 2013 11:09:45 +0000 (13:09 +0200)]
power: max17042: remove temperature from calc
Fuel gauge temperature readings are not working correctly - so remove
this variable from battery depletion calculations and assume room
temperature values.
cpufreq: interactive: Fix race when canceling timer at min freq
When target_freq reaches policy->min the governor calls del_timer()
upon entry to idle. However, it is possible for the timer handler to
still be running at this time, in which case it could rearm itself
such that the timer stays pending.
If we exit from idle before the next timer fires, the timer handler
will find idle_exit_time == 0 and will exit without rearming, from
this point on frequency will be stuck at the current level until we
enter idle again. This sometimes causes frequency to get stuck at
minimum, with cpu load at 100%, causing serious performance problems.
This patch replaces the del_timer() with del_timer_sync().
Jinyoung Park [Thu, 21 Mar 2013 08:48:08 +0000 (17:48 +0900)]
ARM: tegra: thermal: Update due to struct_est_data modification
Updated initialization of skin_data because struct therm_est_data in
include/linux/therm_est.h is modified; adding multiple trip points,
removing get_temp callback in struct therm_est_subdevice, and changing
type of devs from flexible array to pointer.
Jinyoung Park [Thu, 21 Mar 2013 07:44:38 +0000 (16:44 +0900)]
drivers: misc: therm_est: Add multiple trip points support
Replaced cdev_typa and trip_temp to struct thermal_trip_info to support
multiple trip points on therm_est.
And the struct thermal_trip_info has hysteresis for trip temp. So applied
hysteresis to trip temp.
Yunfan Zhang [Tue, 26 Mar 2013 07:52:30 +0000 (15:52 +0800)]
mfd: palmas: fix irq missing issue
Should NOT disable irq during suspend, or there might be pending
interrupt to abort suspend flow and make the secondary irq not be
processing that will cause PMIC can't detect coming interrupts any more
Ajay Gupta [Wed, 20 Mar 2013 23:10:59 +0000 (16:10 -0700)]
usb: xhci: tegra: clock code cleanups
Changes:
- no need to enable ss_src clock
- clean uneeded clk uses such as pllu_clk, utmip_clk, plle_re_vco_clk
- killed clk wash .probe()
- don't enable dev clocks
- change ss_clk to ss_src_clk
- change ss/host_partition_clk to ss/host_clk
Jinyoung Park [Fri, 15 Mar 2013 08:19:44 +0000 (17:19 +0900)]
ARM: tegra114: Change of_platform_populate call order for DT
The of_platform_populate function should be called before
platform_driver_register function call to create a platform_device
for the provided device nodes.
Bo Yan [Wed, 13 Mar 2013 20:55:05 +0000 (13:55 -0700)]
ARM: tegra: Atomics support
This can be used if spin lock type of synchronization is needed
between two different processors. The two different processors
can be ARM7 and Cortex-A9/A15, or any two cores in CPU complex.
If cache and MMU are disabled, the APIs provided by this change
can't be used directly since they require virtual addresses. So
user has to access atomics hardware differently.
Change-Id: I6498415ab206d6032d54125fe680c614c7360dc1 Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/209009 Reviewed-by: Riham Haidar <rhaidar@nvidia.com> Tested-by: Riham Haidar <rhaidar@nvidia.com>
Bo Yan [Mon, 25 Mar 2013 20:27:41 +0000 (13:27 -0700)]
ARM errata: Writing ACTLR.SMP when the L2 cache has been idle for an extended period may not work correctly
This workaround is for ARM errata 799270 which is applicable to
Cortex-A15 up to revision R2P4. The workaround is to read from
a device register and create a data dependency between this read
and the modification of ACTLR.
Change-Id: I26813f17a8a9c6a90446ddeb943ef318e3c69770 Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/212770 Reviewed-by: Bobby Meeker <bmeeker@nvidia.com>
Change-Id: Ib5b0c73f42f73610ec78464dcf789e38d8cab927 Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/212769 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bobby Meeker <bmeeker@nvidia.com>
Bo Yan [Thu, 21 Mar 2013 22:15:32 +0000 (15:15 -0700)]
ARM: tegra114: Implement ARM errata 799270 properly
The ARM errata 799270 requires a data dependency between the returning
device load data and MCR instruction that sets ACTLR.SMP bit. Fix the
current workaround so it confirms to errata document.
Change-Id: Ideeb3dd3d865323d59ae4bc7a2d40889acfe379d Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/211812 Reviewed-by: Bobby Meeker <bmeeker@nvidia.com>
Alex Frid [Sun, 24 Mar 2013 04:18:46 +0000 (21:18 -0700)]
ARM: tegra: clock: Change clock table initialization order
When initializing clocks from table, enable the clock (if requested)
before changing clock parent and/or setting the rate. The latter two
operations would do balanced enable/disable of the target clock anyway.
So, if the clock is to be enabled eventually, better to do it first,
and avoid further unnecessary switching.
Re-factored dvfs rail thermal control so that thermal floors are
applied even when cooling devices are not present or not supported.
Maximum (cold) floor will be set in such case to be safe at any
temperature. Added warnings on different thermal floors and cooling
devices configuration missmatches.
Alex Frid [Sat, 23 Mar 2013 01:30:24 +0000 (18:30 -0700)]
ARM: tegra: dvfs: Don't duplicate cpu rail trip-points
Enforced common set of cpu rail trip-points in dfll and pll modes by
pointing to the same cooling device structure (instead of allocating
two identical structures).
Skipped registration of cpu rail dfll mode trip-points, when they are
the same as in pll mode
Bo Yan [Fri, 22 Mar 2013 21:03:26 +0000 (14:03 -0700)]
nohz: stat: Fix CPU idle time accounting
Since cpustat[CPUTIME_IDLE] is never connected to ts->idle_sleeptime,
never read from cpustat[CPUTIME_IDLE] when reporting stats in
/proc/stat.
Note this was rejected by Michal Hocko when it was initially proposed
by Martin Schwidefsky in LKML, so if you want to upstream it, better
find an alternative (either completely disable cpustat[CPUTIME_IDLE]
for CONFIG_NO_HZ or somehow connect them to keep them in sync.)
Change-Id: I44d153eb2ccc6dbd761dc16e8647455c639a6dae Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/211922
GVS: Gerrit_Virtual_Submit Reviewed-by: Kerwin Wan <kerwinw@nvidia.com> Reviewed-by: Jon Mayo <jmayo@nvidia.com>
During clock initialization verified that children of cbus plls are
either disabled or known cbus clients (the latter will be backed up
on different pll while cbus pll is re-locked).