Laxman Dewangan [Mon, 24 Jan 2011 11:55:10 +0000 (17:25 +0530)]
regulator: Adding gpio switch based regulator
Supporting gpio switch based regulator so that client can
use the power rail through the regulator framework even
if the power rail partially controlled by gpio.
Original-Change-Id: I8cd0141a337d4a38a1b10efb0b5dbb8e3ff98a12
Reviewed-on: http://git-master/r/16727 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Original-Change-Id: I15dedf9ab874037922186b97c5f9daa33dde0b5f
Laxman Dewangan [Fri, 21 Jan 2011 11:09:41 +0000 (16:39 +0530)]
[ARM] tps6591x: Adding regulator and mfd driver
Adding regulator and mfd core driver for TI TPS6591x PMIC family.
Original-Change-Id: I65c0e4758094f211f7e9f0944423bd935c1893c4
Reviewed-on: http://git-master/r/16529 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I2f82c178e3db0998e7c1a5a3b6b8e49832deaf59
Tom Cherry [Wed, 29 Dec 2010 02:30:31 +0000 (18:30 -0800)]
max8907c regulator: fix unit error
The minimum, maximum, and step voltages for SD1 are different on max8907b
and max8907c. This change reads the version register of the device
and uses the proper values, defaulting to the max8907c values, unless
the device is a max8907b.
Colin Cross [Fri, 29 Apr 2011 22:38:33 +0000 (15:38 -0700)]
fs: ext4: Fix computation of inodes per block group
857ac889cce8a486d47874db4d2f9620e7e9e5de (ext4: add interface
to advertise ext4 features in sysfs) added an error check that
exposes a bug in the computation of sbi->s_itb_per_group. If
the number of inodes per group is not a multiple of the number
of inodes per block,
Original-Change-Id: I8c60817dbb6feb43535b567ec7ea5ee0af709c37 Signed-off-by: Colin Cross <ccross@android.com>
(cherry picked from commit 8703a0ccb0135ae0de0d7011f29eeb6dc1caa486)
Todd Poynor [Tue, 15 Feb 2011 19:48:42 +0000 (11:48 -0800)]
ARM: Cortex-A9: Enable dynamic clock gating
Enable dynamic high level clock gating for Cortex-A9 CPUs, as
described in 2.3.3 "Dynamic high level clock gating" of the
Cortex-A9 TRM. This may cut the clock of the integer core,
system control block, and Data Engine in certain conditions.
Add ARM errata 720791 to avoid corrupting the Jazelle
instruction stream on earlier Cortex-A9 revisions.
Lajos Molnar [Fri, 9 Sep 2011 21:44:13 +0000 (16:44 -0500)]
video: fbmon: Add support for CEA pixel ratios.
CEA defines multiple timings with dual timing ratios that cannot
be distinguished from timings parameters. Added 2 new fb flags
to specify 4:3 or 16:9 display ratios.
Also added a flag that denotes CEA formats that require repeating
pixels.
Change-Id: I75d413babdcb4048a0ccce6548ed386ad0e52318 Signed-off-by: Lajos Molnar <molnar@ti.com>
Rebase-Id: Re8a9c83e4707ae0ffabf4f2a539758faeacd6211
JP Abgrall [Sat, 27 Aug 2011 01:39:17 +0000 (18:39 -0700)]
watchdog: tegra_wdt: give time for spinlock lockup detection to work
To allow the spinlock lockup detection to actually trigger after
60 seconds, the tegra_wdt heartbeat needs to be longer than that.
Bumping it to 120sec, as at the 50% marker the watchdog takes an
interrupt.
Colin Cross [Wed, 24 Aug 2011 02:26:33 +0000 (19:26 -0700)]
ARM: tegra: pm: hold cpus unti all have booted when exiting lp2
When exiting lp2, each cpu boots through cpu_resume, which
modifies the last used page table to add a 1-1 mapping in
order to turn on the mmu. The first cpu to boot triggers
booting the second cpu, and if allowed to continue immediately
may start executing a userspace task that is using the same
page tables as the second cpu is modifying during its boot
process. Hold each cpu in a loop until all cpus have
finished booting to ensure page tables are back to their
original state. Each cpu triggers a global tlb flush
after it restores the page table, so all cpus will see the
original values before they exit idle.
Change-Id: Iad91ae57e2abbbec3d6d491460c3e19411b519c0 Signed-off-by: Colin Cross <ccross@android.com>
Rebase-Id: R110a4b1f28846af97edd39bb382e1e09c3f92330
Colin Cross [Wed, 24 Aug 2011 00:43:54 +0000 (17:43 -0700)]
ARM: tegra: sleep: flush tlbs when exiting wfi
tegra_sleep_wfi disables coherency to prepare for possibly
resetting the cpu. If an interrupt is received, it exits
wfi and re-enables coherency, but it was not flushing the
tlbs or the branch predictor array, which could have been
updated by broadcast tlb operations that were ignored.
Flush the tlbs and branch predictor array when exiting.
Change-Id: If2c6ca3f923baf2f883f461a2a90f08833c7e191 Signed-off-by: Colin Cross <ccross@android.com>
Rebase-Id: Re46c9045a33ad78789e7dee2788b470fd1071c83
The prefetcher fetches a total of 128 bytes, and then responding to
sequential reads with this prefetched data. To avoid coherency issues,
it discards the prefetched data if a non sequential read occurs.
Allocate dtd with 128 bytes boundary to make 2 consecutive dtd 128 bytes
apart.
Submitted on behalf of Jay Cheng <jacheng@nvidia.com>
Change-Id: I2adc02c2ac7901d0617b487cb498a34ec7a63e18 Signed-off-by: James Wylder <james.wylder@motorola.com>
Rebase-Id: R5f9b91ece4b041d15bed9c1239bff073af18dcb8
Michael I. Gold [Thu, 31 Mar 2011 02:07:07 +0000 (19:07 -0700)]
video: tegra: add support for tiled surfaces
Change-Id: I82497fc756552740836eaa2f608fecaea409cfeb Signed-off-by: Michael I. Gold <gold@nvidia.com>
Rebase-Id: R546a39a04712c0dbb6fcc51f60fb9ccb20fc46d5
Nathan Connell [Mon, 2 May 2011 19:32:36 +0000 (14:32 -0500)]
usb: ehci: tegra: Correctly handle GetPortStatus during Resume
Multiple GetPortStatus requests can be made while the
USB bus is resuming. All requests must be handled
properly to prevent incorrect disconnect detection
during Resume and improper indentification of
Resume signaling as a remote wakeup event.
James Wylder [Fri, 11 Mar 2011 22:39:43 +0000 (16:39 -0600)]
usb: host: tegra: update memory frequency requests to 150 MHz
With the previous change in memory frequency (200 MHz
to 150 MHz) requests of 200 MHz will round up to full
speed. This negatively impacts current drain.
Change-Id: Ib67d8eaff57836a2f1756d84cce6533539911178 Signed-off-by: James Wylder <james.wylder@motorola.com>
Rebase-Id: R4c915ea04c3319ddd1962b24199d2e50e18fae06
James Wylder [Fri, 11 Mar 2011 22:39:43 +0000 (16:39 -0600)]
usb: gadget: tegra: update memory frequency requests to 150 MHz
With the previous change in memory frequency (200 MHz
to 150 MHz) requests of 200 MHz will round up to full
speed. This negatively impacts current drain.
Change-Id: Iefdb3a50aff338b44daa8311218400e4b4586152 Signed-off-by: James Wylder <james.wylder@motorola.com>
Rebase-Id: R39ff6f546ba05e471bb1e95cca6a78e35492099a
Colin Cross [Fri, 6 May 2011 04:48:54 +0000 (21:48 -0700)]
mmc: host: sdhci-tegra: Add set_clock op
Add a set_clock op to sdhci-tegra to allow the clock to be
disabled. Also add suspend and resume ops to disable
the clock before suspend, and enable it during resume.
Change-Id: I239cb769b54c83a1bd4a80b73e1c4845ce2d165d Signed-off-by: Colin Cross <ccross@android.com>
Rebase-Id: Rbf12d34ca4f97a02931672f600a03cd92008d556
usb: gadget: fsl_udc: Unlock the spinlock before calling clk_enable
On suspend, dr_controller_stop disable interrupts and on resume, interrupts
are disabled until dr_controller_run is called, so it is safe to call
fsl_udc_clk_suspend/resume with interrupts and the spinlock unlocked.
usb: gadget: Enable/disable the gadget device on vbus_session calls
If we use an OTG driver, the driver will detect VBUS changes and notify
the gadget driver through vbus_session. Enable/disable the gadget driver
in vbus session so that there is no need to check the OTG state on every
interrupt.
ARM: tegra: Verify PHY clock valid before clearing USB_SUSP_CLR bit
When enabling the external ULPI PHY, the clock from the PHY must be
valid before the USB_SUSP_CLR bit is cleared in the USB2 controller
interface register. If the clock from the PHY is not valid when
this bit is cleared, the AHB clock to the host controller may be
stopped, preventing any access to the host controller.
Replace hard-coded delay with poll for USB_PHY_CLK_VALID bit. Signed-off-by: Nathan Connell <w14185@motorola.com>
Change-Id: I24fa7575641f20ffdba7737776a81ba453f54395 Signed-off-by: Nathan Connell <w14185@motorola.com>
Rebase-Id: R819c1a8f769f72aad2868ab78f4d31bd3b97c750
Peter Zu [Thu, 7 Apr 2011 04:42:33 +0000 (21:42 -0700)]
video: tegra: dc: hdcp: handle the case of DEVICE_COUNT = 0 properly
When HDCP repeater has no device attached, DEVICE_COUNT reports back as 0.
HDCP driver should handle this case as a good case and continue downstream
authentication, other than fail it.
Erik Gilling [Wed, 13 Apr 2011 15:03:41 +0000 (08:03 -0700)]
video: tegra: fix unplug/suspend timeout in nvhdcp
If HDCP was turned off (either by unplug or suspend) the work funciton
would wait the full timeout 5 * l.75s before exiting. This
causes suspend to timeout and crash.
Change-Id: I8eb185452ad09e34f4573874e9766c0e1cec15de Signed-off-by: Erik Gilling <konkers@android.com>
Rebase-Id: R1f5d558bc5ddc0a34e3b6db80d783a8dd791b8b2
Colin Cross [Thu, 7 Apr 2011 21:47:45 +0000 (14:47 -0700)]
[ARM] mm: add memory type for inner-writeback
For streaming-style operations (e.g., software rendering of graphics
surfaces shared with non-coherent DMA devices), the cost of performing
L2 cache maintenance can exceed the benefit of having the larger cache
(this is particularly true for OUTER_CACHE configurations like the ARM
PL2x0).
This change uses the currently-unused mapping 5 (TEX[0]=1, C=0, B=1)
in the tex remapping tables as an inner-writeback-write-allocate, outer
non-cacheable memory type, so that this mapping will be available to
clients which will benefit from the reduced L2 maintenance.
Change-Id: Iaec3314a304eab2215100d991b1e880b676ac906 Signed-off-by: Gary King <gking@nvidia.com>
Conflicts:
Code Review / linux-2.6.git / log