6 years agoThermal: Remove tc1/tc2 in generic thermal layer.
Zhang Rui [Wed, 27 Jun 2012 01:51:12 +0000]
Thermal: Remove tc1/tc2 in generic thermal layer.

Remove tc1/tc2 in generic thermal layer.
.get_trend() callback starts to take effect from this patch.

bug 1059470

Change-Id: I69ea5306c9e76b0dae8eb6ad4b89335068e78f9b
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Valentin, Eduardo <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159966
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Introduce .get_trend() callback.
Zhang Rui [Wed, 27 Jun 2012 01:54:33 +0000]
Thermal: Introduce .get_trend() callback.

According to ACPI spec, tc1 and tc2 are used by OSPM
to anticipate the temperature trends.
We introduced the same concept to the generic thermal layer
for passive cooling, but now it seems that these values
are hard to be used on other platforms.

So We introduce .get_trend() as a more general solution.

For the platform thermal drivers that have their own way to
anticipate the temperature trends, they should provide
their own .get_trend() callback.
Or else, we will calculate the temperature trends by simply
comparing the current temperature and the cached previous
temperature reading.

bug 1059470

Change-Id: I85ca51d87ae8fde8429a83399a81979a41913218
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Valentin, Eduardo <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159965
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoarm: tegra: baseband: enable autosuspend for Icera PID 0x310
Neil Patel [Tue, 30 Oct 2012 18:54:34 +0000]
arm: tegra: baseband: enable autosuspend for Icera PID 0x310

Enable autosuspend for all Icera modems with product ID 0x310.

Bug 1167714

Change-Id: Ie94600e80be2fa305383cf36d5d77d92f8513149
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/159947
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: baseband: enable oob remote wake and reset detection
Neil Patel [Thu, 1 Nov 2012 14:43:02 +0000]
arm: tegra: baseband: enable oob remote wake and reset detection

Out of band remote wakeup and reset detection for Icera modems was
disabled during T114 bringup and needs to be re-enabled.

Bug 1169035

Change-Id: I0c720f18bcf91dab01051d6e15a866ae2c8053c7
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/160601
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>

6 years agoARM: tegra11x: make SMP disabled compiles
Jong Kim [Fri, 19 Oct 2012 23:32:25 +0000]
ARM: tegra11x: make SMP disabled compiles

Make kernel compiles for disabled CONFIG_SMP.

bug 1057875

Change-Id: Ie7161a86279d31245290f4e74027c1cc5e646790
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/160361
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

6 years agoarm: tegra: isomgr: fix incorrect comparison in isomgr.
Krishna Reddy [Wed, 31 Oct 2012 00:14:42 +0000]
arm: tegra: isomgr: fix incorrect comparison in isomgr.

fix incorrect bandwidth available check comparison during reserve.
check for validity of clients.
support specifying the clients based on soc.
fix format issues.
add missing sysfs nodes for isomgr.

Change-Id: Iad7a95b923397e9e8210c9fc42981095f3045bcd
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/160056
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>

6 years agoARM: tegra11: dvfs: Update DFLL range configuration
Alex Frid [Sat, 27 Oct 2012 02:01:57 +0000]
ARM: tegra11: dvfs: Update DFLL range configuration

Replaced boolean DFLL usage configuration option with integer
TEGRA_USE_DFLL_RANGE option that specifies default range for
DFLL to be used as CPU clock source:
"0" - DFLL is not used,
"1" - DFLL is used as a source for all CPU rates
"2" - DFLL is used only for high rates above crossover with
PLL dvfs curve

Made sure that valid cvb tables for DFLL and PLL modes provide
crossover between DFLL and PLL dvfs voltage ranges.

Change-Id: Idf50ee15b7a30c10a15360f7be2079586c0118f4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/159728
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: Kconfig: enable soctherm by default
Joshua Primero [Sat, 20 Oct 2012 22:50:04 +0000]
ARM: tegra: Kconfig: enable soctherm by default

Soctherm is ready to be enabled.

bug 1169070

Change-Id: I51236e333267c88b07e3883813200007059ebb8f
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/146157
(cherry picked from commit e49070901be252c87811eaadf75668337433206a)
Reviewed-on: http://git-master/r/159500
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoARM: tegra11: secure os: disable normal os timer
Hyung Taek Ryoo [Fri, 26 Oct 2012 14:31:12 +0000]
ARM: tegra11: secure os: disable normal os timer

The timer is handled by the secure os for T11x.
Hence disable timer in normal os when secure os is enabled.

Change-Id: I64639e1f69bca39fdc6e149000f8de8c821ab485
Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-on: http://git-master/r/159123
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agovideo: tegra: host: use platform bus/driver/device
Mayuresh Kulkarni [Fri, 26 Oct 2012 13:17:24 +0000]
video: tegra: host: use platform bus/driver/device

- this commit replaces the custom nvhost bus/driver/device
with platform bus/driver/device
- this is in preparation to add DT support
- following is the list of notable changes done:

1. chip_ops: The per SoC differences is encapsulated by chip_ops structure.
With nvhost_bus:
- It is hidden in nvhost_bus and exposed APIs to rest of the code.
These APIs land up in correct implementation for current SoC.
With platform_bus:
- I had to make this global and adjust the API accordingly.

2. nvhost_device
With nvhost_bus:
- The struct nvhost_device encapsulates both Linux device driver parts
as well as tegra specific parts.
With platform_bus:
- I had to move the current nvhost_device as a platform_data
for each platform_device. For this I renamed the struct nvhost_device
to struct nvhost_device_data.
- Also, since nvhost_driver is gone, I had to move all the
function pointers in it to struct nvhost_device_data.

3. Device specific private data: Host1x master device has its own
static data (called nvhost_master) which stores the per SoC
sync-point, IRQ info etc.
With nvhost_bus:
- This was stored as device specific platform_data.
With platform_bus:
- The device specific platform_data is now struct nvhost_device_data
(as mentioned above).
- I need to keep it common for all the devices whose code is
part of host1x directory, so that other parts of code that need per-device
info have a unique interface of platform_get_drvdata.
- As a result, I had to add a void * field in struct nvhost_device_data
which now holds per-device specific data and expose APIs to get/set this data.
- As of now, only host1x master parent device code uses this.

4. Per SoC device names:
With nvhost_bus:
- Per SoC device name is SAME for all the SoCs.
- The correct driver get linked to this device via the concept of id_table.
This id_table allows us to connect multiple devices to single driver code
and pass appropriate function pointer specific to SoC (you can check gr3d.c for details).
With platform_bus:
- The id_table usage of platform_bus is different from above.
- To adhere to its need, I had to append the per-SoC device name
with a version field (so gr3d for t20 became gr3d01, for t30 became gr3d02 etc).
- I adjusted the correct names in _probe of such devices.
Also, I adjusted the node names exposed to user space (/dev/host-gr3d etc)
to be consistent across SoCs.
- But this fails for the sysfs entries created by device registration code
of Linux, since during this time the _probe is not called.
So, device name is still appended with version field.

5. Per SoC device registration function: tegraXXX_register_host1x_devices
is the per SoC specific APIs which is called by board-file to register
the host1x and client devices. Host1x has strict requirements for the
parent->child relations i.e. any client of host1x device should have the
parent set properly BEFORE device registration.
With nvhost_bus:
- Setting of parent was taken care by nvhost_device_register call and other helpers.
With platform_bus:
- It is not possible to change parent till _probe of client device returns
(meaning not much of control in our hand). The device driver core,
takes a mutex lock of parent BEFORE calling _probe to avoid changing parent during _probe.
- So, to set correct parent, I changed the return type of
tegraXXX_register_host1x_devices to return pointer to master host1x parent device.

6. platform_get_drvdata calls:
With nvhost_bus:
- Only host1x master parent calls this.
With platform_bus:
- Almost all the common code ends up calling this.
Fortunately, we had designed the APIs such that they take nvhost_device * as argument.
So changing them to platform_device * is in a way easy.

7. Device list: The debug-fs dump code & module-reg-read-write
functionality rely on having a list of host1x devices registered currently.
With nvhost_bus:
- This is readily available since struct bus_type of Linux holds this list.
Moreover, it provides an iterators to access this list.
With platform_bus:
- Since it holds large number of devices in system, it is inefficient
to use the above iterators. Also, it is difficult to have a common matching
criteria for all the devices who have different platform_data.
- As a result, I had to add a simple list using Linux kernel's list implementation.
It holds the list of devices which have their code within host1x directory
and actually use channels (remember tegra-dc and nvavp are outside
host1x code && do not use physical channels they only need sync-point
and host1x hardware alive when they are alive).
I also had to provide 2 iterators one which is used for
module-reg-read-write and other for debug-fs dump.

8. I changed how tegra-dc and nvavp called the host1x externally exposed APIs
(such APIs end with _ext). In current code, they know little too much of
host1x code internals. I now changed to make them independent of host1x internal
implementation and structure know-how. They now simply send their own
platform_device * to the external visible APIs and these APIs
ensures that the call ends up in correct function call.

bug 1041377

Change-Id: I9cd4d506e6f3bde805923ce7c7bbbd37c9ec13c4
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/131403
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: pluto: add ina219 power monitor devices
Mallikarjun Kasoju [Wed, 17 Oct 2012 15:10:57 +0000]
ARM: tegra: pluto: add ina219 power monitor devices

Bug 1156147

Change-Id: I9e4f01efb6e102c0637b662f6789439efca6a0c9
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/160402
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoasoc: tegra: cs42173: modify DAPM route table
Dara Ramesh [Wed, 31 Oct 2012 17:40:24 +0000]
asoc: tegra: cs42173: modify DAPM route table

a) register DAPM route table with snd_soc_card structure and
remove the open-coded DAPM add route calls.

b) set card.fully_routed flag to request the ASoC core calculated
unused codec pins, and call snd_soc_dapm_nc_pin() for them.

Bug 1158489
Bug 1052069
Bug 1054060

Change-Id: I43e9f4dab812904e314d460edec0a2bd903f09c6
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/160252
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

6 years agoTegra11x: defconfig: Add necessary camera devices
Rahool Paliwal [Wed, 31 Oct 2012 08:39:32 +0000]
Tegra11x: defconfig: Add necessary camera devices

This adds MAX776 flash device and AS364X torch device

Bug 1165148

Change-Id: Ied777a08e8f4ba01f6a073024a0e1edc2514aeea
Signed-off-by: Rahool Paliwal <rpaliwal@nvidia.com>
Reviewed-on: http://git-master/r/160141
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agoarm: tegra: USB: Disable STREAM_DISABLE
Petlozu Pravareshwar [Tue, 30 Oct 2012 11:50:33 +0000]
arm: tegra: USB: Disable STREAM_DISABLE

Setting STREAM_DISABLE = 0 for all USB controllers.

Bug 1166838

Change-Id: I6f540aac2175a920d5bd549e5545122b1c886a80
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/159864
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agocpuidle: Export target residency
Antti P Miettinen [Mon, 29 Oct 2012 12:37:31 +0000]
cpuidle: Export target residency

Make cpuidle state target residency visible via sysfs.

Change-Id: Ie039bcfa943bdb4aca6cb30ac23356e4b48aa32b
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/159543
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoARM: tegra11:clock:update UTMIPLL register program
Rakesh Bodla [Wed, 31 Oct 2012 05:17:59 +0000]
ARM: tegra11:clock:update UTMIPLL register program

Update the UTMIPLL register programming sequence
to let hardware control UTMIPLL.

Bug 1057339

Change-Id: I38cca059b3f263de8382f56a5f2a0247e0df8743
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/159449
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agocrypto: tegra-se: add chained scatter list support
venkatajagadish [Fri, 26 Oct 2012 09:07:23 +0000]
crypto: tegra-se: add chained scatter list support

This change adds chained scatter list traversing support
to S.E. Driver.

Bug 1010604

Change-Id: If4073b7cf9c8ac901b8d0bd21ddc035e1e6b7ffd
Signed-off-by: venkatajagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/147890
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoarm: usb: phy: HSIC 2LS WAR using PMC resume
Vinod Atyam [Mon, 22 Oct 2012 10:23:43 +0000]
arm: usb: phy: HSIC 2LS WAR using PMC resume

Enable the 2ls war support during
AP resume and remote wakeup resume.

Bug 1028940

Change-Id: I09dc3c71b95bd83b8612624aa40a94b89d98dda7
Signed-off-by: Vinod Atyam <vatyam@nvidia.com>
Reviewed-on: http://git-master/r/146340
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoarm: tegra: pluto: enable powergate for ve
Daniel Solomon [Thu, 1 Nov 2012 00:15:22 +0000]
arm: tegra: pluto: enable powergate for ve

Enable powergate for VE.

Bug 1059495

Reviewed-on: http://git-master/r/142731
(cherry picked from commit f0706776cd7bd90eaaca3823eeb55256fac013c5)

Change-Id: I66c4c3a6a9a18ba175cc61269f3f4bd95af1ad17
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/145997
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoarm: tegra: rename pinmux device/driver name
Pritesh Raithatha [Fri, 19 Oct 2012 09:30:47 +0000]
arm: tegra: rename pinmux device/driver name

rename all tegra pinmux device/driver with similar names.
platform device name has size limit of 20 char.

Bug 1003210

Change-Id: Idd162fad662a364812010630856c1657b9af9c35
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/145910
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agoarm: tegra: emc: Fix the freq to bw conversion API's.
Krishna Reddy [Tue, 30 Oct 2012 23:44:11 +0000]
arm: tegra: emc: Fix the freq to bw conversion API's.

Fix the emc freq to bw conversion and vice versa API's to
return real emc freq and bandwidth numbers based on SOC.

Bug 1167105

Change-Id: I6f244d0f6626e59ed5a3707a2a564ee711a45c43
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/160043
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra: soctherm: Update bind function
Joshua Primero [Tue, 23 Oct 2012 01:11:34 +0000]
ARM: tegra: soctherm: Update bind function

Updated bind function to reflect new Thermal API.

bug 1059470

Change-Id: I77bff7ac080d663018a938ccd2fa887884ab84a5
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/159964
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agodrivers: nct: tsensor: Update bind function
Joshua Primero [Tue, 23 Oct 2012 01:09:57 +0000]
drivers: nct: tsensor: Update bind function

Update the bind function in the tsensor and nct driver to
reflect the new Thermal API.

bug 1059470

Change-Id: I527383d426ff1f70fe531a02d600735cbedea7b8
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/159963
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoThermal: set upper and lower limits
Zhang Rui [Tue, 26 Jun 2012 08:35:57 +0000]
Thermal: set upper and lower limits

set upper and lower limits when binding
a thermal cooling device to a thermal zone device.

bug 1059470

Change-Id: I90f4c79fa2af79896cb93a528fb4e4263f02587c
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159962
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Introduce cooling states range support
Zhang Rui [Tue, 26 Jun 2012 08:27:22 +0000]
Thermal: Introduce cooling states range support

As the active cooling devices can have multiple cooling states,
we may want only several cooling states for a certain trip point,
and other cooling states for other active trip points.

To do this, we should be able to describe the cooling device
behavior for a certain trip point, rather than for the entire thermal zone.
And when updating thermal zone, we need to check the upper and lower limit
to make sure the cooling device is set to the proper cooling state.

Note that this patch will not bring any different behavior as
upper limit is set to max_state and lower limit is set to 0
in this patch, for now.

Next patch will set these to real values.

bug 1059470

Change-Id: I2fcb4e01849f18d471e1481ffc9940162e60a3ec
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159961
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Introduce multiple cooling states support
Zhang Rui [Tue, 26 Jun 2012 08:26:40 +0000]
Thermal: Introduce multiple cooling states support

This is because general active cooling devices, like fans,
may have multiple speeds, which can be mapped to different cooling states.

bug 1059470

Change-Id: Ibebf71a0faca1980269db48a40dc8bb7db0d2357
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Valentin, Eduardo <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159960
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Documentation update
Zhang Rui [Wed, 25 Jul 2012 02:11:00 +0000]
Thermal: Documentation update

With commit 6503e5df08008b9a47022b5e9ebba658c8fa69af,
the value of /sys/class/thermal/thermal_zoneX/mode has been changed
from user/kernel to enabled/disabled.
Update the documentation so that users won't be confused.

bug 1059470

Change-Id: I40e33813ad4ebb4b033c2064664b8b1fbeed31ea
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-on: http://git-master/r/159959
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Add Hysteresis attributes
Durgadoss R [Wed, 25 Jul 2012 02:10:59 +0000]
Thermal: Add Hysteresis attributes

The Linux Thermal Framework does not support hysteresis
attributes. Most thermal sensors, today, have a
hysteresis value associated with trip points.

This patch adds hysteresis attributes on a per-trip-point
basis, to the Thermal Framework. These attributes are
optionally writable.

bug 1059470

Change-Id: I701a72ee65048ffcdbcfa8ff88dccc170cd3715e
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-on: http://git-master/r/159958
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agovideo: tegra: dc: Move PRISM update to V_PULSE2.
Kevin Huang [Tue, 16 Oct 2012 04:50:40 +0000]
video: tegra: dc: Move PRISM update to V_PULSE2.

Add support to update PRISM at V_PULSE2_INT. Use V_PULSE2 for PRISM
if the chip supports.

Bug 1156207

Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Change-Id: I5b908b206d647c3efce7037578b0ed86e9bb2d22
Reviewed-on: http://git-master/r/159945
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: clock: Don't convert EMC shared user requests
Alex Frid [Tue, 30 Oct 2012 03:43:00 +0000]
ARM: tegra11: clock: Don't convert EMC shared user requests

Removed conversion of EMC shared bus users bandwidth requests to EMC
bus width. Let the client drivers do it.

Bug 1167105

Change-Id: I5b7aae3d87f76171bc67cfb9cb6d8480e2122f75
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/159732
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: fb: Update fix line_length
Shashank Sharma [Thu, 25 Oct 2012 09:41:39 +0000]
arm: tegra: fb: Update fix line_length

Update framebuffer's fix line_length parameter when changing
video mode dynamically.The new line_length should be according
to new x resolution. On addition, check the return value from
dc driver while setting a mode.

Bug 1163682
Bug 1056767
Bug 1056782
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Change-Id: Ib0ab48474f0af3235556a7f7f0d8354af3b50994
Reviewed-on: http://git-master/r/147511
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: Enterprise: Add power regulator for atmel.
Xiaohui Tao [Thu, 25 Oct 2012 01:13:52 +0000]
ARM: tegra: Enterprise: Add power regulator for atmel.

Add power regulator support for atmel

Bug 1063749

Change-Id: I0793f7f497ff75a538d1f6b2d8e31b059b5e326b
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/147120
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: Cardhu: Add power regulator for atmel.
Xiaohui Tao [Thu, 25 Oct 2012 01:12:57 +0000]
ARM: tegra: Cardhu:  Add power regulator for atmel.

Add power regulator support for atmel

Bug 1063749

Change-Id: I009cf857628486ba4d8bb2ba2c23d9aae12d3a07
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/147119
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoinput:atmel_mxt - add regulator support
Xiaohui Tao [Tue, 23 Oct 2012 19:24:13 +0000]
input:atmel_mxt - add regulator support

Bug 1063749

Change-Id: I47f9f312fbbda99e0746f5017d30d91a38037e35
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/147118
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>

6 years agoARM: tegra: rename fuse driver
Preetham Chandru R [Tue, 23 Oct 2012 10:10:20 +0000]
ARM: tegra: rename fuse driver

The fuse driver registers parameters and thus
create a /sys/module/fuse directory which collides
with the fuse filesystem driver.

Rename fuse.c to tegra_fuse.c to fix this.

Bug 1058350

Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/#change,143206
(cherry picked from commit b0935d3914c6a01349eaacce08d28620e7b78f6f)
Change-Id: I9a64479555b7e9d6ea184101923eba3d8e1d5bdf
Reviewed-on: http://git-master/r/146886
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: pluto/dalmore: Enable PMU power off
Mallikarjun Kasoju [Tue, 30 Oct 2012 15:38:12 +0000]
ARM: tegra: pluto/dalmore: Enable PMU power off

Enable power off functionality for pluto and dalmore
Bug 1051970

Change-Id: If8956801fa0eea56a3716686cd6dda3b86f63989
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/134305
(cherry picked from commit 0963e62f86ab2c08c0e02dc28087c0460ebada2a)

Conflicts:

arch/arm/mach-tegra/board-dalmore-power.c
arch/arm/mach-tegra/board-pluto-power.c

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I93591db9b8fc636456c56a280b03ba8a3722b44e
Reviewed-on: http://git-master/r/159899
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agocrypto: tegra-se: Fix t114 SE context save failure
Mallikarjun Kasoju [Tue, 30 Oct 2012 14:16:45 +0000]
crypto: tegra-se: Fix t114 SE context save failure

t114 has sticky bits for RSA key slots which is not
there in t30. Context save buffer offsets are
adjusted appropriately for this.

Change-Id: Ifd4e59772a869358d8dd12262e882fa63c53f054
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/159890
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoRevert "HACK: arm: mm: Disable Freeing init memory."
Deepak Nibade [Tue, 30 Oct 2012 05:46:46 +0000]
Revert "HACK: arm: mm: Disable Freeing init memory."

This hack was introduced in Main to enable booting of
dalmore/pluto.
Revert this hack because it is no longer needed.

Bug 1166538

This reverts commit 1fba4c801566639db74d117f1233bb790d1748aa.

Change-Id: I950f056d254e32f8e49967c015bf3ecea44c19db
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/159867
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: Dalmore/pluto: Set drive strengths
Pavan Kunapuli [Fri, 12 Oct 2012 10:26:30 +0000]
ARM: tegra: Dalmore/pluto: Set drive strengths

Setting the drive type for GMA pad groups.
Changed the drive strength settings of GMA
pad group as per characterization team
recommendations.

Bug 1156152

Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/144031
(Cherry picked from commit 0eca234cfc04bfcd6e5f6a8c1a035319186305cd)

Change-Id: I6df5b3e7bc02b1d39079726d5477b5b2dfbc70d5
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/159819
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra: powergate update
Bitan Biswas [Tue, 16 Oct 2012 14:04:48 +0000]
ARM: tegra: powergate update

Tegra11x partition powergate and unpowergate is separated
from older chip implementation

Change-Id: I6669eac81f8c2964139637b5147c07005b594717
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/159760
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoinput: misc: cm3218: suspend/resume state maintenance
Sri Krishna chowdary [Mon, 29 Oct 2012 08:53:48 +0000]
input: misc: cm3218: suspend/resume state maintenance

Need to store the state of cm3218 before suspend so
that when resumed the state can be restored.

Bug 1030776

Change-Id: I02fe19630a938aabbd0185d29b073cd000ae1331
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159747
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agopluto: enable PRISM for 1080p Sharp Panel
Mitch Luban [Thu, 18 Oct 2012 05:15:41 +0000]
pluto: enable PRISM for 1080p Sharp Panel

This change enables PRISM on 1080p Sharp panel.

Change-Id: I9f1a9bd410164a307b8de3e5855ac96b601bd6e5
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/159582
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agommc: tegra: Set broken preset values quirk
Pavan Kunapuli [Tue, 25 Sep 2012 17:01:43 +0000]
mmc: tegra: Set broken preset values quirk

Do not enable preset values for tegra sdmmc
controller as fixed clock divisor values need
to be used for ddr and sdr50 modes.

Bug 1157930

Change-Id: I8c453cc4fe48029dfe7ae5b1c42c6bf3f8dac9dc
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/159562
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agommc: sdhci: Enable preset for valid preset values
Pavan Kunapuli [Mon, 29 Oct 2012 13:45:16 +0000]
mmc: sdhci: Enable preset for valid preset values

Do not enable preset if the preset values in the
host controller register are invalid.

Bug 1157930

Change-Id: I783543e28df516b60c12c1ff721d7c42159369fd
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/159561
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agotty: serial: tegra: check function's return value
Sri Krishna chowdary [Mon, 29 Oct 2012 13:02:30 +0000]
tty: serial: tegra: check function's return value

Platform_get_irq returns int. So, the check should
be (int)irq < 0 not irq < 0 which has no effect as irq
is unsigned.

Bug 1046331

Change-Id: I6599f34ef42bcd286908b4bdd029639231fb9a3d
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159553
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agousb: gadget: tegra: free resources in case of error
Sri Krishna chowdary [Mon, 29 Oct 2012 12:54:52 +0000]
usb: gadget: tegra: free resources in case of error

Bug 1046331

Change-Id: Ic4f4665c77f2dc3b4c5aeb0e9be5b9e9173fddb0
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159552
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agospi: tegra: remove unsigned int comparision to 0 error
Sri Krishna chowdary [Mon, 29 Oct 2012 12:41:27 +0000]
spi: tegra: remove unsigned int comparision to 0 error

Bug 1046331

Change-Id: Id0a2219671ed05de7226128da31302867a2633b1
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159546
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agospi: tegra11: add NULL check
Sri Krishna chowdary [Mon, 29 Oct 2012 12:36:12 +0000]
spi: tegra11: add NULL check

fix coverity issue.
Add Null check before dereferencing t->tx_buf and tspi->cur.

Bug 1046331

Change-Id: I2ff53b1945b4ee9a0d87e23816df7f2a3f1464fe
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159542
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agohwmon: tegra: tsensor: coverity warning fix
Bitan Biswas [Mon, 29 Oct 2012 12:28:01 +0000]
hwmon: tegra: tsensor: coverity warning fix

bug 1046331

Change-Id: I1be17d9343b004a6cb0a81c13fd0f322ada9d109
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/159541
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agomisc: tegra-cryptodev: fix resource leak
Sri Krishna chowdary [Mon, 29 Oct 2012 11:53:27 +0000]
misc: tegra-cryptodev: fix resource leak

Memory allocated from ablkcipher_request_alloc is
not deallocated before function returns when
crypt_req->keylen is invalid.

Bug 1046331

Change-Id: I9d74159c0653b5b5d08e3d0d00b1919590d7599f
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159533
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoiommu/tegra: smmu: remove NULL check
Sri Krishna chowdary [Mon, 29 Oct 2012 10:59:47 +0000]
iommu/tegra: smmu: remove NULL check

smmu->regs cant be NULL if smmu is not NULL.

Bug 1046331

Change-Id: Ic37f0075842583ad957f196338c2b9de66fa4ee1
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159519
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: soctherm: set initial soctherm values
Joshua Primero [Sat, 20 Oct 2012 19:54:16 +0000]
ARM: tegra: soctherm: set initial soctherm values

Set initial soctherm values. This is in preparation for enabling
the hardware.

Change-Id: Id7ad43b39ede0177a3916b9210b7a2e4fbd6eaa6
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/146156
(cherry picked from commit d7cd52519608dd2273105be03a2aab4967f5a3bb)
Reviewed-on: http://git-master/r/159499
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agocrypto: tegra-se: add NULL check
Sri Krishna chowdary [Mon, 29 Oct 2012 09:15:45 +0000]
crypto: tegra-se: add NULL check

Fix coverity issue by adding null check
before pointer dereference.

Bug 1046331

Change-Id: Ib4087056f5fb4c1d48f522c43065cd49a0ea5253
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/159498
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: pluto: enable ringer switch
aghuge [Mon, 29 Oct 2012 06:07:10 +0000]
ARM: tegra: pluto: enable ringer switch

Bug 1157359

Change-Id: Ie24c09d1e05a98e807bd6beb528d3e8020dfe040
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/159464
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: mc: setup chip_specific fn ptrs before enabling interrupts
Chris Johnson [Mon, 29 Oct 2012 05:30:25 +0000]
ARM: tegra: mc: setup chip_specific fn ptrs before enabling interrupts

There are instances when we see that the irq fires before we have setup
the actual chip specific function pointers causing a crash in the mc isr

Change-Id: Ied30c1aafca10d6a1b9745507455e40b55014dc9
Signed-off-by: Chris Johnson <cwj@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/159456
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoarm: tegra: Add NET_IP_ALIGN in mach memory.h
Mohan T [Tue, 30 Oct 2012 05:31:18 +0000]
arm: tegra: Add NET_IP_ALIGN in mach memory.h

NET_IP_ALIGN needs to be define in mach memory.h
to support Unaligned skb DMA access in network drivers
like USB rndis and usbnet.

Bug 1025704

Change-Id: I7517410f0b311721f2157cfbc36ba4f5db3f1583
Signed-off-by: Mohan T <mohant@nvidia.com>
Reviewed-on: http://git-master/r/148675
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agosched :Notify users that tickless-timer is enabled
pdabade [Fri, 26 Oct 2012 06:22:18 +0000]
sched :Notify users that tickless-timer is enabled

Notify users that tickless-timer is enabled.

Bug 1049943

Change-Id: If178c85f21d804b88e91b9430ba5576cfc95cbed
Signed-off-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-on: http://git-master/r/147884
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkata Jagadish <vjagadish@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoarm: dt: tegra: fix length of pad control and mux registers
Pritesh Raithatha [Fri, 26 Oct 2012 08:18:54 +0000]
arm: dt: tegra: fix length of pad control and mux registers

Bug 1003210

Change-Id: I6c480f48e555ebf87352b41545ff905f60ebc79b
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/147878
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Stephen Warren <swarren@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

6 years agoRevert "mac80211&nl80211: support to abort a scan request on tx"
Nitin Bindal [Thu, 25 Oct 2012 12:35:01 +0000]
Revert "mac80211&nl80211: support to abort a scan request on tx"

This reverts commit 4ffe2cabbc00d9d12a3884178e3f85aa9f66804c.

This revert fixes p2p connect issue on android.

Bug 1161910
Bug 1059518

Change-Id: I2d10b2cf57fab88ccdfd3d2eca6cdeb36ef9f544
Signed-off-by: Nitin Bindal <nbindal@nvidia.com>
Reviewed-on: http://git-master/r/147584
Reviewed-by: Rakesh Kumar <krakesh@nvidia.com>
Tested-by: Rakesh Kumar <krakesh@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agovideo: tegra: dc: fix shift clk divider
Animesh Kishore [Fri, 19 Oct 2012 14:47:05 +0000]
video: tegra: dc: fix shift clk divider

Real shift clk divider may be fraction.
Add support for the same.

Bug 1012298

Change-Id: I4f9dd7d5b3b9d3b3aa49345491e04f2c5b805a72
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/147510
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agommc: core: Fix print option of UHS mode of SDIO
rrajk [Thu, 25 Oct 2012 08:33:34 +0000]
mmc: core: Fix print option of UHS mode of SDIO

Print correct UHS mode of SDIO card being used.
Bug 1162770

Change-Id: Ice721ea54fbbd57b4dc97961692bae7656b3aa59
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/147485
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

6 years agopluto: calibrated backlight and PRISM for LG 5"
Mitch Luban [Fri, 21 Sep 2012 08:15:04 +0000]
pluto: calibrated backlight and PRISM for LG 5"

PRISM is enabled and includes backlight adjustments
for LG 5" panel to ensure a linear backlight ramp up.

Bug 1047558
Bug 1027942

Reviewed-on: http://git-master/r/142749
(cherry picked from commit 4064265fc7569fdc4b71e0847070e982bc78d5c4)

Change-Id: I5552635b93dc60810a6c4e9d07d55dfa8384984f
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/147349
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agousb: ehci: tegra: Add phy pre_suspend callback.
Raj Jayaraman [Thu, 4 Oct 2012 22:33:45 +0000]
usb: ehci: tegra: Add phy pre_suspend callback.

Bug 1054808

Change-Id: I1de98ced6e8e30794907797bba05ad13190597a9
Signed-off-by: Raj Jayaraman <rjayaraman@nvidia.com>
Reviewed-on: http://git-master/r/147305
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: WK Tsai <wtsai@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agommc: core: Disable powered resume in power restore
RAJKUMAR [Mon, 15 Oct 2012 09:32:51 +0000]
mmc: core: Disable powered resume in power restore

To detect SDIO v3.0 cards, using default enumeration
in power restore instead of powered resume.

Bug 1162770

Reviewed-on: http://git-master/r/144513
(cherry picked from commit 2702c4ded3ec95c74f122a451b0815c676c24de3)

Change-Id: I40915c0636789bd18cccbd69a961c9a7799fde52
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/146973
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>

6 years agocrypto: tegra-se: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 07:29:54 +0000]
crypto: tegra-se: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
clk_prepare_enable and clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: I697d80e857a040e97ea56adee104ae990419c5b6
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146796
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra3: dvfs: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 06:39:22 +0000]
ARM: tegra3: dvfs: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
tegra_clk_prepare_enable and tegra_clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: I119d635ed8ce041359fdc9ab6f7c86743256b2cb
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146780
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoARM: tegra3: actmon: moving to clk prepre APIs
Sivaram Nair [Tue, 23 Oct 2012 06:35:52 +0000]
ARM: tegra3: actmon: moving to clk prepre APIs

The clk_enable/clk_disable pair of APIs are replaced with
tegra_clk_prepare_enable and tegra_clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: Ia0c8072f673a924ca39b878e8f63475cbef5dcbf
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146779
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoARM: tegra: timer: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 06:31:45 +0000]
ARM: tegra: timer: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
tegra_clk_prepare_enable and tegra_clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: I410e8cf8cfbf6622dc1076b22598b7fb55e4f63e
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146778
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoARM: tegra: usb: disable id and vbus wake source
Krishna Yarlagadda [Fri, 28 Sep 2012 11:15:39 +0000]
ARM: tegra: usb: disable id and vbus wake source

Disabling usb id and vbus wake sources

Bug 1056435

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/139658
(cherry picked from commit e6a6bee5f2515f32045adf5f10cb62343f72babd)

Change-Id: I15654bdac5140960f9e6b195e91f56a14e02e76b
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/146741
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agovideo: tegra: host: remove dummy devices for display & dsi
Mayuresh Kulkarni [Wed, 17 Oct 2012 08:39:55 +0000]
video: tegra: host: remove dummy devices for display & dsi

- the real display and dsi devices are owned by tegra-dc
- tegra-dc always access host1x via its parent
- hence there is no need to have dummy devices for display
& dsi in host1x code
- this commit removes these redundant dummy devices

Change-Id: Ie940679b1d4a69c3329928d080e099fbf272af28
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/145184
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agortc: tps65910: Added rtc time init support
Sumit Sharma [Tue, 16 Oct 2012 04:45:38 +0000]
rtc: tps65910: Added rtc time init support

Added support for initializing rtc time
Fixed IRQ numbers in header file
Changed module name fro rtc-tps65910 to tps65910-rtc

Bug 1055083

Change-Id: I067a52ef21e58eb03331d25417062f53e45b082d
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/144765
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agopinctrl: tegra: add suspend-resume support
Pritesh Raithatha [Tue, 16 Oct 2012 10:03:05 +0000]
pinctrl: tegra: add suspend-resume support

Bug 1003210

Change-Id: If6dff8985dfd3c351e6ed24f194efb247e0c63d6
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/144034
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra11: remove wrong mask from cpu_iddq
Gaurav Batra [Tue, 30 Oct 2012 01:10:36 +0000]
arm: tegra11: remove wrong mask from cpu_iddq

Bug 1046108

Change-Id: Ic8ea48dbc60448b76e11b9b0426a717296da825f
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/159926
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoARM: Tegra: XUSB: Remove stubs for xusb_init calls
Krishna Monian [Tue, 30 Oct 2012 02:32:16 +0000]
ARM: Tegra: XUSB: Remove stubs for xusb_init calls

- Remove xusb stub calls
- Revert 442d96a0db540dbc72ed0051e472fb821c23b758.

Change-Id: Ief19f69f8cfaf80e342aeddc222d98c66fe11ed8
Signed-off-by: Krishna Monian <kmonian@nvidia.com>
Reviewed-on: http://git-master/r/159723
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: clock: Clip CPU boot rate to cpufreq table
Alex Frid [Fri, 26 Oct 2012 02:19:25 +0000]
ARM: tegra: clock: Clip CPU boot rate to cpufreq table

Clipped CPU boot rate to cpufreq table during cpufreq driver
initialization. This would help avoid futile attempts by cpufreq
governor to adjust the rate while dvfs regulators are not ready.

Bug 1060647

Change-Id: I8984c0c53798413887f866f03704b9097f40a361
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147792
(cherry picked from commit d9325e0bd3cdd1b8d8e4989a0018718dfddb84d0)
Reviewed-on: http://git-master/r/159644
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: dvfs: Bound CL-DVFS safe voltage setting
Alex Frid [Wed, 24 Oct 2012 04:37:02 +0000]
ARM: tegra11: dvfs: Bound CL-DVFS safe voltage setting

Removed global CL-DVFS non-zero safe output floor imposed on voltage
calculations by commit af5ba3026ce0d4a6908e7006cab99f2edcabf920.

Instead made sure that safe voltage value when switching from open
to closed loop is at least one step above minimum and one step below
maximum (required to provide initial room for closed loop regulation).

Bug 1157439

Change-Id: I5739d0f62ada92d24b0f5230f4cd4368062f0c87
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147352
(cherry picked from commit 550be6c793f522bb996e311c7da3ff92cf0f88ac)
Reviewed-on: http://git-master/r/159643
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra: dvfs: Update rail statistic
Alex Frid [Sat, 20 Oct 2012 06:04:29 +0000]
ARM: tegra: dvfs: Update rail statistic

- Replaced fixed rail bins with per-rail-per-platform bins (by
default use backward compatible 12.5mV bin)
- On Tegra11 set bins for all rails on cvb alignment boundary (10mV)
- Increased maximum number of bins to 50
- Fixed rail voltage report in dfll mode: compensate 1mV adjustment
used in this mode to force voltage update

Change-Id: I0b7fb49900656de33bc77bb8267dbde713a2441f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/146113
Reviewed-on: http://git-master/r/159642
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: Tegra: Dalmore: Support LG 5" Panel
Matt Wagner [Fri, 12 Oct 2012 21:40:58 +0000]
ARM: Tegra: Dalmore: Support LG 5" Panel

Split LG panel out to support it based on Board ID

Bug 1066897

Change-Id: I8c1ef6569ea2e9b9ac0e229594dce1309800a918
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/147755
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: usb: bind vbus regulator with device
Krishna Yarlagadda [Wed, 24 Oct 2012 08:14:02 +0000]
ARM: tegra: usb: bind vbus regulator with device

passing tegra-ehci.0 as the device for vbus supply
Bug 1055918

Change-Id: Ie52c6f52e91bb4adfd56f9c29db2809ff2d62289
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/147183
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: pluto: pass device to regulator_enable
Gaurav Batra [Tue, 30 Oct 2012 00:38:29 +0000]
arm: tegra: pluto: pass device to regulator_enable

During conflict resolutions at the time of integration,
a part of the change that took care of this problem was
over-written by another change with a different base.
Which resulted in device argument to be missing from
a few regulator calls. This patch, fixes that issue.

Bug 1166698

Change-Id: I6584968938dd343452c4660ea4e851b3523ef3ff
Signed-off-by: Gaurav Batra <gbatra@nvidia.com>
Reviewed-on: http://git-master/r/159924
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: clock: Rename shared bus operations.
Alex Frid [Tue, 30 Oct 2012 04:12:49 +0000]
ARM: tegra: clock: Rename shared bus operations.

Renamed shared_bus operations that are actually applied to bus
user clock (rather than bus clock itself) to shared_bus_user
operations.

Change-Id: Ic73db770264f4890a2c93e54dff16fe6c97d2c3e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/159748
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jin Qian <jqian@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: Tegra: Dalmore: Activate Hall Effect Sensor
Matt Wagner [Wed, 10 Oct 2012 00:17:26 +0000]
ARM: Tegra: Dalmore: Activate Hall Effect Sensor

Set up gpio-key wakeup with the Hall Effect sensor to be SW_LID
to enable lid open and close logic

Bug 1156171

Reviewed-on: http://git-master/r/142805
(cherry picked from commit d6875d355ada98bcaf1785bd6e6f9afcc6890346)

Change-Id: I546302f0768d5ca20b96eae82d90b4cf27a8fa31
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/159670
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoARM: tegra: clock: Mark BW users in the clock tree
Alex Frid [Sat, 27 Oct 2012 07:46:38 +0000]
ARM: tegra: clock: Mark BW users in the clock tree

Marked bandwidth shared users with "+" sign in the clock tree.

Change-Id: I9cbc766a6407d6075b2f39638a9f83f22d98e1f7
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/159430
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agodrivers: video: tegra: dc: Expose HBR capability
Rahul Mittal [Mon, 29 Oct 2012 12:50:47 +0000]
drivers: video: tegra: dc: Expose HBR capability

Enable HBR bit in HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0 register
This exposes HBR pin capability in HD-Audio codec

Bug 966764

Change-Id: I5253daf9e2864b728bf8aab1a71a2f0e4230debd
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/159550
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoasoc: tegra: Fix error in checking SMMU flag
Rahul Mittal [Mon, 29 Oct 2012 06:26:23 +0000]
asoc: tegra: Fix error in checking SMMU flag

SMMU flag check was wrong due to which DMA allocs were done using SMMU
Corrected check to disable SMMU allocations

Bug 1160332
Bug 1155696

Change-Id: I154716d1dc93e45f1f9f1c997bf63fa6f23b73bc
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/159472
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Ravindra Lokhande <rlokhande@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

6 years agoasoc: tegra: cs42l73: VSPIN dapm route with DMIC event
Rahul Mittal [Mon, 29 Oct 2012 05:54:56 +0000]
asoc: tegra: cs42l73: VSPIN dapm route with DMIC event

Enable/disable VSPIN in dapm route only with DAPM event
Default enable caused 1.3W power in LP0 as codec suspend was failing

Bug 1053365
Bug 1161544

Change-Id: I8a4ed0801249ec11da089f0cc597d8abdc6c2dbb
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/159463
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: Tegra: Dalmore: Add P2454 Board Support
Matt Wagner [Fri, 5 Oct 2012 18:37:17 +0000]
ARM: Tegra: Dalmore: Add P2454 Board Support

Add support for P2454 Board

Bug 1066897
Change-Id: I67d99c474b52439eeaecb08c17b65b90a5c419fb
Signed-off-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-on: http://git-master/r/147754
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agospi: tegra11: set value of SPI FIFO depth
Kunal Agrawal [Tue, 23 Oct 2012 08:42:38 +0000]
spi: tegra11: set value of SPI FIFO depth

The value of SPI FIFO depth has been now set to
64.

Change-Id: I9c1ab1bddc4635d4ec1696f5763a5822d688ad71
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/146822
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: powergate: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 07:20:18 +0000]
ARM: tegra: powergate: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
tegra_clk_prepare_enable and tegra_clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: I9980287785eae070d5f75d4f025a202d2867deba
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146792
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: pm: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 07:09:37 +0000]
ARM: tegra: pm: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
tegra_clk_prepare_enable and tegra_clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: I24af62c507f40a8393024eda3d853fe7ed29f203
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146791
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: dma: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 07:06:21 +0000]
ARM: tegra: dma: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
tegra_clk_prepare_enable and tegra_clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: Ia5c3de38697cfe9e55e336175eff7b5ac58b744c
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146788
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: csi: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 07:05:35 +0000]
ARM: tegra: csi: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
tegra_clk_prepare_enable and tegra_clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: I559cadd1c6ec4a57a1c95c3b48bd6d5687679ab0
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146787
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoarm: tegra: power: cleanup dynamic VDD_CPU EDP capping code
Diwakar Tundlam [Fri, 26 Oct 2012 23:55:51 +0000]
arm: tegra: power: cleanup dynamic VDD_CPU EDP capping code

Refactor data structures and names in preparation for dynamic/leakage
parameters update.

Bug 1046108

Change-Id: Id7ed9b4a5aedbd8556fa1520eab93e91fd728556
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/159377
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: kernel: update __cpu_disable to use cache LoUIS maintenance API
Lorenzo Pieralisi [Fri, 7 Sep 2012 05:39:15 +0000]
ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API

When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.

Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.

This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.

This patch updates __cpu_disable to use the new LoUIS API cache operations.

Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Change-Id: Ib95a626f00ff0ab8c1b974e57f62ebef92175510
Reviewed-on: http://git-master/r/147784
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: kernel: update cpu_suspend code to use cache LoUIS operations
Lorenzo Pieralisi [Fri, 7 Sep 2012 05:36:57 +0000]
ARM: kernel: update cpu_suspend code to use cache LoUIS operations

In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore. For processors like A15/A7 flush_cache_all() ends up cleaning
all cache levels up to Level of Coherency (LoC) that includes
the L2 unified cache.

When a single CPU is suspended (CPU idle) a complete L2 clean is not
required, so generic cpu_suspend code must clean the data cache using the
newly introduced cache LoUIS function.

The context and stack pointer (context pointer) are cleaned to main memory
using cache area functions that operate on MVA and guarantee that the data
is written back to main memory (perform cache cleaning up to the Point of
Coherency - PoC) so that the processor can fetch the context when the MMU
is off in the cpu_resume code path.

outer_cache management remains unchanged.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Change-Id: I305b9d3bbb2def6f32d3d08769babd6a99798194
Reviewed-on: http://git-master/r/147783
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11x: cpuidle: Stats for C1NC/C0NC/CRAIL
Bo Yan [Thu, 25 Oct 2012 23:11:04 +0000]
ARM: tegra11x: cpuidle: Stats for C1NC/C0NC/CRAIL

This patch adds stats for power gating C0NC and C1NC partitions,
it also adds stats for fast cluster rail gating.

The numbers under column CPU0 are the sum of CE0 power gating,
C0NC power gating, and rail gating. The numbers under column cpulp
are the sum of CELP power gating and C1NC power gating.

Change-Id: Ia02f78ed124652b1deac3a6e29a47aaec8fcd910
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/147745
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agotf_driver: integrate latest TL release
Hyung Taek Ryoo [Wed, 24 Oct 2012 07:22:49 +0000]
tf_driver: integrate latest TL release

V9 version for Tegra3: TF_TEGRA3_AB02.02.38127
V9 version for Tegra4: TF_TEGRA4_AC02.01e1.38186

This package is the first release of Trusted Foundations v9
It supports all the features supported by TFv8 (i.e. TF_TEGRA3_AB01.13)
1) Dynamic loading of secure services is supported
2) ARM generic and Tegra specific code are regrouped in HAL driversthat can be repostlinked
3) The fix for imprecise abort observed during Widvine session

bug 969937
bug 969981

Change-Id: I1fd0d0df21ead84fb226ba2e0a6b3cf463472a26
Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-on: http://git-master/r/147176
GVS: Gerrit_Virtual_Submit
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

6 years agovideo: tegra: dc: power optimize DC and host1x clk
Jon Mayo [Tue, 17 Jul 2012 22:56:44 +0000]
video: tegra: dc: power optimize DC and host1x clk

Use threaded IRQ to support enabling clocks in interrupt handling.
Use io_start and io_end to hold and release host1x clock.
Disable IRQ after it is first requested to balance enable/disable.
Use disable_irq_nosync() anywhere dc->lock is held to avoid deadlock.

Change tegra_dc_update_windows() to always be balanced with
tegra_dc_sync_windows(). Sync points (from host1x) are potentially lost if
clock gated after update, generally this only affects applications that
update at a slow frame rate.

To balance update and sync calls, Colormap/LUT code now performs a
sync_windows on a LUT change, this makes LUT changes slower and take effect
immediately.

Add a nosync version of tegra_dc_dsi_write_data to be used within dsi
module.

Bug 1036025
Bug 1031933
Bug 1030415
Bug 1029041
Bug 1028716
Bug 1025621
Bug 1020592
Bug 1013506
Bug 1002768
Bug 955184
Bug 929609
Bug 899059
Bug 887342

Change-Id: Idc9b4c2922ad3d476d57fdf760acae76f0c837e2
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/146107
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>

6 years agomedia: video: tegra: ov9772: fix Coverity error
Frank Chen [Fri, 26 Oct 2012 21:32:46 +0000]
media: video: tegra: ov9772: fix Coverity error

Fix incorrect sizeof expression.

Bug 1055065

Change-Id: I735c3df49024d240f8d029a753e3ffa90b953665
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/159286
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: usb_phy: add fence read for T114
Suresh Mangipudi [Fri, 5 Oct 2012 14:42:05 +0000]
arm: tegra: usb_phy: add fence read for T114

Fence read will be needed by T114 as the h/w issue is not resolved.

Bug 1056145

Reviewed-on: http://git-master/r/142177
(cherry picked from commit 1fcb62e55e4e558887fa98aa3c3c72b06087f9f4)

Change-Id: I477cecb8299f1e51e64a06fd30b414e411b250ed
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/159487
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>