7 years agoregulator: write permission for only user
Sachin Nikam [Thu, 16 Jun 2011 09:52:26 +0000]
regulator: write permission for only user

Write permission only for User for syncevent_regulators
sysfs attribute.

This is needed so as to pass FileSystemPermission CTS.

Bug 840409

Original-Change-Id: Iad1ac9fc63b9471b2f7c9f2c12524512b3f5941e
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/36897
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Rb71c94a12e155ae630d09f30fb42df4d83cc6e7c

7 years agovideo: tegra: dsi: Update DSI pad register.
Kevin Huang [Tue, 21 Jun 2011 22:24:03 +0000]
video: tegra: dsi: Update DSI pad register.

Bug 829327

Original-Change-Id: If17ec2aafccdfad1834f3fc914398cbd3babba01
Reviewed-on: http://git-master/r/36818
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R32a6361714d6352fe1ae938ac11dc0ea6eca07ce

7 years agotegra: dc: adding max pixclock check for hdmi
Donghan Ryu [Sun, 22 May 2011 09:30:31 +0000]
tegra: dc: adding max pixclock check for hdmi

tegra_dc_hdmi_equal doesn't check pixclock and some devices doesn't
support 148.5Mhz pixclock which is needed for 1080p@60. However,
adding 1080p@30 to the supported hdmi mode array makes
tegra_dc_hdmi_equal to retun 1080p@60. Therefore, this commit adds
max pixclock check to distinguish modes with different pixclock

Bug: 815409

Original-Change-Id: Ifbf07929e3c7a92172856518a55e9d4a04f0b943
Reviewed-on: http://git-master/r/32511
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R5b3c53a840ea0855d4298d92ec8db696a0c2f40e

7 years agoARM: tegra: generate status events for all clocks
Peter De Schrijver [Mon, 2 May 2011 12:43:06 +0000]
ARM: tegra: generate status events for all clocks

Original-Change-Id: I55f52ab038764079811c68b3bb3738a9de17d7bf
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: http://git-master/r/31530
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R25afcccf5ff8d7a88b705ce7f68ab83e818ae1e4

7 years agovideo: tegra: dc: No S_IWGRP permission for sysfs attrbs
Sachin Nikam [Thu, 16 Jun 2011 11:28:18 +0000]
video: tegra: dc: No S_IWGRP permission for sysfs attrbs

Don't give write permission for Group for sysfs:
stats_enable, enable and smart dimmer attributes.

Bug 840409

Original-Change-Id: Ic51e2a831c7bffed055d5120e684022ff64736c8
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/36994
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R235fd834aaf57f9205e83335a3aab327d0848587

7 years agoARM: tegra: sysfs write permission for user only
Sachin Nikam [Thu, 16 Jun 2011 07:46:26 +0000]
ARM: tegra: sysfs write permission for user only

Giving read-write permission for user only for sysfs attributes.
Group and other will have only read permission.
- tegra_mc_stats: enable and quantum
- susend: mode
- clock: rate, parent, state

File System Permission CTS expects this to pass.

Bug 840409

Original-Change-Id: I3335b27124be38f0f5ea4cc415fef6532e574680
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/36867
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R3360698aa910479a0eccb460656d104912af99bb

7 years agoarm: tegra: cardhu: handle regulator_get error
Prayas Mohanty [Wed, 22 Jun 2011 11:05:43 +0000]
arm: tegra: cardhu: handle regulator_get error

For sh532u, when regulator_get fails, it still returns
unwanted value. Reset regulator variable to NULL and
return error.

bug 841078

Original-Change-Id: I7265b2b5ca40405c92555a242d7d39f5dfe2bb07
Reviewed-on: http://git-master/r/37848
Reviewed-by: Alok Chauhan <alokc@nvidia.com>
Tested-by: Prayas Mohanty <pmohanty@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R74efd1bf6a77b71f19a32058f55ba094e213648d

7 years agoarm: tegra: cardhu: enable PMU features for lp0
Luke Huang [Wed, 25 May 2011 01:00:49 +0000]
arm: tegra: cardhu: enable PMU features for lp0

Enable PMU only features for LP0. System-wise LP0 is not enable by default yet.

1. Allow pmu SLEEP state
2. Keep 32KHz clk out from PMU enabled on LP0
3. Set core_power_req to be high enable
4. Turn off VDD1 (power for Vcore) on LP0

Original-Change-Id: Id6babdfc36de1a597f8df5d2943ef048699013d4
Reviewed-on: http://git-master/r/32853
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R1be5db70870d950a7ffe1361e60aad4156398172

7 years agovideo: tegra: dsi: Set dc and dsi clock for DSI burst mode.
Kevin Huang [Thu, 23 Jun 2011 01:32:23 +0000]
video: tegra: dsi: Set dc and dsi clock for DSI burst mode.

Original-Change-Id: Ia631f7bae013f378c36fe05c665ef178bef12a46
Reviewed-on: http://git-master/r/31904
Reviewed-by: Kevin Huang <kevinh@nvidia.com>
Tested-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>

Rebase-Id: R5b5d821365fce376a19a5527c5a9ecc9d2bfbb14

7 years agovideo: tegra: Do not set HDMI as a wakeup source
Sanjay Singh Rawat [Sun, 12 Jun 2011 12:05:15 +0000]
video: tegra: Do not set HDMI as a wakeup source

HDMI connect/disconnect will not affect the suspended device.

bug 835157

Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/37174
(cherry picked from commit 31f69bbe2e832a7dfa7678bb965b3461f421e0f5)

Original-Change-Id: Id66cdfcc5435df5abfab54fff823968ae67465a8
Reviewed-on: http://git-master/r/38204
Tested-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>

Rebase-Id: R58dac5622778d03bee6d6e73ede3913c24569112

7 years agoARM: tegra: clock: Add clock rate change notification
Alex Frid [Sun, 12 Jun 2011 06:23:50 +0000]
ARM: tegra: clock: Add clock rate change notification

Original-Change-Id: I97434334a4214180a365d9709a331405da135669
Reviewed-on: http://git-master/r/36202
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7bfea35bf7b2e083e594538e245e3b74e25d090a

7 years agoInput: atmel_mxt_touch: NVIDIA touch customization
Robert Collins [Wed, 15 Jun 2011 21:43:41 +0000]
Input: atmel_mxt_touch: NVIDIA touch customization

* Fix suspend/resume bug to prevent unecessary i2cinterrupts when suspended.
* Change input device name to match NVDA IDC name.
* Add I2C address defines.
* Change "printk" to "dev_info" function calls.

BUG 826854

Original-Change-Id: Ic1b25bc469b86d8a26e876e80973597d9f6fb107
Reviewed-on: http://git-master/r/35285
Reviewed-by: Robert R Collins <rcollins@nvidia.com>
Tested-by: Robert R Collins <rcollins@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rcba51c79d3c004372c0be18538f14f56a2249bc0

7 years agoInput: atmel_mxt_ts: Atmel customizations to touch.
Robert Collins [Mon, 6 Jun 2011 21:57:01 +0000]
Input: atmel_mxt_ts: Atmel customizations to touch.

Integrate changes made by Atmel.  These changes are in addition to
mainline driver.

NOTE:  Driver will compile as a stand-alone.

BUG 826854

Original-Change-Id: If13688d90d97b71718576f3fb756496f57a965d7
Reviewed-on: http://git-master/r/35280
Reviewed-by: Robert R Collins <rcollins@nvidia.com>
Tested-by: Robert R Collins <rcollins@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Reb8ae14299d248c0ce69e52b26a8816d1a0ee057

7 years agoarm: tegra: Fix file permissions
Scott Williams [Thu, 23 Jun 2011 00:24:05 +0000]
arm: tegra: Fix file permissions

Remove executable permission from source files.

Original-Change-Id: I174be22b3b753569e33de1dc1fed2e823fda6120
Reviewed-on: http://git-master/r/37956
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R904a5f20719575c5921b9bf1e9b54e0db13cefee

7 years agovideo: tegra: nvmap: free vm_struct in nvmap_munmap()
kenjchen [Wed, 8 Jun 2011 07:18:27 +0000]
video: tegra: nvmap: free vm_struct in nvmap_munmap()

In nvmap_munmap(), remove_vm_area just remove the allocated memory
page information. It doesn't de-allocate vm_struct. kfree()
should be used to avoid memory leak in nvmap.

Bug: 833796
Original-Change-Id: Ibd0309c1ff323fb8110870ace27819f5a1e006ba
Reviewed-on: http://git-master/r/35638
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R417df608c4a24667af81f328bfb65cf3389e19ae

7 years agoarm:tegra:enterprise:board changes for PMU RTC
venu byravarasu [Thu, 16 Jun 2011 11:12:40 +0000]
arm:tegra:enterprise:board changes for PMU RTC

Board changes needed to enable TI PMU 80031 RTC
on enterprise are added.

bug 833336

Original-Change-Id: Ic2d2374ed6bff773964bd7bf6b81c69feda2d9b1
Reviewed-on: http://git-master/r/34457
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Raa8d932bdbd4586201160e4070077b59ce5f55cc

7 years agoarm: tegra: cardhu: Uart platform data for hsuart driver
Laxman Dewangan [Tue, 21 Jun 2011 10:47:07 +0000]
arm: tegra: cardhu: Uart platform data for hsuart driver

Adding uart platform data for the hsuart driver. Passing the
clock information through the platform data.

bug 837140
bug 836059

Original-Change-Id: I321cd904ea072b0bc931016d46a4fa8462c28c8d
Reviewed-on: http://git-master/r/37636
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R2012b1e682e406e31818f38eff0e4c9e8e7358eb

7 years agoarm: tegra: enterprise: adding power off support.
venu byravarasu [Wed, 22 Jun 2011 09:16:08 +0000]
arm: tegra: enterprise: adding power off support.

Board related changes, needed to turn off the device,
are being addded.

bug 833661

Original-Change-Id: Ia5f5f69fc19367995e6ad988a185825bd7b4d969
Reviewed-on: http://git-master/r/36670
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Reaa3eb086baabd1d3b37a86555c7d2cfcb2eea68

7 years agomisc: mpu3050: removed printk
Jon Mayo [Tue, 14 Jun 2011 20:43:53 +0000]
misc: mpu3050: removed printk

unnecessary printk removed

BUG 842174

Original-Change-Id: I4b194a175fa2d040d1512804787f1351dbefc336
Reviewed-on: http://git-master/r/36582
Reviewed-by: Robert R Collins <rcollins@nvidia.com>
Tested-by: Robert R Collins <rcollins@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>

Rebase-Id: R8f555dd608b30531fcde5d7c411c848475418a79

7 years agortc: tps80031: Adding driver for TI PMU RTC 80031
venu byravarasu [Tue, 21 Jun 2011 11:45:03 +0000]
rtc: tps80031: Adding driver for TI PMU RTC 80031

With this change, RTC driver for TI PMU 80031 is being checked in.

bug 833336

Original-Change-Id: If4789a5dd49163d2391ab016845ff5807c061f12
Reviewed-on: http://git-master/r/34453
Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R98c49f456537e65d02460e738029673e7eea1bc0

7 years agoserial: tegra: Support for best clock source
Laxman Dewangan [Tue, 21 Jun 2011 10:38:08 +0000]
serial: tegra: Support for best clock source

Finding the best clock source for uart controller which can
generate the clock rate having minimum error between requested
baudrate and configured baudrate.

bug 837140
bug 836059

Original-Change-Id: I4e751b238612a21d894ee8e6611886ab6e832a36
Reviewed-on: http://git-master/r/37635
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: Rbcfe08c513308bf003ad20c06085499da5d71b66

7 years agomfd: tps80031: Adding Power off functionality
venu byravarasu [Fri, 17 Jun 2011 07:07:57 +0000]
mfd: tps80031: Adding Power off functionality

Implementing power off functionality to turn off the device.

bug 833661

Original-Change-Id: I2a08f96de7a9814967c774530659f4db47946acc
Reviewed-on: http://git-master/r/35054
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

Rebase-Id: R9266dff9162e4d6e372c7807275c0f22b349464d

7 years agousb: otg: tegra: correcting enable/disable clocks
Rakesh Bodla [Fri, 17 Jun 2011 12:17:06 +0000]
usb: otg: tegra: correcting enable/disable clocks

usbd clock should not be disabled in the probe, otherwise
controller will not work.

Bug 836594

Original-Change-Id: I93754344d1c5944ea1220427b5d85eb343b44d1c
Reviewed-on: http://git-master/r/37300
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>
Tested-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>

Rebase-Id: R17ad10568ef1974f39e1da21a28a30f23a2b229f

7 years agoarm: tegra: enterprise: Configure pmu int on active low
Laxman Dewangan [Tue, 21 Jun 2011 14:28:22 +0000]
arm: tegra: enterprise: Configure pmu int on active low

The PMU generates interrupt as active low. So configuring the
Power management unit to have the active low interrupt from PMU_INT
pin.

bug 839238

Original-Change-Id: I69e5cfb756d3b9e39fe7515cf8126753800cda03
Reviewed-on: http://git-master/r/37670
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com>

Rebase-Id: R4e0d333cc9dc2186ecc8b651c127912964769ff9

7 years agovideo: tegra: dc: make hdcp respond quickly on HDMI modeset.
Seongho Joo [Tue, 7 Jun 2011 17:38:46 +0000]
video: tegra: dc: make hdcp respond quickly on HDMI modeset.

hdcp worker could be in sleep during modeset.
The front part of the video could be lost because of it.
This change makes hdcp respond quickly to shorten the delay.

bug 826468

Reviewed-on: http://git-master/r/36215
(cherry picked from commit e856cedd18d60c3636b694f1fba612259abf7229)
Original-Change-Id: I1e907753e1d2eec8514bf5bc2f4166502c5477dc
Reviewed-on: http://git-master/r/37422
Tested-by: Seongho Joo <sjoo@nvidia.com>
Reviewed-by: Jonathan Mayo <jmayo@nvidia.com>

Rebase-Id: R94af8a09f68427762618cac0a9f21f9b5fedbe6b

7 years agoarm: tegra: pm269: Correct the input supply for HDMI
Alok Chauhan [Thu, 9 Jun 2011 16:29:09 +0000]
arm: tegra: pm269: Correct the input supply for HDMI

change the input supply to master 5v to enable VDDIO_HDMI
signal for HDMI.

Bug 825778
Bug 823160

Original-Change-Id: I2d6360ab3769ff876bdb7d0e0b34d9298aa780d0
Reviewed-on: http://git-master/r/35904
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R0ad5c2ba75a7fd6c5ab26f27e6aa987681a6b014

7 years agoarm: tegra: usb: USB controller set to reset
Suresh Mangipudi [Thu, 9 Jun 2011 14:22:50 +0000]
arm: tegra: usb: USB controller set to reset

1. The usb UTMIP controllers are set to reset mode when there is no usb cable.
2. Power down the reciever circuitory.
3. Set the OTG_PD for instances which do not use OTG.

Bug 829628

Original-Change-Id: I90b5c4aad30cf29ab4817aa3479fa323a20699bc
Reviewed-on: http://git-master/r/35894
Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com>
Tested-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

Rebase-Id: Rfe422c4ccb5b4ca4445f2199b6aed39f74143e3b

7 years agonvhost: Make 3D workaround Tegra3 A01 only
Terje Bergstrom [Thu, 19 May 2011 06:35:16 +0000]
nvhost: Make 3D workaround Tegra3 A01 only

3D hardware workaround is needed for Tegra3 A01 only. With this patch, we
read run-time whether it should be enabled or not.

Workaround should be removed once A01's have been phased out.

Bug 786316

Original-Change-Id: Icd1b85b30a53c74d2e5c7a6df65a805d1fe5147c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/32136
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R6053c07b62aea3c2710d0d2ad6b5647a9fcf486b

7 years agoarm: tegra: cardhu: Modify modem w_disable control.
Raj Jayaraman [Mon, 13 Jun 2011 21:18:41 +0000]
arm: tegra: cardhu: Modify modem w_disable control.

Gpio controlling w_disable has changed since Fab3.
Modify it accordingly.

Bug 819563

Original-Change-Id: Idbeb9467168aa91c5cf942f72ec5d581a28dc4d1
Reviewed-on: http://git-master/r/36368
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R9f571abed87a8da6005f2933d2292f502b05d977

7 years agotegra: avp: implement NvRmPowerModuleClockConfig() for AVP
Mayuresh Kulkarni [Wed, 13 Apr 2011 11:14:26 +0000]
tegra: avp: implement NvRmPowerModuleClockConfig() for AVP

this change will allow clock rate control from AVP.

Original-Change-Id: I470a401a93f769fa2f8b6e96158d1515c4034ca9
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/31839
Reviewed-by: Mandar Potdar <mpotdar@nvidia.com>
Tested-by: Mandar Potdar <mpotdar@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R12982bdc7285748188af7aa5a71238d45fb873c3

7 years agoi2c: tegra: Remove the synchronization between isr and caller
Alok Chauhan [Thu, 26 May 2011 06:01:25 +0000]
i2c: tegra: Remove the synchronization between isr and caller

Remove the handling of synchronisation between isr and caller.
This change has become obsolete because now clock driver will make
sure that any write operations will be completed before disabling the
driver clock.

Original-Change-Id: I95957351fd1f291a59182fddbb619ffd02a0db63
Reviewed-on: http://git-master/r/33099
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Alok Chauhan <alokc@nvidia.com>

Rebase-Id: Rec9671e9283870630fda6ceb977b99b92c3a99a9

7 years agoARM: tegra: clock: Synchronize Tegra3 clocks scaling
Alex Frid [Sat, 14 May 2011 06:58:33 +0000]
ARM: tegra: clock: Synchronize Tegra3 clocks scaling

On Tegra3 clocks of major h/w engines - 2D/EPP/3D/MPE/VDE/SE - are
sourced from PLLC through integer dividers. Low resolution of these
dividers does not allow to set scaling frequency levels matching
intermediate voltage steps within core voltage range. Only changing
the source frequency can achieve it. However, re-locking common PLL
while engines are running requires synchronization of engines clock
control, and complex operations including switching to backup sources
during PLL stabilization time.

This commit introduces a new virtual clock "cbus" to support clocks
synchronization and PLLC re-locking procedures. The dvfs table for
cbus clock is constructed from frequency steps close to maximum rates
for each characterized core voltage level. Engine clocks exposed to
the drivers are no longer physical module clocks, but shared cbus
users. Setting the rate for such clock specifies the clock floor.
The final cbus rate is determined as maximum floor setting for all
enabled engines, and rounded up along the cbus dvfs ladder. Actual
engine clock rate is set equal to the cbus clock rate. Hence, engines
will be running close to maximum frequency for minimum voltage that
satisfies all floor requests.

Special case: Host1x. This clock will be always configured at 1/2 of
cbus clock rate, and its shared user floor request is ignored by cbus
target frequency calculations.

Added cbus dvfs tables and updated VDE engine dvfs data.

Original-Change-Id: Ic02ea08227f920dc4f47b2389c311a23cea472f6
Reviewed-on: http://git-master/r/36199
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: R1b7556f1cca12987e4f7c8c6342778da1cec1915

7 years agoARM: tegra: enterprise: panel power management
Animesh Kishore [Wed, 15 Jun 2011 10:33:30 +0000]
ARM: tegra: enterprise: panel power management

Implementation for dsi panel power management

Bug 833709
Bug 793857

Original-Change-Id: Ia13c9b0a4a8a4ec1d802ad56cdbcdc27e5f183d4
Reviewed-on: http://git-master/r/36139
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Tested-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>

Rebase-Id: R38c4c8dedf3dde4e1413fe1b105af1827b65d431

7 years agoarm: tegra: power: fix lp0 resume failure
Luke Huang [Mon, 6 Jun 2011 20:05:44 +0000]
arm: tegra: power: fix lp0 resume failure

Do not check PLLX lock bit on PLLX sanity check, since it might not be in the
lock state yet.

Original-Change-Id: I607210330dc355a1359dc856a192bd4163df4cb3
Reviewed-on: http://git-master/r/35261
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: R1ea05b0640b93de011109de3402d8810a64defcc

7 years agoarm: tegra: enterprise: Controls for 3d barrier
Alex Odorovic [Mon, 23 May 2011 10:42:27 +0000]
arm: tegra: enterprise: Controls for 3d barrier

Adds userspace control for 3d barrier on 3d panel found on enterprise.
Provides 2 sysfs files:

/sys/devices/nvhost/tergradc/stereo_mode
/sys/devices/nvhost/tergradc/stereo_orientation

These are used to enable/disable 3d barrier and control it's
orientation, respectively.

Original-Change-Id: I580f0992c19cbee9a695bac9bef503c9888abc83
Reviewed-on: http://git-master/r/32575
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>

Rebase-Id: Rf97ba4335f3f79697159c574ef00cbdd8330b1b6

7 years agoARM: defconfig: Enable PCA953x for cardhu
Krishna Yarlagadda [Fri, 3 Jun 2011 06:08:12 +0000]
ARM: defconfig: Enable PCA953x for cardhu

Enable CONFIG_GPIO_PCA953X on cardhu

Bug 829875

Original-Change-Id: I3e5573e053123387b59a16e885e9f951c30d1f87
Reviewed-on: http://git-master/r/35012
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Tested-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

Rebase-Id: Rc4a886e0cabcdec8ff32c1a5f96c23881f97bca0

7 years agoarm: tegra: configs: Enabled Security Engine for Enterprise
Kasoju Mallikarjun [Wed, 1 Jun 2011 13:28:37 +0000]
arm: tegra: configs: Enabled Security Engine for Enterprise

Original-Change-Id: I571de9cecd90659de9b1fa25440274fedf85ab1e
Reviewed-on: http://git-master/r/34709
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: R715b1ceb7c6af5fbb01362185a2c0ee2ee5bb1ef

7 years agoarm: tegra: enterprise: Enabling Security Engine
Kasoju Mallikarjun [Mon, 13 Jun 2011 11:37:28 +0000]
arm: tegra: enterprise: Enabling Security Engine

Bug 622025

Original-Change-Id: I64b560f831b33b92f431242032a7828a88d098a4
Reviewed-on: http://git-master/r/34711
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

Rebase-Id: R29d5a1a3ae2dfb63ad9120721b7a770cbea4effb

7 years agoARM: tegra: usb: update default UTMIP phy setting
Jay Cheng [Thu, 5 May 2011 20:03:52 +0000]
ARM: tegra: usb: update default UTMIP phy setting

Revise some default settings for utimp phy

Bug 815848

Reviewed-on: http://git-master/r/30257
(cherry picked from commit 5f2b525a73dd48435975ef72937d1b8627e1c917)

Original-Change-Id: I403746d85a3ef32d05bec5867b407f41e1f614e4
Reviewed-on: http://git-master/r/30568
Tested-by: Cho-Che Cheng <jacheng@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Rebase-Id: R0025020748320e50ad9c9b035e98b17611027742

7 years agoARM: tegra: power: use buffered memory for suspend context
Jin Qian [Thu, 11 Aug 2011 22:57:43 +0000]
ARM: tegra: power: use buffered memory for suspend context

use buffered memory to bypass L2
add memory barrier after cpu suspend

Bug 862494

Change-Id: I0592ebd6608d2581700b9ae965de3e7d8aa2cabe
Reviewed-on: http://git-master/r/47172
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Tested-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rfee82dddd83449e730ccfcd5f6359bbaa00582a7

7 years agoARM: tegra: power: Enable LP2 mode on Cardhu platform
Scott Williams [Mon, 15 Aug 2011 19:37:21 +0000]
ARM: tegra: power: Enable LP2 mode on Cardhu platform

Change-Id: If47d86312afd02fb8e193631b7baec66c3232864
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/47163
Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rfadb990de8dc73fd53392029cc622629c8b986bd

7 years agoARM: tegra2: power: Don't disable CPU1 GIC interface in LP2
Scott Williams [Mon, 15 Aug 2011 16:08:06 +0000]
ARM: tegra2: power: Don't disable CPU1 GIC interface in LP2

Leave the GIC processor interface enabled for CPU1 during LP2.
Disabling it prevents CPU1 from waking up on IPIs.

Change-Id: I32ae01066f21f8b4fba1fd0da392bc691c29bf49
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R16db6ca494653a5d8c61cc7ac2b5cb2c3fa9f46f

7 years agoARM: tegra: power: Perform L2 cache sync when flushing L1
Scott Williams [Fri, 12 Aug 2011 17:21:35 +0000]
ARM: tegra: power: Perform L2 cache sync when flushing L1

Change-Id: I7b769bec8fc2dc0cd6db34e125f1cfd45aea8b12
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rcf33e9438333a90b3aa9bf29925a277d65317f84

7 years agoARM: tegra2: power: Fix reset race condition between the CPUs
Scott Williams [Thu, 11 Aug 2011 20:57:49 +0000]
ARM: tegra2: power: Fix reset race condition between the CPUs

During LP2 for CPU idle on Tegra2, there could be a race condition
between the CPUs. CPU1 cannot autonomously shut itself down (put
itself into reset). CPU1 must be reset by CPU0 but only when it
has no outstanding memory or I/O transactions going on (i.e., it
is in the WFI state). CPU1 indicates its readiness to be reset
by setting status in a PMC scratch register. If CPU1 wakes up
and CPU0 sees CPU1's ready to be reset status before CPU1 can
clear it CPU1 could be reset at inappropriate times resulting
in loss of cache coherency and ultimately a kernel panic.

Eliminate the race condition by ensuring that:

- CPU1's reset ready status is cleared as early as possible
  before CPU1 rejoins the coherent world.
- Use writel when updating the IRAM LP2 status flags to ensure
  the IRAM and coherent memory views of the flags are consistent.
- If there is not enough time remaining for CPU1 to be in LP2 for
  the minimum residency time, clear CPU1's reset status flag
  before entering WFI so that CPU0 will not wait for CPU1 to be
  ready to reset (since it won't be if there is insufficient time).

Change-Id: I20dc5c6406b1521f20852294d48ce6d67f0926b9
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd485f696126d7ca019d15651b839d4f2fc595848

7 years agoARM: tegra: timer: Save TWD counter instead of load register
Scott Williams [Wed, 10 Aug 2011 21:18:37 +0000]
ARM: tegra: timer: Save TWD counter instead of load register

In tegra_twd_suspend(), save the remaining count rather than the
initial count of the timer.

Also catch invalid TWD configurations during suspend/restore
(e.g., enabled with a zero count).

BUG 862605

Change-Id: I05bf9e37f922a2b0a48cff23f1aa94ec8e8e039e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R6c7e5ae1220faee4564cd751fa6c94f7404ddc27

7 years agoARM: tegra: power: Workaround PMD corruption by cpu_resume_mmu
Scott Williams [Wed, 10 Aug 2011 01:19:47 +0000]
ARM: tegra: power: Workaround PMD corruption by cpu_resume_mmu

The common ARM CPU state suspend/resume code does not work with
and external L2 cache controller (like a PL310) enabled. This
change fixes corruption of the current PMD by the MMU resume code.

cpu_resume_mmu modifies the currently active page tables to add
a flat (VA==PA) section mapping of cpu_resume_turn_mmu_on to
handle MMU off-to-on transition. It turns off the L1 data cache
but it knows nothing of the L2 cache. Since page table walks are
L2 cacheable, other CPUs in the system can pick up the corrupted
PMD which will eventually result in a kernel panic.

The workaround for this is to modify push_ctx_regs to save the
current TTB0 and CONTEXID registers in the CPU register context
and switch to the private tegra_pgd before saving the rest of the
CPU context. The tegra_pgd already has a flat mapping for the
code in question, so it can't be damaged by the actions of
cpu_resume_mmu. Likewise, pop_ctx_regs is modified to restore
the actual TTB0 and CONTEXTID registers when restoring the CPU
registers.

Change-Id: Ided2b31cbea0b0abb934e64cf056e85e1a3f06ae
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R3f6ca9c63752430395fdf8375b82794abc9776af

7 years agoARM: tegra2: power: Don't flush D-cache on aborted LP2 with L2
Scott Williams [Wed, 10 Aug 2011 01:14:11 +0000]
ARM: tegra2: power: Don't flush D-cache on aborted LP2 with L2

Don't try to flush the L1 D-cache for an aborted LP2 on the
secondary CPU if the L2 cache is enabled. The L1 cache will have
already been flushed and disabled by the suspend-side code.

Change-Id: If6fc7bd0f7d630e6cdcda6824411503f346c5405
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc50e525a320986432d2b125f82f846f94f605cc3

7 years agoARM: tegra: power: Map the CPU context page to tegra_pgd
Scott Williams [Wed, 10 Aug 2011 01:10:12 +0000]
ARM: tegra: power: Map the CPU context page to tegra_pgd

Add a mapping of the page used to save the CPU context to the
private pgd used during MMU shutdown.

Change-Id: I10ef282ff15ff5ee8469fcaa3637bcb0fb39ba4d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R837a2eb005ad93ef206153b120e972ee65383b65

7 years agoARM: tegra: power: Consolidate PM_SLEEP conditionals
Scott Williams [Wed, 10 Aug 2011 01:05:11 +0000]
ARM: tegra: power: Consolidate PM_SLEEP conditionals

Change-Id: If8f8868d929ec5bebe7c0083e03af504c7a6af11
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rf382a5bf2c7587ad496f2a88deaff75cb609f91c

7 years agoARM: tegra: power: Conditionalize diagnostic register save/restore
Scott Williams [Wed, 10 Aug 2011 01:01:49 +0000]
ARM: tegra: power: Conditionalize diagnostic register save/restore

Change-Id: I540d7272d585331da0241e7878dbb35557f0bb99
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R59fe634cc803ba2c9bb7916046aff5f92120f5c3

7 years agoARM: tegra: power: Fix build errors when DVFS is enabled
Scott Williams [Mon, 8 Aug 2011 20:41:53 +0000]
ARM: tegra: power: Fix build errors when DVFS is enabled

Change-Id: Icc37a1ac4fe1af3d08e579faf35ccb4ab1db1b1c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R786d091cccb765acb8d89acd59017ae993b78733

7 years agoARM: tegra: Fix mutex in atomic context when updating TWD freq
Scott Williams [Sat, 6 Aug 2011 01:16:48 +0000]
ARM: tegra: Fix mutex in atomic context when updating TWD freq

The CPU frequency change notifer runs in an atomic context but
obtaining the current CPU frequency requires taking a mutex because
updating the CPU frequency involves the regulator. Instead of
directly parenting the TWD clock on the CPU clock, make the TWD
a "detached child" of the CPU clock whose rate is updated whenever
the CPU frequency changes.

Change-Id: I49e15f85f269fb3ed0bcaee36ff739b4f064d6b8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7aa10f2576752390464586bc629c972802beb989

7 years agoARM: tegra: power: Rename variables for consistency
Scott Williams [Fri, 5 Aug 2011 01:41:41 +0000]
ARM: tegra: power: Rename variables for consistency

Rename Tegra3 CPU idle handler variables to be the same as their
Tegra2 counterparts for consistency.

Change-Id: I49a03182ff5a15d34847b3837f681ca842dcf643
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc71d7d71bebb197c983180429f24de7708d8dfea

7 years agoARM: tegra: power: Fix Tegra2 secondary CPU LP2 time calculation
Scott Williams [Fri, 5 Aug 2011 01:35:45 +0000]
ARM: tegra: power: Fix Tegra2 secondary CPU LP2 time calculation

CPU 0 must wake up before CPU 1 therefore CPU 0 must be awake by
the minimum of its or CPU 1's absolute wakeup time. However, the
the CPU idle request time is a duration not an absolute time.
Change the LP2 sleep time calculation to use an absolute "must
be away by" time.

Change-Id: Ia73dcbe071f81d0bd9fc6c5d860837e606575a8c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R138e6d4ae652932607f7dd411be3aa89ee53e34c

7 years agoARM: tegra: power: Save CPU context to non-cacheable stack
Scott Williams [Thu, 4 Aug 2011 20:32:10 +0000]
ARM: tegra: power: Save CPU context to non-cacheable stack

The standard cpu_suspend does not work if there is an exernal
L2 cache in the system individual CPUs are suspending without
shutting down the whole CPU complex. As a workaround for this
problem, we must save the CPU context to a non-cacheable region
of memory.

Change-Id: I2fffbc77ed4f17fe9710307aaacda80836bacee8
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R7328c032c2a13775aa09432e119ea845ded85930

7 years agoARM: tegra: power: Add stack frame debug checks
Scott Williams [Thu, 4 Aug 2011 05:18:31 +0000]
ARM: tegra: power: Add stack frame debug checks

Tag the stack frame created by the CPU register context push
macro with a magic number and validate that magic number in
the register context pop macro to ensure that the stack
remains balanced and uncorrupted.

Change-Id: I6aa876496e30e6e70c0c60800c1b35d217595153
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R78eba17c256f03bdd6457ca3ebb1ecdba5632e60

7 years agoARM: tegra: power: Define push/pop context register macros
Scott Williams [Thu, 4 Aug 2011 04:44:21 +0000]
ARM: tegra: power: Define push/pop context register macros

Define macros to ensure that the behavior of push/pop of the
context regsiter set is consistent across all callers.

Change-Id: If2e68764e9755979a205a57543b30438e9b7ff96
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rb8f4984258e71c318e93fc709b18d1efdf5b2cc4

7 years agoARM: tegra: power: Use uniform save/restore register set
Scott Williams [Thu, 4 Aug 2011 04:38:01 +0000]
ARM: tegra: power: Use uniform save/restore register set

Modify the register usage of tegra_cpu_save so that the same set
of registers is saved to and restored from the stack.

Change-Id: I9a0e3ce80e0e1d4b47cbb984fb732fd612bf2c16
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R89e119278eb1d8f10f3c4e1c3c3203628de37a59

7 years agoARM: tegra: power: Use standard definitions for SCTLR
Scott Williams [Thu, 4 Aug 2011 03:36:21 +0000]
ARM: tegra: power: Use standard definitions for SCTLR

Change-Id: Ie2f619df4e5bff06960dcaa910a39d4cff78b879
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Ra75a8dba9e8f0fa57081a3fed9b3ef743b3c8796

7 years agoARM: tegra: power: Consolidate CPU context save and SMP exit
Scott Williams [Thu, 4 Aug 2011 02:07:51 +0000]
ARM: tegra: power: Consolidate CPU context save and SMP exit

Every call to tegra_cpu_save is always followed by a call to
tegra_cpu_exit_coherency. Simplify the callers of tegra_cpu_save
by folding the CPU context save functionality of cpu_suspend and
the coherency exit functionality into a single function called
tegra_cpu_suspend.

Change-Id: Ia71a663b2971685712d5b8a2b7e8b44fe1526f40
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R36c0c5f44608d0c099d928e19e36af2e7ba061d8

7 years agoARM: tegra: power: Clear cache/TLB forwarding when exiting SMP
Scott Williams [Thu, 4 Aug 2011 02:21:48 +0000]
ARM: tegra: power: Clear cache/TLB forwarding when exiting SMP

When exiting SMP coherency, clear cache and TLB operation forwarding.

Change-Id: Id91331b60eb40e47591fb0282820e31b14e027d5
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R4d7697d029fa1b9d30ff612fad940f1c65b3b376

7 years agoARM: tegra: power: Add SMP coherency exit macro
Scott Williams [Thu, 4 Aug 2011 00:33:37 +0000]
ARM: tegra: power: Add SMP coherency exit macro

Define the SMP coherency exit code as a macro to allow it to be
inlined in assembly code that needs to control its register usage.

Change-Id: If5bd01241a92eb471cf59b4fc8445934fd4932b1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R921ed4d46431115d164f73bacac16a68a9d32b0a

7 years agoARM: tegra: power: Delete obsolete function
Scott Williams [Thu, 4 Aug 2011 00:08:54 +0000]
ARM: tegra: power: Delete obsolete function

Deleted tegra3_sleep_cpu which is never called by anything.

Change-Id: I59a737e92ed8bec222cec65252cc19592e171fd6
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R1fabb1b9a728f1d4ff99643b4d31cfe7292c260d

7 years agoARM: tegra: Use common coherency exit function for Tegra2
Scott Williams [Wed, 3 Aug 2011 15:59:34 +0000]
ARM: tegra: Use common coherency exit function for Tegra2

Change-Id: Ibbc9c2a38fb654e24b1edb4ee7bbcaf285bf0f7d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R9ff092cf658b71d8f79ef3901bd5067d18548e69

7 years agoARM: tegra: power: Fix suspend pgd identity mapping
Scott Williams [Tue, 2 Aug 2011 20:33:01 +0000]
ARM: tegra: power: Fix suspend pgd identity mapping

The RAM identity mapping in the suspend pgd was based upon the
characteristics of the Tegra2 address map and would not work for
Tegra3. Change the mapping so that it's independent of the physical
address map characteristics.

Change-Id: Ib8f67c169f6b0988e88a4ef7616dfd48e66754ac
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R399b9624e8f25637538273642059e8d0719badf5

7 years agoARM: tegra: power: Allocate non-cacheable page for CPU context
Scott Williams [Tue, 2 Aug 2011 03:38:04 +0000]
ARM: tegra: power: Allocate non-cacheable page for CPU context

The standard cpu_suspend() mechanism doesn't work if there's an L2
cache controller like a PL310 in the system because there's no
effective way to flush the saved CPU context out to the L3 memory
system. Allocate a page of non-cacheable memory to hold the CPU
context. This save area will be utilized in a subsequent change.

Change-Id: I1e3bd60bd0bd19c1010905ef65ea0a8597ad6654
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R00d69f8cab6992ed729c1f6ef67fd38c999c3a5b

7 years agoARM: tegra: power: Put power functions under CONFIG_PM_SLEEP
Scott Williams [Tue, 2 Aug 2011 02:22:02 +0000]
ARM: tegra: power: Put power functions under CONFIG_PM_SLEEP

Place additional functions that are invoked only by code under
CONFIG_PM_SLEEP conditionals under CONFIG_PM_SLEEP conditionals
also.

Change-Id: I224ae07b9031038474b922422422a4feafcd94f1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R65b81ec60f59ae981fd668ad8354b14b8b4c83b9

7 years agoARM: tegra: power: Reorganize CPU idle code
Scott Williams [Sat, 30 Jul 2011 00:45:21 +0000]
ARM: tegra: power: Reorganize CPU idle code

Change-Id: I57653997b7dc059f74e0722b9ea298f3d8a38095
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rc8638db0a47faf6fe25976375542fb6eb6326c4c

7 years agoARM: tegra: power: Disable power management if pgd alloc fails
Scott Williams [Sat, 30 Jul 2011 00:38:11 +0000]
ARM: tegra: power: Disable power management if pgd alloc fails

Disable power management functions if we're unable to obtain memory
for our the suspend pgd.

Change-Id: If7900535ea05df9441c0b82ccb9152961ea9e12b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R4b616bb53552d2dd8b9da39ca9bc11ad10825f54

7 years agoHACK keep tegra_uart_platform_data for integrations
Dan Willemsen [Sat, 6 Aug 2011 00:20:18 +0000]
HACK keep tegra_uart_platform_data for integrations

Rebase-Id: Rfb3d85a09b37cabbaae8d5ca9457b3e7ec4d523a

7 years agoARM: Tegra: Make T20's MACH_* depend on ARCH_TEGRA_2x_SOC
Stephen Warren [Tue, 26 Jul 2011 19:43:55 +0000]
ARM: Tegra: Make T20's MACH_* depend on ARCH_TEGRA_2x_SOC

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Rebase-Id: Rf4c2fea470f0190a2fce7cd0e1d5aaee2eac9649

7 years agoARM: tegra: Cardhu/Ventana only select ..._TEGRA_WM8903 if SND_SOC
Dan Willemsen [Fri, 5 Aug 2011 21:23:17 +0000]
ARM: tegra: Cardhu/Ventana only select ..._TEGRA_WM8903 if SND_SOC

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rfe31ce305b8a1ba26507ae7770f9efac2d4fef2e

7 years agoARM: Tegra: ALSA support for Cardhu
Stephen Warren [Tue, 26 Jul 2011 20:08:31 +0000]
ARM: Tegra: ALSA support for Cardhu

Define GPIO names, platform data, and platform devices for audio support
on Cardhu.

Configure/register the WM8903 IRQ gpio.

Don't statically configure most audio-related clocks; the ASoC utils code
sets this all up now.

Signed-off-by: Stephen Warren <swarren@nvidia.com>

Rebase-Id: R77ca15a61948eefd790d97cbfe1470d2687c5b73

7 years agovideo: tegra: nvmap: Fix formatting
Dan Willemsen [Thu, 4 Aug 2011 21:04:38 +0000]
video: tegra: nvmap: Fix formatting

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R40af26da1b703abcca7c96c8fe9ca3f8a42b367d

7 years agoARM: tegra: Limit ahb.c to Tegra2
Dan Willemsen [Thu, 4 Aug 2011 21:00:48 +0000]
ARM: tegra: Limit ahb.c to Tegra2

Change-Id: Ia9a67a2ce2c437b115efe7d1f5d69da481208d35
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R866af3fffbba37a2efac84ecfcbd8979d3c3b745

7 years agoARM: tegra: power: cluster control requires CONFIG_PM_SLEEP
Scott Williams [Fri, 29 Jul 2011 23:26:10 +0000]
ARM: tegra: power: cluster control requires CONFIG_PM_SLEEP

Change-Id: I6d395efbd8a83d867e6ac645e232ff95538b7f91
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R08fc23af26e1e1b9daf3de235fdd7df8419013de

7 years agoARM: tegra: power: Add debug checks for LP2 entry/exit
Scott Williams [Fri, 29 Jul 2011 01:31:21 +0000]
ARM: tegra: power: Add debug checks for LP2 entry/exit

Add debug traps for recursive attempts to enter or exit LP2 state.

Change-Id: I7da05774c90a4fd5b9f2369e801c5b447024698f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb74239b3fbabf80cf7548c6f5958b0c540ae6b62

7 years agoARM: tegra: power: Clean up stack pointer handling
Scott Williams [Thu, 28 Jul 2011 04:30:14 +0000]
ARM: tegra: power: Clean up stack pointer handling

Clean up some rather fragile manipulation of the stack pointer in
the CPU suspend code. It's all unnecssary except in one case where
Tegra2 can abort a suspend because of activity on the other CPU.

Change-Id: Ic872364c5abd58f704b2afeeae4d8722f127d3bb
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5873dd120df2e98cc5bfcc74f86ebea6cc10f9b2

7 years agoARM: tegra: power: Fix Tegra2 LP2 mode
Scott Williams [Thu, 28 Jul 2011 04:02:36 +0000]
ARM: tegra: power: Fix Tegra2 LP2 mode

All CPUs are not created equal. CPU0 must be the one to perform
the CPU complex suspend actions. CPU complex power gating and rail
gating cannot be triggered from CPU1. The Linux 2.6.39 port for
Tegra2 violates this hardware restriction. While it may have
appeared that the system was entering LP2 state, when entered
on CPU1, essentially all that happened was a WFI with no CPU
complex power gating and no CPU rail gating.

Change-Id: Ie754520264fe8de1b95f523d6575914bf77e747f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R66e19457bc55bcd84124e3a4e23beae7b4ee707c

7 years agoARM: tegra: Handle uniprocessor all CPUs booted status
Scott Williams [Thu, 28 Jul 2011 03:57:45 +0000]
ARM: tegra: Handle uniprocessor all CPUs booted status

For CONFIG_SMP systems that report only a single CPU available,
platform_smp_prepare_cpus() will never get called. Make sure that
tegra_all_cpus_booted is properly set in this case.

Change-Id: I6bf30be02c0b692f0578eb9a19062bcb562c1892
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rb800c15e27cff51a091e8e704610ed72572b4b6e

7 years agoARM: tegra: Fix uniprocessor reset handler initialization
Scott Williams [Thu, 28 Jul 2011 03:10:06 +0000]
ARM: tegra: Fix uniprocessor reset handler initialization

- For CONFIG_SMP kernels on systems that only report one CPU available,
  there is never a call to platform_smp_prepare_cpus() which means
  the reset handler would not get initialized. Invoke the reset handler
  initialization from smp_init_cpus() if there is only one CPU.
- For non-CONFIG_SMP kernels, the call to initialize the reset handler
  got accidentally dropped in the port to Linux 2.6.39. Invoke the
  reset handler initiazation from tegra_init_early() in this case.

Change-Id: I782faf84c89d4285aac26bfccb829f27878029de
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R9b35221571885a1620e0d7e19880b05a18c97233

7 years agoARM: tegra: power: CPU complex must be suspended on CPU0
Scott Williams [Tue, 26 Jul 2011 01:31:19 +0000]
ARM: tegra: power: CPU complex must be suspended on CPU0

All CPUs are not created equal. CPU0 must be the one to perform the
CPU complex rail gating action and as such must always be the last
CPU taken down.

Change-Id: I92d1c1c29305d2bf35a15baa43a6d299806482b7
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R5ba8fbba2771a2458fcf27d9d49c964ffbe53c88

7 years agoARM: tegra: power: Add LP2 in idle support for secondary CPUs
Scott Williams [Mon, 25 Jul 2011 20:24:13 +0000]
ARM: tegra: power: Add LP2 in idle support for secondary CPUs

Change-Id: Ie557f4429d65fb4cf701935b7ea6b1190140a878
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rf03d13e909ff708671ab09077d1de590182b9917

7 years agoARM: tegra: power: Split CPU context save and coherency exit
Scott Williams [Mon, 25 Jul 2011 21:55:25 +0000]
ARM: tegra: power: Split CPU context save and coherency exit

Separate the CPU context save and CPU coherency exit into separate
functions.

Change-Id: I7c5376677e293342b02b5bebdef6be2610522936
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R17eb40d551e797448410cf6220dfba122faa702d

7 years agoARM: tegra: power: Calculate address of IRAM LP2 mask once
Scott Williams [Mon, 25 Jul 2011 19:56:29 +0000]
ARM: tegra: power: Calculate address of IRAM LP2 mask once

Perform the calcuation of the address of the IRAM copy of the LP2
mask only once because run-time evaluation of it's IO_ADDRESS()
is a rather lengthly computation whose value never changes.

Change-Id: I8456fa3eb719dcf4f42c360196349177b8907fd9
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R429d76f341410455883ad7d9e28ff66a44eddb98

7 years agoARM: tegra: timer: Save TWD registers on secondary CPU LP2
Scott Williams [Fri, 22 Jul 2011 22:00:22 +0000]
ARM: tegra: timer: Save TWD registers on secondary CPU LP2

Change-Id: I0ca5186fd833913b79abf2a7dbddc528d547acc6
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Simplify, remove unnecessary macros
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R686b57e37db12361f3c5054500c74337de6fd5a6

7 years agoARM: tegra: power: Save TWD registers on cluster transitions
Scott Williams [Fri, 22 Jul 2011 01:24:34 +0000]
ARM: tegra: power: Save TWD registers on cluster transitions

The ARM timer/watchdog (TWD) registers do not need saving on LP2
transitions resulting from real idle events. They do still need
saving/restoring on transitions resulting from cluster control
operations.

Change-Id: I459b25b98c256a52a2e9e68fb63dbf2681e90b07
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R3c7c0cae8b847af6355fa1fa0b8bf5bf1e1efef5

7 years agoARM: tegra: power: Add TWD context save/restore
Scott Williams [Thu, 21 Jul 2011 01:13:59 +0000]
ARM: tegra: power: Add TWD context save/restore

Change-Id: I629f77041ce444dfff32b563795573174afea3a1
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R7a21e91127b44461d219a8bfd388f99ba7a72b53

7 years agoARM: tegra3: power: Add LP2 power mode support for CPU 0
Scott Williams [Thu, 21 Jul 2011 23:06:08 +0000]
ARM: tegra3: power: Add LP2 power mode support for CPU 0

Add support for forced Tegra3 LP2 low power mode on the boot processor
(CPU 0) via the cluster control interface when all others are offline.
Switching to the LP CPU mode is also enabled with this change.

LP2 in idle and LP2 mode on the secondary processors is not yet
supported.

Change-Id: Icb898729f093be5e006c413f701532dd45228687
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8

7 years agoARM: tegra: cardhu: Disable power management features
Scott Williams [Fri, 22 Jul 2011 18:58:27 +0000]
ARM: tegra: cardhu: Disable power management features

Tegra3 power management features have not been fully ported to
Linux 2.6.39 yet. Disable them temporarily.

Change-Id: Id9e1ebcab5f665845e6d1b685364f9cea9fe7329
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rd813fa7d2be0ae8eec44c02834e21c2a47b5a846

7 years agoARM: tegra: power: Clean up cluster control definitions
Scott Williams [Thu, 21 Jul 2011 22:46:01 +0000]
ARM: tegra: power: Clean up cluster control definitions

Reduce the complexity of the cluster control compile-time conditionals.
Also disable DEBUG_CLUSTER_SWITCH because it invokes clock code that
takes a mutex when taking of a mutex is disallowed.

Change-Id: I9b614d4b0189fbb01d0b7f8af7053c7586d9515b
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R412820dc2fd9f0c9cc7b1e3ad7ead7e2e68a0ff3

7 years agoARM: tegra: power: Fix CPU complex suspend/resume
Scott Williams [Thu, 21 Jul 2011 21:29:58 +0000]
ARM: tegra: power: Fix CPU complex suspend/resume

- Invoke cpu_pm_enter()/cpu_pm_exit() to save/restore the GIC
  processor interface registers for the last processor standing from
  the cluster control interface.
- Disable the GIC processor interface on the last processor standing
  before shutting down the CPU complex so that wakeup interrupts get
  routed from the legacy interrupt controller to the flow controller.
- For Tegra3 enable GIC pass-through mode to prevent WFI failures.

Change-Id: Ia866b17bef47fc8e9e75d4e353394b2d1a09259c
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R249fb53a2622218a7128646d68d8a3552268b4f1

7 years agoARM: tegra: power: Fix incorrect flow controller programming
Scott Williams [Thu, 21 Jul 2011 21:09:39 +0000]
ARM: tegra: power: Fix incorrect flow controller programming

Errors and invalid assumptions about how the flow controller should
be programmed were introduced in the port to Linux 2.6.39.

- Do not touch the flow controller HALT_EVENTS register for any of
  the secondary CPUs in suspend_cpu_complex(). Doing so can cause the
  flow controller state machine to prematurely abort resulting in fatal
  errors when power gating the CPU complex.
- Do not touch the flow controller CSR register for any of the
  secondary CPUs in restore_cpu_complex(). Doing so can cause the
  flow controller state machine to prematurely abort resulting in
  the secondary CPUs waking up before they're supposed to.
- suspend_cpu_complex() and restore_cpu_complex() can only be invoked
  from CPU 0. The hardware does not allow the CPU complex to be
  suspended from any other CPU.

Change-Id: I89546bf53f8f6f12c0e62ce49fc99a46244fa57f
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rf61122cb730d852179d8e2d9e667ae7c65b09c58

7 years agoARM: tegra: power: Fix TEGRA_SUSPEND_NONE handling
Scott Williams [Thu, 21 Jul 2011 20:41:18 +0000]
ARM: tegra: power: Fix TEGRA_SUSPEND_NONE handling

- Do not assert in tegra_pm_set() if the platform suspend mode is
  set to TEGRA_SUSPEND_NONE. Just return.
- Do not override the platform suspend mode to a deeper power saving
  mode if the SDRAM refresh context save area cannot be obtained.

Change-Id: I1ebceef715f9175b8db25af3df28c48582ec0815
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Rfe888ac904de11cb5a63475dc95ab736a39f5c4b

7 years agoARM: tegra: Add Tegra 3 CPU hotplug support
Scott Williams [Thu, 21 Jul 2011 20:20:20 +0000]
ARM: tegra: Add Tegra 3 CPU hotplug support

Change-Id: Ie43f4efdf884a916c6bc9737157091c35dc44501
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R1f023651504a7d336f7e98921f6372bee0aa1341

7 years agoARM: tegra: power: Consolidate power management flags
Scott Williams [Thu, 21 Jul 2011 19:24:05 +0000]
ARM: tegra: power: Consolidate power management flags

Consolidate all of the power management control flags in one
header and adjust the values of the software flags so that they
do not conflict with the values of the hardware flags.

Change-Id: I7971d274946d84dcc50bd9d9e0190091ebbefa2e
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R29d2420a74f977c16f73b1abd9ca7470695a53f4

7 years agoARM: tegra: Rename tegra<n>_sleep_reset
Scott Williams [Mon, 25 Jul 2011 22:50:36 +0000]
ARM: tegra: Rename tegra<n>_sleep_reset

Rename tegra<n>_sleep_reset to tegra<n>_hotplug_shutdown since that is
more descriptive of their actual function.

Change-Id: I411e2474bd35a799d5367a182809d17933238612
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
DW: Split into logical changes
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R72bf50004ab3fcdde5485b84b7ba008247d1bf4c

7 years agoARM: tegra: power: Align MMU shutdown code to L1 cache line
Scott Williams [Thu, 21 Jul 2011 19:16:18 +0000]
ARM: tegra: power: Align MMU shutdown code to L1 cache line

The MMU shutdown code must be aligned to an L1 cache line boundary.

Change-Id: Ib6c976470983b7f69b45e720104fc65cae54e162
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R305325117ba1debc8d112b4c3596c158df98d75e

7 years agoARM: tegra: Remove obsolete files
Scott Williams [Mon, 25 Jul 2011 22:39:50 +0000]
ARM: tegra: Remove obsolete files

Change-Id: I92b35e1a9966023be98e532de8f89b6b0497a005
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: Raf0dfd3a5ae967563885b05c2e8b03916439dfff

7 years agoARM: tegra: clock: Don't require DVFS for setting LP CPU clock
Scott Williams [Thu, 21 Jul 2011 18:32:33 +0000]
ARM: tegra: clock: Don't require DVFS for setting LP CPU clock

If DVFS tables do not exist, assume the CPU power rail is at it's
nominal voltage and permit the rate for the LP mode clock to be
set normally.

Change-Id: I29f592ab1f1b44ed07c187f48cd7eb9de1b6db3d
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>

Rebase-Id: R14a4fc8e7c53070afdf29ca9e0c7bfb2269a380d