7 years agoARM: tegra: Use cbus clocks for power gating
Terje Bergstrom [Wed, 3 Oct 2012 07:09:14 +0000]
ARM: tegra: Use cbus clocks for power gating

Use cbus clocks instead of physical clocks. This allows cbus to
adjust PLL correctly.

Change-Id: I609129bf5af8cdc906409f89bfc1b3fc89c582cf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/160515
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

7 years agoARM: tegra: pluto: Enable pwm based cl dvfs
Pradeep Goudagunta [Wed, 7 Nov 2012 08:24:28 +0000]
ARM: tegra: pluto: Enable pwm based cl dvfs

Enable pwm based cl dvfs for SMPS6, modem voltage rail.

Bug 1058480

Change-Id: I2e110127106f57a8337735a67eaf5e9b9a19d00e
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/159833
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agomfd: palmas: pwm based cl dvfs support
Pradeep Goudagunta [Wed, 7 Nov 2012 08:16:11 +0000]
mfd: palmas: pwm based cl dvfs support

SMPS12 and SMPS6 are capable of PWM based cl dvfs.

Bug 1058480

Change-Id: Ib000300ac508b471b9ebe698c603c93129f0675e
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/159832
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Neil Patel <neilp@nvidia.com>

7 years agoarm: tegra: usb_phy: Fix remote wakeup resume
Abhishek Shukla [Tue, 23 Oct 2012 11:09:36 +0000]
arm: tegra: usb_phy: Fix remote wakeup resume

FPR bit was getting cleared before RUN bit
is getting set by ehci_bus_resume. If there
are prints in resume code before RUN  bit
is set, device can go to suspend state from
idle. To avoid this, setting RUN bit in
pre_resume after remote wakeup is detected.

Bug 1159691

Change-Id: I2c0a6348eb8df7eb5d668b5e6b9400f2f30a8b7a
Signed-off-by: Abhishek Shukla <abhisheks@nvidia.com>
Reviewed-on: http://git-master/r/146892
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agovideo: tegra: dc: remove enable/disable in set_par
Jon Mayo [Wed, 7 Nov 2012 22:41:40 +0000]
video: tegra: dc: remove enable/disable in set_par

Remove a work around that is no longer necessary. This fixes a strobing display
issue when scrolling or double buffering.

Bug 1161314

Change-Id: I7f74c089461b01c2f2933e14094e3190cef4726a
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/162135
Reviewed-by: Automatic_Commit_Validation_User

7 years agoARM: tegra: soctherm: suspend/resume functionality
Joshua Primero [Thu, 25 Oct 2012 22:03:28 +0000]
ARM: tegra: soctherm: suspend/resume functionality

Added suspend/resume functionality to soctherm.

Change-Id: I500b9483bf947b110da1d659688c661363f8b975
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/162123
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

7 years agovideo: tegra: dc: support either DC as the primary
Jon Mayo [Tue, 6 Nov 2012 23:01:39 +0000]
video: tegra: dc: support either DC as the primary

Allow either DC to be used as the primary display.

Bug 1003636

Change-Id: I179462aaa86c4ae3166d3318ef440ad53de6994d
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/162118
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoAdd nvdumper kernel module to monitor reboots
Colin Patrick McCabe [Wed, 7 Nov 2012 05:49:23 +0000]
Add nvdumper kernel module to monitor reboots

The nvdumper kernel module tracks whether the system has been rebooted
cleanly.  It does this by writing 'dirty' to a fixed physical memory
address when the kernel starts.  Then, on a planned reboot, we write
'clean' to this location.  The bootloader can then examine this location
and see if the reboot was dirty or clean.  It will dump the contents of
memory after a dirty reboot.

Bug 895895

Change-Id: I31e552da9bf6218cefb77f76f7488fcf9a9151b1
Signed-off-by: Joshua Cha <joshuac@nvidia.com>
Reviewed-on: http://git-master/r/161969
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agodrivers: power: max17042: check for battery detection
Syed Rafiuddin [Fri, 9 Nov 2012 05:04:16 +0000]
drivers: power: max17042: check for battery detection

check for the presence of battery using temperature

Change-Id: I0d1fe322825c6a9fa40ebd2a310e9c2566ab4273
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/161753
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agoARM: Tegra: Enable rcv_sel pinmux
Graziano Misuraca [Tue, 30 Oct 2012 18:24:43 +0000]
ARM: Tegra: Enable rcv_sel pinmux

Enable setting rcv_sel bit in DDC pinmux

Bug 1052024

Change-Id: If0b1025aea51b443943213488e57b7e68ea33451
Signed-off-by: Graziano Misuraca <gmisuraca@nvidia.com>
(cherry picked from commit 10a36664a2f4ee20b0eb62f1018c75a8f3d6dc6c)
Reviewed-on: http://git-master/r/161720
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agomfd: palmas: disable irq during suspend
Mallikarjun Kasoju [Thu, 8 Nov 2012 06:25:26 +0000]
mfd: palmas: disable irq during suspend

disable palmas irq during suspend and enable it in
resume

Bug 1159444

Change-Id: Iaab1cce124c1e833bc9412826eb59888c6f878fb
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/161719
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

7 years agovideo: tegra: host: Fix resource leak
Juha Tukkinen [Tue, 6 Nov 2012 11:45:04 +0000]
video: tegra: host: Fix resource leak

Free fw_name before exiting tsec_get_fw_name on failure.

Change-Id: I22719c49f48593d4df54fa3ee7bcf382f63b9c47
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/161608
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

7 years agovideo: tegra: host: Fix resource leak
Juha Tukkinen [Tue, 6 Nov 2012 11:18:05 +0000]
video: tegra: host: Fix resource leak

Free fw_name before exiting msenc_get_fw_name on failure.

Change-Id: I9b7917103657df3adf61887f28cc88372327c387
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/161598
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

7 years agoARM: tegra: usb_phy: Fix 2LS WAR removal
Suresh Mangipudi [Fri, 19 Oct 2012 08:50:05 +0000]
ARM: tegra: usb_phy: Fix 2LS WAR removal

Correct the sequence properly to remove the 2LS WAR.

Bug 1156346

Change-Id: I57ca4d57376f47e2485764ce614d1282455f7334
Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com>
Reviewed-on: http://git-master/r/161576
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoArm: Tegra: Roth: Support Roth platform
Pavan Kunapuli [Fri, 9 Nov 2012 09:00:59 +0000]
Arm: Tegra: Roth: Support Roth platform

Adding initial support for Roth platform
based on dalmore platform.

Populate power tree based on board design for roth.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

Bug 1169149

Change-Id: I2e14b464cc199c59a246500388fb1480866e10a3
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/160908
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoarm: tegra: power: update model parameters for VDD_CPU EDP
Diwakar Tundlam [Fri, 2 Nov 2012 00:45:06 +0000]
arm: tegra: power: update model parameters for VDD_CPU EDP

Bug 1167145

Change-Id: I485d86c42c90351b3207f5dbd1b7b5a8188b6e50
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/160721
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

7 years agoARM: tegra11x: remove redundant cache invalidation
Bo Yan [Thu, 1 Nov 2012 23:31:17 +0000]
ARM: tegra11x: remove redundant cache invalidation

the Cortex-A15 MPCore TRM says following are invalidated at reset:

   L1 instruction and data TLBs,
   L1 instructin and data caches,
   L2 unified TLB

in addition, following are invalidated at power on reset:

   L2 duplicate snoop tag RAM
   L2 prefetch stride queue RAM
   L2 unified cache RAM

So there is no need to invalidate cache after power ungating
and rail ungating. With this change, cache is no longer invalidated
explicitly after power ungating and rail ungating, but for CPU
hotplug, the cache is still being invalidated in ARMv7 setup code.

Change-Id: Icafbc0f20ff6c3b73670c7ce104cbbe03d3627c2
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/160712
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

7 years agoARM: tegra: soctherm: Fix many soctherm instances
Joshua Primero [Wed, 31 Oct 2012 01:19:03 +0000]
ARM: tegra: soctherm: Fix many soctherm instances

Fixed the bug where there were multiple soctherm instances
being initialized.

bug 1169070

Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Change-Id: I99dfa0d884c028dd5876652ae638fa0c2358dda6
Reviewed-on: http://git-master/r/160087
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: add tegra timer HZ config
Jin Qian [Tue, 30 Oct 2012 23:42:14 +0000]
ARM: add tegra timer HZ config

Change-Id: Ie556857bbc265429bcef6f47f352ab87ba333716
Signed-off-by: Jin Qian <jqian@nvidia.com>
Reviewed-on: http://git-master/r/160042
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: tegra: Set scratch1_eco register for memory dpd
Karthik Ramakrishnan [Sat, 13 Oct 2012 03:27:09 +0000]
ARM: tegra: Set scratch1_eco register for memory dpd

Setting the proper PMC register settings for memory in
suspend mode. This will be reset back on resume from lp0
in the bct.

Bug 1156167

Change-Id: I53fe808bbfa22a4c28fb24868f6787fe97a927bf
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
(cherry picked from commit 22752293180a7e03418ebaa2e1e4c94d103b0330)
Reviewed-on: http://git-master/r/160029
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: tegra: thermal: Update Tegra11 thermal throttle table
Diwakar Tundlam [Mon, 15 Oct 2012 21:01:35 +0000]
ARM: tegra: thermal: Update Tegra11 thermal throttle table

Bug 1058013

Change-Id: I0a68776f9fcd1c728b5e502973a2b0a4a70b1ba0
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/160002
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoarm: tegra: pluto: Use V_PULSE2 for PRISM proc.
Kevin Huang [Tue, 16 Oct 2012 05:50:08 +0000]
arm: tegra: pluto: Use V_PULSE2 for PRISM proc.

Bug 1156207

Change-Id: Ie0796f73bbfc6341198ce709f53ab5169645821f
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/159946
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoarm: tegra: pluto: enable pull-down for MDM1_COLD_BOOT
Steve Lin [Thu, 11 Oct 2012 18:03:19 +0000]
arm: tegra: pluto: enable pull-down for MDM1_COLD_BOOT

Enable pull-down for onboard modem cold boot GPIO.

Bug 1047414

Change-Id: I724827a4c33e96f18df022fba040bff10d75a6bd
Signed-off-by: Steve Lin <stlin@nvidia.com>
Reviewed-on: http://git-master/r/143781
(cherry picked from commit 8c79e4f2f12571cde694d1efa2c566ec2adc737d)
Reviewed-on: http://git-master/r/159153
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoarm: tegra: pci: Pass device info in regulator api
Jay Agarwal [Fri, 26 Oct 2012 06:14:01 +0000]
arm: tegra: pci: Pass device info in regulator api

Passing device information while getting the regu-
lator needed from k3.4 onwards.

Bug 1158690

Change-Id: I5552106334290bfcbd968ad3a131f33df1640ed3
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/147837
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

7 years agoARM: tegra: clocks: add frequency stats support for dual cbus
Shaoming Feng [Wed, 17 Oct 2012 03:09:17 +0000]
ARM: tegra: clocks: add frequency stats support for dual cbus

Add frequency stats support for c2bus and c3bus

Bug 1026583

Change-Id: I216f6d3eb1492782c681705637d66dae20f0a051
Signed-off-by: Shaoming Feng <shaomingf@nvidia.com>
Reviewed-on: http://git-master/r/147798
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: tegra: Document sysfs/debugfs LP2 node change
Bo Yan [Thu, 8 Nov 2012 19:26:16 +0000]
ARM: tegra: Document sysfs/debugfs LP2 node change

The name of one sysfs node for CPU power state control has been
changed from "lp2_in_idle" to "power_down_in_idle", the name of
the corresponding debugfs node has been changed from "lp2" to
"power_down_stats".

bug 1034196

Change-Id: I72daa591c4da783062f070bd32b4245eb6a350df
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/162462
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

7 years agoasoc: tegra: cs42l73: Add VSPIN to DAPM route
Rahul Mittal [Thu, 8 Nov 2012 06:03:50 +0000]
asoc: tegra: cs42l73: Add VSPIN to DAPM route

Workaround to get VSP recording working with Cirrus codec
Need to add proper DAPM route based on Cirrus inputs

Change-Id: I118f90b8561525979e23cfab011e99490d8f86a0
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/162260
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

7 years agovideo: tegra: dc: Select BACKLIGHT_CLASS_DEVICE
Robert Morell [Thu, 8 Nov 2012 00:33:05 +0000]
video: tegra: dc: Select BACKLIGHT_CLASS_DEVICE

We call into the bl subsystem for smartdimmer.  Building without it will
fail to link.

Bug 1047558

Change-Id: Ia6fb4b4e343509811e764ddaf9aface71f1d3269
Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/162168
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

7 years agoRevert "ARM: tegra: misc: pmureader driver"
Bo Yan [Wed, 7 Nov 2012 04:53:04 +0000]
Revert "ARM: tegra: misc: pmureader driver"

This reverts commit c1be13b9d1895756acb18054a2c14b595bfd6037.

Change-Id: I02c1683f98816a59fdce6932d115e45460a4cbc0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/161865
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit

7 years agomedia: video: tegra: ov9772: add 960x720 support
Phil Breczinski [Thu, 18 Oct 2012 01:36:22 +0000]
media: video: tegra: ov9772: add 960x720 support

Add support for 960x720 resolution to ov9772 driver. This
provides a 4:3 resolution in addition to the existing
16:9 resolution (720p).  Also includes support for
sensor-specific setmode frame delays (needed for driver
functionality).

Bug 1156852

Signed-off-by: Phil Breczinski <pbreczinski@nvidia.com>
Change-Id: I5dfb5f9aa131caae66f19ff975b879b4a54c2788
Reviewed-on: http://git-master/r/161830
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

7 years agoarm: tegra: iovmm: add tracing support for iovmm.
Krishna Reddy [Wed, 7 Nov 2012 00:46:27 +0000]
arm: tegra: iovmm: add tracing support for iovmm.

Change-Id: Iea1c776a66f35b10bb182220dab8db99ff5d4e64
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/161824
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>

7 years agoarm: tegra: panels: sd update bl after linear bl adjustments
Mitch Luban [Wed, 17 Oct 2012 17:47:29 +0000]
arm: tegra: panels: sd update bl after linear bl adjustments

Smart dimmer assumes a linear backlight. Therefore,
we should be applying smart dimmer backlight adjustments
after we do linear backlight correction.

Bug 1047558

Change-Id: I9a4705b752fddaf647ac566e9dc07636a2069dbc
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/161818
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agovideo: tegra: dc: allow r/w of cmu_enable sysfs node
Mitch Luban [Tue, 6 Nov 2012 23:37:21 +0000]
video: tegra: dc: allow r/w of cmu_enable sysfs node

Allows reading and writing to cmu_enable sysfs node.

Change-Id: I66e09c7bd9eb92e1125cd311608bd0ac3f6bf7bc
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/161795
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

7 years ago i2c: tegra: handle system reboot
Seshendra Gadagottu [Wed, 31 Oct 2012 01:18:26 +0000]
  i2c: tegra: handle system reboot

  When system reboot happens, if any i2c tranafers are
  active then they are cauing issue after reboot.

  To avoid this, shutdown handler is added and i2c driver
  is suspended before shutdown.

  Bug 1159422
  Bug 1164896

Change-Id: I50c7659b6051840f19a5b4dcff7544df649a7617
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/161724
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agoarm: tegra: isomgr: Fix deadlock issues.
Krishna Reddy [Mon, 5 Nov 2012 20:38:00 +0000]
arm: tegra: isomgr: Fix deadlock issues.

Fix the deadlock issues and avoid renegotiations
for the client, who is realizing.
Remove redundant variables.

Change-Id: Ie95a875682cc46caf3c7a8af407e6704732c5f36
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/161387
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>

7 years agohwmon: ina219: INA219 driver with more sysfs
Anshul Jain [Wed, 31 Oct 2012 18:44:20 +0000]
hwmon: ina219: INA219 driver with more sysfs

This new driver allows state change of the INA219 device using this sysds node:
To turn the ina219 device on,
echo 1 > /<i2c device path>/cur_state

To turn it off:
echo 0 > /<i2c device path>/cur_state

It has new sysfs nodes current2_input and power2_input that contains
current and power calculated using shunt resistor and voltage drop
across shunt resistor.

This driver is backward compatible with the old driver.

Bug 1160868

Change-Id: I5e05947e8e3b20a85f02188a48ea4441218e27a8
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/160070
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

7 years agoARM: tegra: dalmore: Change INA219 platform data
Anshul Jain [Wed, 31 Oct 2012 18:39:26 +0000]
ARM: tegra: dalmore: Change INA219 platform data

Changed INA219 platform data declaration to include values of
shunt registers, trigger config data and continuous
config data

Bug 1160868

Change-Id: I0bfaeaa217607272b48bdab256d1990ffa8e4da2
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/160068
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

7 years agoARM: tegra: cardhu: Changed INA219 platform data
Anshul Jain [Wed, 31 Oct 2012 18:36:44 +0000]
ARM: tegra: cardhu: Changed INA219 platform data

Changed INA219 platform data declaration to include values of
shunt resistor, continuous config data and trigger
config data

Bug 1160868

Change-Id: If7bcae81804b2807f11daae524bf66055ba3dd03
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/160067
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

7 years agohwmon: ina219: Update INA219 platform data
Anshul Jain [Wed, 31 Oct 2012 18:33:39 +0000]
hwmon: ina219: Update INA219 platform data

platform data structure now contains:
shunt resistor value
trigger config data
continuous config data

Bug 1160868

Change-Id: I5a4102745db2304fd7c5735981e1f70d182f32f6
Signed-off-by: Anshul Jain <anshulj@nvidia.com>
Reviewed-on: http://git-master/r/160065
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

7 years agotty: serial: tegra: Add stub runtime power management
Pradeep Goudagunta [Thu, 30 Aug 2012 15:42:47 +0000]
tty: serial: tegra: Add stub runtime power management

Add stub runtime_pm calls which go through the flow of enabling
and disabling but don't actually do anything with the device itself
as there's nothing useful we can do. This provides the core PM
framework with information about when the device is idle,
enabling chip wide power savings.

Bug 887359

Change-Id: I159f7798dbf141813ec1aa56ddb06cc8ca6595f4
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/159835
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agoarm: enable the control of CORENPDRQ bit
Liang Cheng [Tue, 23 Oct 2012 18:23:15 +0000]
arm: enable the control of CORENPDRQ bit

Transitions to suspend states cripple any ongoing JTAG
or coresight debug session. It can be prevented by
setting the bit CORENPDRQ in debug register DBGPRCR.

This change provides the control interface.

Bug 1029902

Change-Id: I1d82dfdce4136f3c9bd40f1a5d6dc619020fe6fc
Signed-off-by: Liang Cheng <licheng@nvidia.com>
Reviewed-on: http://git-master/r/147012
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

7 years agoarm: tegra: cardhu: print less alarming message
Naveen Kumar S [Mon, 15 Oct 2012 07:29:27 +0000]
arm: tegra: cardhu: print less alarming message

Print a less alarming message for cardhu boards which does not
have the mechanical fix for touch screen.

Bug 1049937
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Change-Id: I114b05fa513d3e03994498da7670d76ab247b52f
Reviewed-on: http://git-master/r/146374
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agomedia: video: tegra: Ad5816 power/gpio changes
Sudhir Vyas [Tue, 30 Oct 2012 13:01:39 +0000]
media: video: tegra: Ad5816 power/gpio changes

* Reorganise power sequence.
* Restructure focuser driver code.
* Add support for dalmore focuser.
* Make changes for image sharpness.
* Remove unnecessary code.

Bug 1156996
Bug 1157339

Change-Id: I578e6f586a66f751d35a6cc99fa5e7c229194ff9
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/160205
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prayas Mohanty <pmohanty@nvidia.com>
Reviewed-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

7 years agoARM: tegra: ad5816 power/gpio programming changes
Sudhir Vyas [Tue, 30 Oct 2012 13:33:30 +0000]
ARM: tegra: ad5816 power/gpio programming changes

* Reorganise power sequence.
* Add support for dalmore focuser.

Bug 1156996

Change-Id: I63a7b133f18922061f2bca96dbaf6f39172f3749
Signed-off-by: Sudhir Vyas <svyas@nvidia.com>
Reviewed-on: http://git-master/r/159880
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

7 years agomedia: video: tegra: add imx091 nvc driver
Wei Chen [Wed, 31 Oct 2012 19:55:01 +0000]
media: video: tegra: add imx091 nvc driver

add NVC framework driver for imx091

Bug 961418

Change-Id: I2a6c984eac956f62fefb36119d3868aadb800f26
Signed-off-by: Wei Chen <wechen@nvidia.com>
Reviewed-on: http://git-master/r/159376
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

7 years agodrivers: power: tps65090: detect battery from fuel-guage
Syed Rafiuddin [Tue, 6 Nov 2012 13:59:32 +0000]
drivers: power: tps65090: detect battery from fuel-guage

detect battery in tps65090 charger driver using
bq20z45 fuel-gauge driver.

Change-Id: Ic19a8f2459b3fecde2c7cf17b3d02b9e4b71c307
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/161649
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Daniel Solomon <daniels@nvidia.com>

7 years agovideo: tegra: host: Fix error handling of reg read
Juha Tukkinen [Tue, 6 Nov 2012 08:59:48 +0000]
video: tegra: host: Fix error handling of reg read

Check value of mem_sgt and check value of mem_dma only after setting it.

Change-Id: I949cbc3b3496e959234c8ad8c24d9f60250dcb1a
Signed-off-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-on: http://git-master/r/161566
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

7 years agoARM: tegra: dvfs: Add targeted predict millivolts APIs
Alex Frid [Sun, 4 Nov 2012 02:20:47 +0000]
ARM: tegra: dvfs: Add targeted predict millivolts APIs

Implemented voltage prediction APIs that return expected voltage
for clock domain if pll or dfll clock source is used, regardless
of the actual source selection (in addition to existing API that
predicts voltage for current clock source selection). Made sure
dfll mode can not be enabled for clock domains that do not have
dfll support.

Change-Id: I6bb0b7ab5fa60bc6633ebb207f3fc6e52844f770
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/161078
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>

7 years agoarm: tegra: dalmore: Add Sharp LQ101R1SX01 panel support
Animesh Kishore [Thu, 18 Oct 2012 12:29:03 +0000]
arm: tegra: dalmore: Add Sharp LQ101R1SX01 panel support

10.1" 2560x1600 panel.

Change-Id: I13a901114c908ce1b2d5e2025594def50f8d151c
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/160725
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agoarm: tegra: dalmore/pluto: add imx091 nvc driver
Wei Chen [Wed, 31 Oct 2012 19:49:23 +0000]
arm: tegra: dalmore/pluto: add imx091 nvc driver

add board file related changes for imx091 nvc driver

Bug 961418

Change-Id: Ibc179fbfac0e31642158990c0ac77c52076b5ace
Signed-off-by: Wei Chen <wechen@nvidia.com>
Reviewed-on: http://git-master/r/160285
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agoARM: tegra11: dvfs: Enable CPU and core voltage scaling
Alex Frid [Wed, 31 Oct 2012 08:27:57 +0000]
ARM: tegra11: dvfs: Enable CPU and core voltage scaling

Set configuration options for CPU and core voltage scaling.
No changes in current system behavior (VDD_CPU is scaled,
VDD_CORE is not scaled) is expected, since

- by default after boot DFLL is used as CPU clock source, and
CPU voltage is automatically scaled by CL-DVFS (this change only
enables scaling when/if PLL is used as a clock source)

- EMC DVFS tables requires nominal voltage for all rates, and
effectively prevents core voltage scaling, even if it is enabled

Change-Id: I9a1ee3a9dfce57521dd31f75d767763238be2acc
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/160138
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agoarm: tegra: tai: PRISM calibration for Tai
Mitch Luban [Thu, 30 Aug 2012 01:13:54 +0000]
arm: tegra: tai: PRISM calibration for Tai

Modified board-enterprise-panel.c file which
has calibration data for Tai panel.

Bug 1029936

Reviewed-on: http://git-master/r/130834
(cherry picked from commit 695665ca15c1b71786b1d98ac8193076de76db94)

Change-Id: I4cb164359bbb2b5047b1f48f470a0106e4cbda1a
Signed-off-by: Mitch Luban <mluban@nvidia.com>
Reviewed-on: http://git-master/r/133722
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agoRevert "arm: tegra: Separating out pmc from usb phy."
Ray Poudrier [Wed, 7 Nov 2012 19:49:00 +0000]
Revert "arm: tegra: Separating out pmc from usb phy."

This reverts commit c2958491e5a392be8f52824d59eabadb34b82060.

Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Change-Id: Idf66b95f1df2b732d319357ae4ea54f798cba82d
Reviewed-on: http://git-master/r/162093
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agoARM: tegra: Kconfig: NVMAP_CACHE_MAINT_BY_SET_WAYS for tegra11x
Hiroshi Doyu [Mon, 5 Nov 2012 11:46:07 +0000]
ARM: tegra: Kconfig: NVMAP_CACHE_MAINT_BY_SET_WAYS for tegra11x

Enable NVMAP_CACHE_MAINT_BY_SET_WAYS for tegra11x

Bug 1158336

Change-Id: I72ac4790c859cd464fafcde4f5da5c45d3d0abeb
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/161224
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agoarm: mm: cpa: Configurable cache_maint_{inner,outer}_threshold
Hiroshi Doyu [Mon, 5 Nov 2012 10:29:35 +0000]
arm: mm: cpa: Configurable cache_maint_{inner,outer}_threshold

Introduce configurable cache_maint_{inner,outer}_threshold via debugfs.

Bug 1158336

Change-Id: I7bb94adadbc41ff65dbd9992920c938df2449b06
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/161209
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

7 years agovideo: tegra: nvmap: Configurable cache_maint_{inner,outer}_threshold
Hiroshi Doyu [Mon, 5 Nov 2012 10:26:27 +0000]
video: tegra: nvmap: Configurable cache_maint_{inner,outer}_threshold

Introduce configurable cache_maint_{inner,outer}_threshold via debugfs.

Bug 1158336

Change-Id: I0b20d44ddf1e8e88954ac8fac7750b4e31959564
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/161208
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

7 years agovideo: tegra: nvmap: Clean up fast_cache_maint()
Hiroshi Doyu [Mon, 5 Nov 2012 10:37:14 +0000]
video: tegra: nvmap: Clean up fast_cache_maint()

Get rid of ifdef in a function for readability.

Bug 1158336

Change-Id: I31e9521f97dda91fecf523bcd49ff5b34db86e45
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/161207
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>

7 years agoARM: tegra11x: cpuidle: Remove LP2 references
Bo Yan [Tue, 30 Oct 2012 20:51:33 +0000]
ARM: tegra11x: cpuidle: Remove LP2 references

This change completely removes references to lp2 in cpuidle-t11x.c,
some related changes also affect cpuidle-t2.c, cpuidle-t3.c, and a
few other files.

bug 1034196

Change-Id: Ic2387bf614b39bd08ed4b2fc6e996f6fbf8306c0
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/160017
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

7 years agoinput: misc: Added sysfs to MAX77665 haptics driver
Sumit Sharma [Fri, 2 Nov 2012 04:07:34 +0000]
input: misc: Added sysfs to MAX77665 haptics driver

Added sysfs support to access and modify vibrator parameters

Change-Id: If372f0ce8df34c6b88a87056c4a214f63207d108
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/159817
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoarm: tegra: Added MAX77665 vibrator EDP data
Sumit Sharma [Fri, 2 Nov 2012 04:05:33 +0000]
arm: tegra: Added MAX77665 vibrator EDP data

Added EDP states in MAX77665 platform data for EDP implementation

Bug 1043388

Change-Id: Ieae95d196a43526084c11f3ee1063af57b6cc0e0
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/159816
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoinput: misc: Added EDP support in MAX77665 haptics driver
Sumit Sharma [Fri, 2 Nov 2012 04:02:54 +0000]
input: misc: Added EDP support in MAX77665 haptics driver

Registered vibrator EDP client
Implemented throttle callback function for EDP

Bug 1043388

Change-Id: I444251c6791baf112fdc86bed9aa02994236bde7
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/159815
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agoregmap: no need primary handler for nested irq
Yunfan Zhang [Sat, 8 Sep 2012 10:53:25 +0000]
regmap: no need primary handler for nested irq

The primary handler will NOT be called if the interrupt nests into
another interrupt thread. Remove it to avoid confusing.

Signed-off-by: Yunfan Zhang <yfzhang@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 81380739516730124067576c9cc9f2418be5bf36)

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: If06302d8d5806c00f34dd473b3ad937ebe626000
Reviewed-on: http://git-master/r/161555
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

7 years agoregmap: irq: Add mask invert flag for enable register
Xiaofan Tian [Thu, 30 Aug 2012 09:03:35 +0000]
regmap: irq: Add mask invert flag for enable register

Currently, regmap will write 1 to mask_base to mask
an interrupt and write 0 to unmask it.

But some chips do not have an interrupt mask register,
and only have interrupt enable register.
Then we should write 0 to disable interrupt and 1 to enable.

So add an mask_invert flag to handle this.
If it is not set, behavior is same as previous.
If set it to 1, the mask value will be inverted
before written to mask_base

Change-Id: I1c6875de71e0b9b9a89a23c1669638df4dfe541e
Signed-off-by: Xiaofan Tian <tianxf@marvell.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/161554
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

7 years agoregmap: irq: initialize all irqs to wake disabled
Stephen Warren [Wed, 1 Aug 2012 19:57:24 +0000]
regmap: irq: initialize all irqs to wake disabled

The kerneldoc for irq_set_irq_wake() says:

    Enable/disable power management wakeup mode, which is
    disabled by default.

regmap_irq_set_wake() clears bits to enable wake for an interrupt,
and sets bits to disable wake. Hence, we should set all bits in
wake_buf initially, to mirror the expected disabled state.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 40052ca0c243d101cfadd65936f60ef81df10b02)

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I2ae49a53467ea10eb01b37604a093c99720d4d37
Reviewed-on: http://git-master/r/161553
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Stephen Warren <swarren@nvidia.com>

7 years agoregmap: set MASK_ON_SUSPEND/SKIP_SET_WAKE if no wake_base
Stephen Warren [Wed, 1 Aug 2012 17:40:49 +0000]
regmap: set MASK_ON_SUSPEND/SKIP_SET_WAKE if no wake_base

If a regmap-irq chip has no wake base:

* There's no point calling .irq_set_wake, hence IRQCHIP_SKIP_SET_WAKE.

* If some IRQs in the chip are enabled for wake and some aren't, we
  should mask those interrupts that are not wake enabled, so that if
  they occur during suspend, the system is not awoken. Hence,
  IRQCHIP_MASK_ON_SUSPEND.

Note that IRQCHIP_MASK_ON_SUSPEND is handled by check_wakeup_irqs(),
which always iterates over every single interrupt in the system,
irrespective of whether an interrupt is a child of a controller whose
output interrupt has no wake-enabled inputs and hence is presumably
masked itself. Hence this change might cause interrupt unnecessary
masking operations and associated register I/O.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 685879f4b2036e58c1a0cdaaee2b155d3c965461)

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: Ibdb63f7574fa2017d1ba1f6f497c787f12f4e260
Reviewed-on: http://git-master/r/161552
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Stephen Warren <swarren@nvidia.com>

7 years agoregmap: name irq_chip based on regmap_irq_chip's name
Stephen Warren [Wed, 1 Aug 2012 17:40:48 +0000]
regmap: name irq_chip based on regmap_irq_chip's name

This is intended to give each irq_chip a useful name, rather than hard-
coding them all as "regmap".

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit ca142750f8ac3d01e45909e624ca783779894640)

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I1dfe76e23fe60b46b33bfc2ef048b8498ffc8ac6
Reviewed-on: http://git-master/r/161551
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Stephen Warren <swarren@nvidia.com>

7 years agoregmap: store irq_chip inside regmap_irq_chip_data
Stephen Warren [Wed, 1 Aug 2012 17:40:47 +0000]
regmap: store irq_chip inside regmap_irq_chip_data

This will allow later patches to adjust portions of the irq_chip
individually for each regmap_irq_chip that is created.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 7ac140ec426ed304237205be77f99eedfc1186b5)

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: Ib73deca2d8ca01d1ec49bdc94ebe20053c97981c
Reviewed-on: http://git-master/r/161550
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Stephen Warren <swarren@nvidia.com>

7 years agoregmap: irq: Only update mask bits when doing initial mask
Mark Brown [Wed, 1 Aug 2012 19:29:14 +0000]
regmap: irq: Only update mask bits when doing initial mask

Don't write the full register, it's possible there's bits other than the
masks in the same register which we shouldn't be changing.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
(cherry picked from commit 0eb46ad0c8d60943c1f46cef795fc537fbffd177)

Change-Id: I4e9f42422e961f9f842ab793227af7be25ca82cf
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/161549
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

7 years agoregmap: fix some error messages to take account of irq_reg_stride
Stephen Warren [Fri, 27 Jul 2012 19:01:54 +0000]
regmap: fix some error messages to take account of irq_reg_stride

A number of places in the code were printing error messages that included
the address of a register, but were not calculating the register address
in the same way as the access to the register. Use a temporary to solve
this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 16032624f511b2fac0671cba5e7da40aa7e73a66)

Change-Id: I60e982d5f9f2bc5aba7a8a72e45893e23c4bb0d4
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/161548
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Stephen Warren <swarren@nvidia.com>

7 years agoasoc: tegra: Rt5640: modify DAPM route table
Vijay Mali [Mon, 5 Nov 2012 14:45:04 +0000]
asoc: tegra: Rt5640: modify DAPM route table

a) register DAPM route table with snd_soc_card structure and
remove the open-coded DAPM add route calls.

b) set card.fully_routed flag to request the ASoC core calculated
unused codec pins, and call snd_soc_dapm_nc_pin() for them.

Bug 1054060

Change-Id: I512b6329bf1328eff172f40d4cc6b59c763f1323
Signed-off-by: Vijay Mali <vmali@nvidia.com>
Reviewed-on: http://git-master/r/161249
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>

7 years agoarm: tegra: sdhci: Set emmc voltage to 1.8V
rrajk [Mon, 5 Nov 2012 14:31:21 +0000]
arm: tegra: sdhci: Set emmc voltage to 1.8V

Set emmc supply interface voltage to 1.8V
Bug 1167307
Bug 1167312

Change-Id: I066fba8fe68b74d540a5803cc463ceef75cdfebb
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/161248
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agommc: tegra: Set proper emmc voltage
rrajk [Mon, 5 Nov 2012 14:23:47 +0000]
mmc: tegra: Set proper emmc voltage

Check interface supply voltage limit of emmc
and set it to 1.8V or 3.3V at resume
Bug 1167312
Bug 1167307

Change-Id: I2dda670ed9c270761f61eacb93233a7487894d84
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/161246
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agospi: tegra11: Set MODE bits before setting CS bit
Kunal Agrawal [Mon, 5 Nov 2012 09:25:15 +0000]
spi: tegra11: Set MODE bits before setting CS bit

Implemented change to set the MODE bits first and then
set CS and other bits of the command register.

Bug 1168218

Change-Id: I87bd94b8fac5821f11e575e53ee5694d6cad6d2c
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/161184
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agoARM: tegra: configs: Enable ROTH platform support
Pavan Kunapuli [Mon, 5 Nov 2012 08:47:53 +0000]
ARM: tegra: configs: Enable ROTH platform support

Change-Id: I2c56843f1fad3d962be811a4a83e0aae10dedaa5
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/161159
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: tegra11: dvfs: Update miscellaneous dvfs tables
Alex Frid [Thu, 25 Oct 2012 07:07:38 +0000]
ARM: tegra11: dvfs: Update miscellaneous dvfs tables

- Updated dvfs tables for SBUS (system clock), Host1x, and VI clocks
- Updated maximum limits for Host1x and MSELECT clocks
- Allowed only integer divisors for Host1x, VI, and MSELECT clocks

Change-Id: I4128cde767609a6bf4ccc3dd85a0f060feaa2dcb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147681
(cherry picked from commit 03a2546f2745dab8a8adda72777a062b7c113865)
Reviewed-on: http://git-master/r/161070
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: tegra11: clock: Do not allow 1:1.5 clock dividers ratio
Alex Frid [Thu, 25 Oct 2012 06:45:24 +0000]
ARM: tegra11: clock: Do not allow 1:1.5 clock dividers ratio

Change-Id: Iac26d1144b45247c3b5c70a47e26a1fba228b4d0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147680
(cherry picked from commit 723f73ae73cacb4274b2b671a8454f5741dae712)
Reviewed-on: http://git-master/r/161069
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: tegra11: dvfs: Update LP CPU dvfs table
Alex Frid [Thu, 25 Oct 2012 05:59:18 +0000]
ARM: tegra11: dvfs: Update LP CPU dvfs table

Change-Id: I47c5f2eae9ad0cbb1685c232308cc30bf7b2e6bf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147679
(cherry picked from commit ed29f1c25fe727023f8624536a78fbe45ab91689)
Reviewed-on: http://git-master/r/161068
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

7 years agoARM: tegra11: dvfs: Updated dvfs tables of c-bus modules
Alex Frid [Wed, 24 Oct 2012 22:06:36 +0000]
ARM: tegra11: dvfs: Updated dvfs tables of c-bus modules

Updated dvfs tables of c-bus modules per characterization.
Moved EPP from c3bus and c2bus, since it is closely matching 2d/3d
rates. As a result bus assignments:

c2bus = 2D, 3D, and EPP modules
c3bus = MSENC, SE, TESEC, and VDE modules

Change-Id: I78f6336a459f7959a18071c91c299e0247dbeb6f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147326
(cherry picked from commit 034654b06d2b9d089202a193a872d47f2367d930)
Reviewed-on: http://git-master/r/161067
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: tegra11: dvfs: Reduce core voltage range
Alex Frid [Wed, 24 Oct 2012 21:15:25 +0000]
ARM: tegra11: dvfs: Reduce core voltage range

For initial testing of core voltage scaling s/w reduced core voltage
range from [0.9V ... 1.125V] to [1.0V ... 1.120V].

Bug 116126

Change-Id: Ieb21a45d3ecb3a228c2a122cb78aeb2daaaef3d2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147325
(cherry picked from commit 1282fa23b54c2cfdedfeaa439a1cb5945d04b5ad)
Reviewed-on: http://git-master/r/161066
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

7 years agoarm: tegra: fuse: fix the minor number for T11x A01 version.
Krishna Reddy [Sat, 3 Nov 2012 00:53:19 +0000]
arm: tegra: fuse: fix the minor number for T11x A01 version.

The minor number is set to 0 instead of 1 for A01.

Change-Id: I5ffa98f740d4cb6d88ac96d787fe6b463feaf7f0
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/161039
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agoARM: tegra: enterprise: Change Power Rail for nct1008
Xiaohui Tao [Fri, 2 Nov 2012 23:23:40 +0000]
ARM: tegra: enterprise: Change Power Rail for nct1008

The power rail for nct1008 is different for Enterprise A02 and
A03. The A02 uses ldousb_common and A03 uses ldo5. Modify entries
to provide the right one.

bug 1163476

Change-Id: I97592c4b0cb0a484e0846a265c79ad369d411a79
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/161014
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Tested-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agoRevert "asoc: tegra: cs42l73: VSPIN dapm route with DMIC event"
Rahul Mittal [Fri, 2 Nov 2012 09:10:36 +0000]
Revert "asoc: tegra: cs42l73: VSPIN dapm route with DMIC event"

This reverts commit 8bd50e3f390810fffdb63d3b0a32972e09db3000
Fix for pluto DMIC audio recording ANR
Bug 1167696

Change-Id: I58edab224d6527912869e8bafa7248c82c332556
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/160833
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

7 years agoARM: tegra: dalmore: fix multiple GPIO mapping
aghuge [Fri, 2 Nov 2012 09:07:46 +0000]
ARM: tegra: dalmore: fix multiple GPIO mapping

GPIO_PK4 is sued for TS_RESET and not for
EXT_MIC

Bug 1052495

Change-Id: Id078dc732be969b01a9348a01bdef30bd1ee0a3e
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/160830
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: David Jung <djung@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agoarm: tegra: Added platform data for max77665 haptics driver
Sumit Sharma [Wed, 31 Oct 2012 09:21:02 +0000]
arm: tegra: Added platform data for max77665 haptics driver

Added platform data for MAXIM77665 haptics driver in board file

Bug 1157818
Bug 1043388
Bug 1157811

Change-Id: I387f6d589c0e23b2cbdc1b74cc21e3d615f9c985
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/160766
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoarm: tegra: config: Added max77665 haptics driver support
Sumit Sharma [Wed, 31 Oct 2012 09:06:41 +0000]
arm: tegra: config: Added max77665 haptics driver support

Enabled MAXIM 77665 haptics driver support config variable in defconfig

Bug 1157818
Bug 1043388
Bug 1157811

Change-Id: Id05c3fd545c1f6bae05d2a7b48b7f61b48995d4b
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/160765
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agobacklight: max8831: check power before updating bl
Kerwin Wan [Thu, 25 Oct 2012 10:38:57 +0000]
backlight: max8831: check power before updating bl

bug 1057856

Change-Id: I592f61432d4f628618fdf7420e29ff3f5e26046a
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/160406
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agopluto: add interface to check the power of bl
Kerwin Wan [Thu, 25 Oct 2012 10:37:30 +0000]
pluto: add interface to check the power of bl

bug 1057856

Change-Id: Ie30dc8a724f1c961be1aa9f1972d491b47c1bf64
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/160405
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: tegra: Dalmore/pluto: Set drive strengths
Naveen Kumar Arepalli [Tue, 30 Oct 2012 07:01:28 +0000]
ARM: tegra: Dalmore/pluto: Set drive strengths

Enabling HSM for SD Pad groups: SDIO1, SDIO3, GMA
as per characterization team recommendations

Bug 1052592

Change-Id: I6c5f3033effa9f40420ff5f2300ffc0da3ae4041
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/159769
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

7 years agoARM: tegra: Add support to parse pwr_i2c in command line
Chaitanya Bandi [Tue, 30 Oct 2012 06:53:03 +0000]
ARM: tegra: Add support to parse pwr_i2c in command line

Bootloader passes pwr_i2c=1000 if 1Mhz is supported with
PWR_I2C. Parsing this is kernel.

Bug 1158569

Change-Id: I5c6c87e905dceb9d67ef1f23eaf0b70768481061
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/159768
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agotegra: dc: hdmi: Add 720p CVT mode
Shashank Sharma [Fri, 26 Oct 2012 10:54:16 +0000]
tegra: dc: hdmi: Add 720p CVT mode

Add 720p mode in supported CVT video mode list.

Bug 1065850
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Change-Id: I19b90254aa3b4a82965ae43fc7e09b38dad46cd8
Reviewed-on: http://git-master/r/149130
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoarm: tegra: Separating out pmc from usb phy.
Venu Byravarasu [Fri, 26 Oct 2012 11:20:15 +0000]
arm: tegra: Separating out pmc from usb phy.

Taking out PMC from Tegra11x USB phy driver.
This would facilitate in having common PMC interface between XUSB and USB.

Change-Id: I695ac2794ff8324d73e3ed8e679ad5da54593fd4
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-on: http://git-master/r/147480
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

7 years agoARM: tegra11x: flush L2 at entry of system suspend
Bo Yan [Wed, 31 Oct 2012 01:55:26 +0000]
ARM: tegra11x: flush L2 at entry of system suspend

since we are no longer flushing L2 cache in cpu_suspend, this has
to be done when we need to enter system suspend.

Change-Id: If84d1b4e8120e48aaea7fc850254ff71474a4399
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/160077
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

7 years agoARM: Tegra11x: defconfig: Build SND_HDA_INTEL as a module
Rahool Paliwal [Mon, 8 Oct 2012 13:21:00 +0000]
ARM: Tegra11x: defconfig: Build SND_HDA_INTEL as a module

Build SND_HDA_INTEL as a module. SND_HDA_INTEL is required for
audio on HDMI. Building it with "y" makes it default ALSA device,
which then blocks all multimedia audio use cases.

Bug 1154979

Change-Id: Id84f3b7d8a0934a9862dad493706c103aa72cce3
Signed-off-by: Rahool Paliwal <rpaliwal@nvidia.com>
Reviewed-on: http://git-master/r/142434
Reviewed-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
(cherry picked from commit 10bedbfd274014808a9f76808734775e91a12c87)
Reviewed-on: http://git-master/r/160783
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

7 years agoarm: tegra: fix pinmux setting for 4.7in JDI panel
Karthik Ramakrishnan [Fri, 2 Nov 2012 02:50:26 +0000]
arm: tegra: fix pinmux setting for 4.7in JDI panel

Modify pinmux table to reincorporate smart panel related changes.

Change-Id: Ic6d4bca25e937bfae6260aff244ca7b4a549f4ed
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Reviewed-on: http://git-master/r/160761
Tested-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agoARM: tegra11: clock: Propagate shared bus maximum limit
Alex Frid [Tue, 30 Oct 2012 06:03:01 +0000]
ARM: tegra11: clock: Propagate shared bus maximum limit

Propagated recursively maximum rate limitation down the possible
chain of shared buses (don't exist yet). Made sure shared user
rates are not increased while propagating new maximum rate.

Change-Id: Ie77a4212c75e15fd81a4364f8647a11bdb82ceff
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/160461
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

7 years agoARM: tegra11: clock: Rename bus user comparison ops
Alex Frid [Sun, 28 Oct 2012 06:28:58 +0000]
ARM: tegra11: clock: Rename bus user comparison ops

Renamed bus user comparison operations from "cbus_user_is_xxx"
to "bus_user_is_xxx", as they can be applied to non cbus users
as well.

Change-Id: Iced5166f368a688675509dfd0d2e37291d13dd1b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/160460
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

7 years agoCHROMIUM: config: Add t114 splitconfig
Christopher Freeman [Wed, 31 Oct 2012 20:50:54 +0000]
CHROMIUM: config: Add t114 splitconfig

Adds config file for T114/Dalmore for ChromeOS

Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Change-Id: Ie9497a4310b73640bccff66db61fc29c69703128
Reviewed-on: http://git-master/r/160312
Reviewed-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Andrew Chew <achew@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

7 years agoArm: tegra: ahb: Enable AHB prefetch for sdmmc4
naveenk [Tue, 16 Oct 2012 15:19:59 +0000]
Arm: tegra: ahb: Enable AHB prefetch for sdmmc4

Change-Id: I32cbd108998fda75de5ba740370d4aeb9a0c8423
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/159771
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

7 years agovideo: tegra: dc: remove log spam on mode change
Jon Mayo [Fri, 26 Oct 2012 18:12:33 +0000]
video: tegra: dc: remove log spam on mode change

Bug 1159399

Change-Id: I0c359fc080e9b45dcd068b73c97d8c8ca0c487fa
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/159920
Reviewed-by: Automatic_Commit_Validation_User

7 years agoARM: tegra: configs: disble CONFIG_MMC_EMBEDDED_SDIO
Nitin Bindal [Mon, 5 Nov 2012 09:15:18 +0000]
ARM: tegra: configs: disble CONFIG_MMC_EMBEDDED_SDIO

Disble CONFIG_MMC_EMBEDDED_SDIO flag, so that CCCR information
can be read from WiFi chipset.

Bug 1162770

Change-Id: I08f913f528a9eccc246b606309eceae3581f5ea0
Signed-off-by: Nitin Bindal <nbindal@nvidia.com>
Reviewed-on: http://git-master/r/161164
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>