13 years ago[SPARC64]: Fix C-function name called by sun4v_mna trap code.
David S. Miller [Wed, 15 Feb 2006 00:39:22 +0000]
[SPARC64]: Fix C-function name called by sun4v_mna trap code.

The trap code was calling itself :-)

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Don't printk() any messaages in sun4v_build_irq().
David S. Miller [Wed, 15 Feb 2006 00:37:13 +0000]
[SPARC64]: Don't printk() any messaages in sun4v_build_irq().

It just clutters up the log.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: INO is never fully specified already on SUN4V.
David S. Miller [Tue, 14 Feb 2006 22:12:44 +0000]
[SPARC64]: INO is never fully specified already on SUN4V.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Kill sun4v_register_fault_status() on SMP.
David S. Miller [Tue, 14 Feb 2006 21:49:32 +0000]
[SPARC64]: Kill sun4v_register_fault_status() on SMP.

That now gets done as a side effect of taking over the
trap table from OBP.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix gcc-3.3.x warnings.
David S. Miller [Tue, 14 Feb 2006 09:32:29 +0000]
[SPARC64]: Fix gcc-3.3.x warnings.

It doesn't like const variables being passed into
"i" constraing asm operations.  It's a bug, but
there is nothing we can really do but work around
it.

Based upon a report from Andrew Morton.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: arch/sparc64/kernel/trampoline.S needs asm/cpudata.h
David S. Miller [Tue, 14 Feb 2006 08:55:49 +0000]
[SPARC64]: arch/sparc64/kernel/trampoline.S needs asm/cpudata.h

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Make error codes available from sun4v_intr_get*().
David S. Miller [Tue, 14 Feb 2006 06:56:27 +0000]
[SPARC64]: Make error codes available from sun4v_intr_get*().

And check for errors at call sites.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Pass correct ino to sun4v_intr_*().
David S. Miller [Tue, 14 Feb 2006 06:37:32 +0000]
[SPARC64]: Pass correct ino to sun4v_intr_*().

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Use TRAP_LOAD_IRQ_WORK() in sun4v device mondo handler.
David S. Miller [Tue, 14 Feb 2006 06:37:07 +0000]
[SPARC64]: Use TRAP_LOAD_IRQ_WORK() in sun4v device mondo handler.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix IOMMU mapping on sun4v.
David S. Miller [Tue, 14 Feb 2006 05:50:27 +0000]
[SPARC64]: Fix IOMMU mapping on sun4v.

We should dynamically allocate the per-cpu pglist not use
an in-kernel-image datum, since __pa() does not work on
such addresses.

Also, consistently use "u32" for devhandle.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Trim down sun4v IRQ translation kernel log message.
David S. Miller [Tue, 14 Feb 2006 05:36:30 +0000]
[SPARC64]: Trim down sun4v IRQ translation kernel log message.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64] sunhv: Bug fixes.
David S. Miller [Tue, 14 Feb 2006 05:28:40 +0000]
[SPARC64] sunhv: Bug fixes.

Add udelay to polling console write loop, and increment
the loop limit.

Name the device "ttyHV" and pass that to add_preferred_console()
when we're using hypervisor console.

Kill sunhv_console_setup(), it's empty.

Handle the case where we don't want to use hypervisor console.
(ie. we have a head attached to a sun4v machine)

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix comment typo in asm/hypervisor.h
David S. Miller [Tue, 14 Feb 2006 05:15:44 +0000]
[SPARC64]: Fix comment typo in asm/hypervisor.h

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64] sunhv: Use virtual-devices layer to get interrupt.
David S. Miller [Tue, 14 Feb 2006 04:43:02 +0000]
[SPARC64] sunhv: Use virtual-devices layer to get interrupt.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Probe virtual-devices root node on sun4v.
David S. Miller [Tue, 14 Feb 2006 04:42:16 +0000]
[SPARC64]: Probe virtual-devices root node on sun4v.

This is where we learn how to get the interrupts
for things like the hypervisor console device.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Kill spurious semicolon in sun4v_pci_init().
David S. Miller [Tue, 14 Feb 2006 04:41:11 +0000]
[SPARC64]: Kill spurious semicolon in sun4v_pci_init().

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Prevent registering wrong serial console.
David S. Miller [Tue, 14 Feb 2006 04:09:10 +0000]
[SPARC64]: Prevent registering wrong serial console.

If the console is not for a particular Sun serial
controller, set the drv->cons to NULL.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Program IRQ registers correctly on sun4v.
David S. Miller [Tue, 14 Feb 2006 02:22:57 +0000]
[SPARC64]: Program IRQ registers correctly on sun4v.

Need to use hypervisor calls instead of direct register
accesses.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Generic sun4v_build_irq().
David S. Miller [Tue, 14 Feb 2006 02:16:10 +0000]
[SPARC64]: Generic sun4v_build_irq().

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: More SUN4V PCI work.
David S. Miller [Tue, 14 Feb 2006 02:09:44 +0000]
[SPARC64]: More SUN4V PCI work.

Get bus range from child of PCI controller root nexus.
This is actually a hack, but the PCI-E bridge sitting
at the top of the PCI tree responds to PCI config cycles
for every device number, so best to just ignore it for now.

Preliminary PCI irq routing, needs lots of work.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Log faulting vaddr when bogus kernel PC detected.
David S. Miller [Tue, 14 Feb 2006 02:07:45 +0000]
[SPARC64]: Log faulting vaddr when bogus kernel PC detected.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Implement rest of generic interrupt hypervisor calls.
David S. Miller [Mon, 13 Feb 2006 08:23:32 +0000]
[SPARC64]: Implement rest of generic interrupt hypervisor calls.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.S
David S. Miller [Mon, 13 Feb 2006 08:02:16 +0000]
[SPARC64]: Move devino_to_sysino out of pci_sun4v_asm.S

It is not PCI specific, it is for all system interrupts.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Range check bus number in SUN4V PCI controller driver.
David S. Miller [Mon, 13 Feb 2006 07:49:18 +0000]
[SPARC64]: Range check bus number in SUN4V PCI controller driver.

It has to be somewhere in the range from pbm->pci_first_busno to
pbm->pci_last_busno, inclusive.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Missing 'return' statement in sun4v_pci_init().
David S. Miller [Mon, 13 Feb 2006 06:29:36 +0000]
[SPARC64]: Missing 'return' statement in sun4v_pci_init().

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Implement basic pci_sun4v_scan_bus().
David S. Miller [Mon, 13 Feb 2006 06:18:52 +0000]
[SPARC64]: Implement basic pci_sun4v_scan_bus().

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: PCI-SUN4V fixes.
David S. Miller [Mon, 13 Feb 2006 06:06:53 +0000]
[SPARC64]: PCI-SUN4V fixes.

Clear top 8-bits of physical addresses in "ranges" property.
This gives the actual physical address.

Detect PBM-A vs. PBM-B by checking bit 0x40 of the devhandle.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Use inline patching for critical PTE operations.
David S. Miller [Mon, 13 Feb 2006 05:10:07 +0000]
[SPARC64]: Use inline patching for critical PTE operations.

This handles the SUN4U vs SUN4V PTE layout differences
with near zero performance cost.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Move PTE field definitions back into asm/pgtable.h
David S. Miller [Mon, 13 Feb 2006 01:07:51 +0000]
[SPARC64]: Move PTE field definitions back into asm/pgtable.h

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Don't expect cfg space in PCI PBM ranges on SUN4V.
David S. Miller [Sun, 12 Feb 2006 07:38:00 +0000]
[SPARC64]: Don't expect cfg space in PCI PBM ranges on SUN4V.

PCI cfg space is accessed transparently through the Hypervisor and not
through direct cpu PIO operations.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix branch signedness bug in all code patching.
David S. Miller [Sun, 12 Feb 2006 07:28:40 +0000]
[SPARC64]: Fix branch signedness bug in all code patching.

The bug that hit SUN4V TLB patching exists elsewhere.
Make sure we cure all such cases.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Recognize "virtual-console" as input and output console device.
David S. Miller [Sun, 12 Feb 2006 07:24:30 +0000]
[SPARC64]: Recognize "virtual-console" as input and output console device.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Do not try to synchronize %stick registers on SUN4V.
David S. Miller [Sun, 12 Feb 2006 07:22:47 +0000]
[SPARC64]: Do not try to synchronize %stick registers on SUN4V.

Writes by privileged code are not allowed.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Do not try to write to %tick or %stick on SUN4V.
David S. Miller [Sun, 12 Feb 2006 07:14:59 +0000]
[SPARC64]: Do not try to write to %tick or %stick on SUN4V.

Writes by privileged code are disallowed.  The hypervisor manages
the non-privileged bit.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix mondo queue allocations.
David S. Miller [Sun, 12 Feb 2006 07:07:13 +0000]
[SPARC64]: Fix mondo queue allocations.

We have to use bootmem during init_IRQ and page alloc
for sibling cpu calls.

Also, fix incorrect hypervisor call return value
checks in the hypervisor SMP cpu mondo send code.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Deal with PTE layout differences in SUN4V.
David S. Miller [Sun, 12 Feb 2006 05:57:54 +0000]
[SPARC64]: Deal with PTE layout differences in SUN4V.

Yes, you heard it right, they changed the PTE layout for
SUN4V.  Ho hum...

This is the simple and inefficient way to support this.
It'll get optimized, don't worry.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Register kernel TSB with hypervisor.
David S. Miller [Sat, 11 Feb 2006 22:41:18 +0000]
[SPARC64]: Register kernel TSB with hypervisor.

We do this right after we take over the trap table from OBP.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix some SUN4V TLB miss bugs.
David S. Miller [Sat, 11 Feb 2006 20:21:20 +0000]
[SPARC64]: Fix some SUN4V TLB miss bugs.

Code patching did not sign extend negative branch
offsets correctly.

Kernel TLB miss path needs patching and %g4 register
preservation in order to handle SUN4V correctly.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix typo in sun4v_patch().
David S. Miller [Sat, 11 Feb 2006 19:05:52 +0000]
[SPARC64]: Fix typo in sun4v_patch().

Second instruction offset is '4' not '3'.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix sun4v early bootup.
David S. Miller [Sat, 11 Feb 2006 18:56:43 +0000]
[SPARC64]: Fix sun4v early bootup.

prom_sun4v_name should be "sun4v" not "SUNW,sun4v"

Also, this is too early to make use of the
.sun4v_Xinsn_patch code patching, so just check
things manually.

This gets us at least to prom_init() on Niagara.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix some Niagara memcpy() bugs.
David S. Miller [Sat, 11 Feb 2006 18:30:41 +0000]
[SPARC64]: Fix some Niagara memcpy() bugs.

We need to restore the %asi register properly.
For the kernel this means get_fs(), for user this
means ASI_PNF.

Also, NGcopy_to_user.S was including U3memcpy.S instead
of NGmemcpy.S, oops :-)

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Handle hypervisor case correctly in copy_tsb().
David S. Miller [Sat, 11 Feb 2006 18:19:37 +0000]
[SPARC64]: Handle hypervisor case correctly in copy_tsb().

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add SUN4V Hypervisor Console driver.
David S. Miller [Sat, 11 Feb 2006 10:25:21 +0000]
[SPARC64]: Add SUN4V Hypervisor Console driver.

Since it can do things like BREAK and HUP, we implement
this as a serial uart driver.

This still needs interrupt probing code, as I haven't figured
out how interrupts will work or be probed for on SUN4V yet.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fetch bootup time of day from Hypervisor.
David S. Miller [Sat, 11 Feb 2006 09:01:55 +0000]
[SPARC64]: Fetch bootup time of day from Hypervisor.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Simplify sun4v TLB handling using macros.
David S. Miller [Sat, 11 Feb 2006 08:29:34 +0000]
[SPARC64]: Simplify sun4v TLB handling using macros.

There was also a bug in sun4v_itlb_miss, it loaded the
MMU Fault Status base into %g3 instead of %g2.

This pointed out a fast path for TSB miss processing,
since we have %g2 with the MMU Fault Status base, we
can use that to quickly load up the PGD phys address.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.
David S. Miller [Fri, 10 Feb 2006 23:39:51 +0000]
[SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.

This is where the virtual address of the fault status
area belongs.

To set it up we don't make a hypervisor call, instead
we call OBP's SUNW,set-trap-table with the real address
of the fault status area as the second argument.  And
right before that call we write the virtual address into
ASI_SCRATCHPAD vaddr 0x0.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: First cut at SUN4V PCI IOMMU handling.
David S. Miller [Fri, 10 Feb 2006 08:08:26 +0000]
[SPARC64]: First cut at SUN4V PCI IOMMU handling.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix hypervisor call arg passing.
David S. Miller [Fri, 10 Feb 2006 06:57:21 +0000]
[SPARC64]: Fix hypervisor call arg passing.

Function goes in %o5, args go in %o0 --> %o5.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add HV_PCI_TSBID() macro.
David S. Miller [Fri, 10 Feb 2006 06:26:34 +0000]
[SPARC64]: Add HV_PCI_TSBID() macro.

For constructing hypervisor PCI TSB IDs.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Implement SUN4V PCI config space access.
David S. Miller [Fri, 10 Feb 2006 06:20:01 +0000]
[SPARC64]: Implement SUN4V PCI config space access.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: More SUN4V PCI controller work.
David S. Miller [Fri, 10 Feb 2006 06:05:54 +0000]
[SPARC64]: More SUN4V PCI controller work.

Add assembler file for PCI hypervisor calls.
Setup basic skeleton of SUN4V PCI controller driver.

Add 32-bit devhandle to PBM struct, as this is needed for
hypervisor calls.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Beginnings of SUN4V PCI controller support.
David S. Miller [Fri, 10 Feb 2006 05:32:07 +0000]
[SPARC64]: Beginnings of SUN4V PCI controller support.

Abstract out IOMMU operations so that we can have a different
set of calls on sun4v, which needs to do things through
hypervisor calls.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fetch cpu mid properly on sun4v.
David S. Miller [Fri, 10 Feb 2006 04:46:22 +0000]
[SPARC64]: Fetch cpu mid properly on sun4v.

If there is a "cpuid" property, use that.  Else suck
it out of the top bits of the "reg" property.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC]: Clean up idprom header files.
David S. Miller [Fri, 10 Feb 2006 04:45:26 +0000]
[SPARC]: Clean up idprom header files.

Delete unused macros, and use fixed sized types in
sparc32 header.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: SUN4V memory exception trap handlers.
David S. Miller [Fri, 10 Feb 2006 04:20:34 +0000]
[SPARC64]: SUN4V memory exception trap handlers.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Hypervisor TSB context switching.
David S. Miller [Fri, 10 Feb 2006 01:21:53 +0000]
[SPARC64]: Hypervisor TSB context switching.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Implement sun4v TSB miss handlers.
David S. Miller [Fri, 10 Feb 2006 00:12:22 +0000]
[SPARC64]: Implement sun4v TSB miss handlers.

When we register a TSB with the hypervisor, so that it or hardware can
handle TLB misses and do the TSB walk for us, the hypervisor traps
down to these trap when it incurs a TSB miss.

Processing is simple, we load the missing virtual address and context,
and do a full page table walk.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: kernel/cpu.c needs asm/spitfire.h
David S. Miller [Thu, 9 Feb 2006 11:00:00 +0000]
[SPARC64]: kernel/cpu.c needs asm/spitfire.h

For 'tlb_type'.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Print ARCH as SUN4V when tlb_type is hypervisor.
David S. Miller [Thu, 9 Feb 2006 10:54:54 +0000]
[SPARC64]: Print ARCH as SUN4V when tlb_type is hypervisor.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Detect sun4v early in boot process.
David S. Miller [Thu, 9 Feb 2006 10:52:44 +0000]
[SPARC64]: Detect sun4v early in boot process.

We look for "SUNW,sun4v" in the 'compatible' property
of the root OBP device tree node.

Protect every %ver register access, to make sure it is
not touched on sun4v, as %ver is hyperprivileged there.

Lock kernel TLB entries using hypervisor calls instead of
calls into OBP.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Sun4v cross-call sending support.
David S. Miller [Thu, 9 Feb 2006 00:41:20 +0000]
[SPARC64]: Sun4v cross-call sending support.

Technically the hypervisor call supports sending in a list
of all cpus to get the cross-call, but I only pass in one
cpu at a time for now.

The multi-cpu support is there, just ifdef'd out so it's easy to
enable or delete it later.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Sun4v interrupt handling.
David S. Miller [Wed, 8 Feb 2006 10:53:50 +0000]
[SPARC64]: Sun4v interrupt handling.

Sun4v has 4 interrupt queues: cpu, device, resumable errors,
and non-resumable errors.  A set of head/tail offset pointers
help maintain a work queue in physical memory.  The entries
are 64-bytes in size.

Each queue is allocated then registered with the hypervisor
as we bring cpus up.

The two error queues each get a kernel side buffer that we
use to quickly empty the main interrupt queue before we
call up to C code to log the event and possibly take evasive
action.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Allocate and register the 4 sun4v mondo queues at bootup.
David S. Miller [Wed, 8 Feb 2006 08:08:23 +0000]
[SPARC64]: Allocate and register the 4 sun4v mondo queues at bootup.

Needs to occur before we enable PSTATE_IE in %pstate.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Verify all trap_per_cpu assembler offsets in trap_init()
David S. Miller [Wed, 8 Feb 2006 07:51:49 +0000]
[SPARC64]: Verify all trap_per_cpu assembler offsets in trap_init()

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add sun4v mondo queue bases to struct trap_per_cpu.
David S. Miller [Wed, 8 Feb 2006 06:53:56 +0000]
[SPARC64]: Add sun4v mondo queue bases to struct trap_per_cpu.

Also, correct TRAP_PER_CPU_FAULT_INFO define, it should be
0x40 not 0x20.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix some comment typos in asm/hypervisor.h
David S. Miller [Wed, 8 Feb 2006 06:49:38 +0000]
[SPARC64]: Fix some comment typos in asm/hypervisor.h

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Patch up mmu context register writes for sun4v.
David S. Miller [Wed, 8 Feb 2006 06:13:05 +0000]
[SPARC64]: Patch up mmu context register writes for sun4v.

sun4v uses ASI_MMU instead of ASI_DMMU

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Register per-cpu fault status area with sun4v hypervisor.
David S. Miller [Wed, 8 Feb 2006 05:51:08 +0000]
[SPARC64]: Register per-cpu fault status area with sun4v hypervisor.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: asm/cpudata.h needs asm/asi.h
David S. Miller [Wed, 8 Feb 2006 05:15:41 +0000]
[SPARC64]: asm/cpudata.h needs asm/asi.h

For the expansion of __GET_CPUID() on SMP.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Niagara copy/clear page.
David S. Miller [Wed, 8 Feb 2006 00:09:12 +0000]
[SPARC64]: Niagara copy/clear page.

Happily we have no D-cache aliasing issues on these
chips, so the implementation is very straightforward.

Add a stub in bootup which will be where the patching
calls will be made for niagara/sun4v/hypervisor.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patch
David S. Miller [Tue, 7 Feb 2006 08:00:16 +0000]
[SPARC64]: Rename gl_{1,2}insn_patch --> sun4v_{1,2}insn_patch

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Initial sun4v TLB miss handling infrastructure.
David S. Miller [Tue, 7 Feb 2006 07:44:37 +0000]
[SPARC64]: Initial sun4v TLB miss handling infrastructure.

Things are a little tricky because, unlike sun4u, we have
to:

1) do a hypervisor trap to do the TLB load.
2) do the TSB lookup calculations by hand

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add missing memory barriers to instruction patching functions.
David S. Miller [Mon, 6 Feb 2006 23:52:05 +0000]
[SPARC64]: Add missing memory barriers to instruction patching functions.

V9 requires a write memory barrier before the instruction flush.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Sanitize %pstate writes for sun4v.
David S. Miller [Mon, 6 Feb 2006 06:27:28 +0000]
[SPARC64]: Sanitize %pstate writes for sun4v.

If we're just switching between different alternate global
sets, nop it out on sun4v.  Also, get rid of all of the
alternate global save/restore in the OBP CIF trampoline code.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Kill all %pstate changes in context switch code.
David S. Miller [Mon, 6 Feb 2006 05:59:03 +0000]
[SPARC64]: Kill all %pstate changes in context switch code.

They are totally unnecessary because:

1) Interrupts are already disabled when switch_to()
   runs.

2) We don't use hard-coded alternate globals any longer.

This found a case in rtrap, which still assumed alternate
global %g6 was current_thread_info(), and that is fixed
by this changeset as well.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add initial code to twiddle %gl on trap entry/exit.
David S. Miller [Mon, 6 Feb 2006 05:29:28 +0000]
[SPARC64]: Add initial code to twiddle %gl on trap entry/exit.

Instead of setting/clearing PSTATE_AG we have to change
the %gl register value on sun4v.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fill dead cycles on trap entry with real work.
David S. Miller [Mon, 6 Feb 2006 04:47:26 +0000]
[SPARC64]: Fill dead cycles on trap entry with real work.

As we save trap state onto the stack, the store buffer fills up
mid-way through and we stall for several cycles as the store buffer
trickles out to the L2 cache.  Meanwhile we can do some privileged
register reads and other calculations, essentially for free.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add define for "GL" field of sun4v %tstate register.
David S. Miller [Sun, 5 Feb 2006 07:59:38 +0000]
[SPARC64]: Add define for "GL" field of sun4v %tstate register.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add sun4v case to __GET_CPUID() patch tables.
David S. Miller [Sat, 4 Feb 2006 23:40:53 +0000]
[SPARC64]: Add sun4v case to __GET_CPUID() patch tables.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Sun4v interrupt queue register definitions.
David S. Miller [Sat, 4 Feb 2006 11:12:14 +0000]
[SPARC64]: Sun4v interrupt queue register definitions.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Sun4v scratchpad register layout.
David S. Miller [Sat, 4 Feb 2006 11:12:02 +0000]
[SPARC64]: Sun4v scratchpad register layout.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Sun4v specific ASI defines.
David S. Miller [Sat, 4 Feb 2006 11:11:50 +0000]
[SPARC64]: Sun4v specific ASI defines.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Niagara optimized memcpy() and copy_{to,from}_user().
David S. Miller [Mon, 6 Mar 2006 00:41:56 +0000]
[SPARC64]: Niagara optimized memcpy() and copy_{to,from}_user().

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add Niagara init-store twin-load ASI defines.
David S. Miller [Sat, 4 Feb 2006 11:11:17 +0000]
[SPARC64]: Add Niagara init-store twin-load ASI defines.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add some hypervisor tlb_type checks.
David S. Miller [Sat, 4 Feb 2006 11:10:53 +0000]
[SPARC64]: Add some hypervisor tlb_type checks.

And more consistently check cheetah{,_plus} instead
of assuming anything not spitfire is cheetah{,_plus}.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add 'hypervisor' to ultra_tlb_type enumeration.
David S. Miller [Sat, 4 Feb 2006 11:09:03 +0000]
[SPARC64]: Add 'hypervisor' to ultra_tlb_type enumeration.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: SUN4V hypervisor TLB flush support code.
David S. Miller [Sat, 4 Feb 2006 11:08:37 +0000]
[SPARC64]: SUN4V hypervisor TLB flush support code.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: SUN4V hypervisor interface defines.
David S. Miller [Sat, 4 Feb 2006 11:01:45 +0000]
[SPARC64]: SUN4V hypervisor interface defines.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Refine register window trap handling.
David S. Miller [Sat, 4 Feb 2006 08:10:01 +0000]
[SPARC64]: Refine register window trap handling.

When saving and restoing trap state, do the window spill/fill
handling inline so that we never trap deeper than 2 trap levels.
This is important for chips like Niagara.

The window fixup code is massively simplified, and many more
improvements are now possible.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Add explicit register args to trap state loading macros.
David S. Miller [Fri, 3 Feb 2006 05:55:10 +0000]
[SPARC64]: Add explicit register args to trap state loading macros.

This, as well as making the code cleaner, allows a simplification in
the TSB miss handling path.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Refine code sequences to get the cpu id.
David S. Miller [Mon, 27 Feb 2006 07:27:19 +0000]
[SPARC64]: Refine code sequences to get the cpu id.

On uniprocessor, it's always zero for optimize that.

On SMP, the jmpl to the stub kills the return address stack in the cpu
branch prediction logic, so expand the code sequence inline and use a
code patching section to fix things up.  This also always better and
explicit register selection, which will be taken advantage of in a
future changeset.

The hard_smp_processor_id() function is big, so do not inline it.

Fix up tests for Jalapeno to also test for Serrano chips too.  These
tests want "jbus Ultra-IIIi" cases to match, so that is what we should
test for.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Turn off TSB growing for now.
David S. Miller [Fri, 3 Feb 2006 00:16:24 +0000]
[SPARC64]: Turn off TSB growing for now.

There are several tricky races involved with growing the TSB.  So just
use base-size TSBs for user contexts and we can revisit enabling this
later.

One part of the SMP problems is that tsb_context_switch() can see
partially updated TSB configuration state if tsb_grow() is running in
parallel.  That's easily solved with a seqlock taken as a writer by
tsb_grow() and taken as a reader to capture all the TSB config state
in tsb_context_switch().

Then there is flush_tsb_user() running in parallel with a tsb_grow().
In theory we could take the seqlock as a reader there too, and just
resample the TSB pointer and reflush but that looks really ugly.

Lastly, I believe there is a case with threads that results in a TSB
entry lock bit being set spuriously which will cause the next access
to that TSB entry to wedge the cpu (since the TSB entry lock bit will
never clear).  It's either copy_tsb() or some bug elsewhere in the TSB
assembly.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Correctable ECC errors cannot occur at trap level > 0.
David S. Miller [Thu, 2 Feb 2006 09:20:18 +0000]
[SPARC64]: Correctable ECC errors cannot occur at trap level > 0.

The are distrupting, which by the sparc v9 definition means they
can only occur when interrupts are enabled in the %pstate register.
This never occurs in any of the trap handling code running at
trap levels > 0.

So just mark it as an unexpected trap.

This allows us to kill off the cee_stuff member of struct thread_info.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Access TSB with physical addresses when possible.
David S. Miller [Wed, 1 Feb 2006 23:55:21 +0000]
[SPARC64]: Access TSB with physical addresses when possible.

This way we don't need to lock the TSB into the TLB.
The trick is that every TSB load/store is registered into
a special instruction patch section.  The default uses
virtual addresses, and the patch instructions use physical
address load/stores.

We can't do this on all chips because only cheetah+ and later
have the physical variant of the atomic quad load.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.h
David S. Miller [Wed, 1 Feb 2006 07:13:29 +0000]
[SPARC64]: Kill out-of-date commentary in asm-sparc64/tsb.h

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Don't clobber alt-global %g4 on window fixups.
David S. Miller [Wed, 1 Feb 2006 02:35:05 +0000]
[SPARC64]: Don't clobber alt-global %g4 on window fixups.

If we are returning back to kernel mode, %g4 could be live
(for example, in the case where we window spill in the etrap
code).  So do not change it's value if going back to kernel.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix race in LOAD_PER_CPU_BASE()
David S. Miller [Wed, 1 Feb 2006 02:34:51 +0000]
[SPARC64]: Fix race in LOAD_PER_CPU_BASE()

Since we use %g5 itself as a temporary, it can get clobbered
if we take an interrupt mid-stream and thus cause end up with
the final %g5 value too early as a result of rtrap processing.

Set %g5 at the very end, atomically, to avoid this problem.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Kill swapper_pgd_zero, totally unused.
David S. Miller [Wed, 1 Feb 2006 02:34:34 +0000]
[SPARC64]: Kill swapper_pgd_zero, totally unused.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Fix too early reference to %g6
David S. Miller [Wed, 1 Feb 2006 02:34:21 +0000]
[SPARC64]: Fix too early reference to %g6

%g6 is not necessarily set to current_thread_info()
at sparc64_realfault_common.  So store the fault
code and address after we invoke etrap and %g6 is
properly set up.

Signed-off-by: David S. Miller <davem@davemloft.net>

13 years ago[SPARC64]: Kill hard-coded %pstate setting in sparc_exit.
David S. Miller [Wed, 1 Feb 2006 02:34:06 +0000]
[SPARC64]: Kill hard-coded %pstate setting in sparc_exit.

Just flip the bit off of whatever it's currently set to.
PSTATE_IE is guarenteed to be enabled when we get here.

Signed-off-by: David S. Miller <davem@davemloft.net>