asoc: aic326x machine: add aic326x for enterprise

Change-Id: I1b41c408b65b79f12b20a5efb7c0d2e3245bad6a
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/90057
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>

ARM: tegra: enterprise: enable TI AIC326x codec

Change-Id: I941e1140b139240d04906759098249508dbd9535
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/90056
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>

net: usb: raw-ip: rx / tx statistics

Add rx, tx, error statistics feature

Bug 932703

Change-Id: Ic7a6232dd3b48feff2b064fcff8f0d146b1e9902
Signed-off-by: Shawn Joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/89305
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>

video: tegra3: dc: remove hard coded HDMI rates

Set dc clock rate dynamically to requested pixel rate.
Using modes specified in monitor's EDID data.
Return mode set errors on unsupported clock tolerances.

Bug 931908

Change-Id: I60990ecbc2fbeab542987036b8ccc30b8dababe8
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-on: http://git-master/r/86073
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

video: tegra: nvavp: Fix for high SMMU aparture

- With this fix NVAVP works with CONFIG_TEGRA_SMMU_BASE_AT_E0000000.

Change-Id: I9c267bc9b008a57f6f0cc4e9b27dbee0501e6a77
Signed-off-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-on: http://git-master/r/91316
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra3: p1852: clock: changed p1852 clocks

Changed clock frequencies for vi, host1x etc. as per POR
Bug 882186

Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/74289
(cherry picked from commit 915b9924388f432fbc68be611f84047d09fc0d33)

Change-Id: I19c3aa845c75f0b8d07bd2dd109055696098e12a
Reviewed-on: http://git-master/r/90494
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

arm: tegra: baseband: Add wakelock after modem re-enumeration.

Holding wakelock after modem re-enumeration to ensure ril has enough
time to restart.

Bug 948610

Reviewed-on: http://git-master/r/91072
(cherry picked from commit 572bd2f735c4667ce326a1acb6e7d0884847d794)

Change-Id: Iee4f5243746ca218623c1ac2cd173482badba358
Signed-off-by: Steve Lin <stlin@nvidia.com>
Reviewed-on: http://git-master/r/91361
Reviewed-by: Automatic_Commit_Validation_User

video: tegra: dc: VGA modes in supported mode list

Add following VGA video modes in tegra_dc_hdmi_supported_modes list:

Resolution   Refresh rate(Hz)
-----------  ----------------
 640x480  75
 720x400  59
 800x600  60
 800x600  75
1024x768  75
1024x768  60
1152x864  75
1280x800  60
1280x960  60
1280x1024  60
1368x768  60
1440x900  60
1600x1200  75
1680x1050  60

Add CVT representation of all above modes to make sure they pass all the
HDMI constraints.
Add a new function tegra_dc_reload_mode to pick up CVT representation of
matching mode.

Bug 883911
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Change-Id: I5227644207d38ca83a0452d3c078ef202e40a508
Reviewed-on: http://git-master/r/89126
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

ASoC: Tegra WM8903 machine: Fix to control name conflict

This change resolves the control name (Line Out Switch) conflict between
wm8903 codec driver and tegra machine driver.

Bug 956506

Change-Id: Iab049c7fb2fdde0d481d07d8e1bbdbeea1a831d9
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: http://git-master/r/91510
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

media: common camera headers

- Add support for ISP focus

Bug 852480

Change-Id: Ibd4c983d80a5021a88b46033c51c26d1b8120e62
Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com>
Reviewed-on: http://git-master/r/91203
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

tegra:pcie: Correct pcie check link sequence

1. Removed mdelay in reset code since pci devices
   are not detected with this.
2. Moved the reset logic down in retry label.

Bug 637871

Change-Id: Idd6344860e513407d5f8c8ba05e1beef0f39bf57
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/89128
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>

arm: tegra: kai: Correcting fuse supply name

As fuse driver expects regulator name as Vdd_fuse
instead of Vpp_fuse, fixing it.

bug 956535

Change-Id: I4ecf38acd2ae8c2191f4dbbd018904a33b87043c
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-on: http://git-master/r/91472
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

arm: tegra: enterprise: enable out of band interrupt

configuring wf_wakeup gpio

Change-Id: I05e907c36847da07990d440357b9ef4ae3a857be
Signed-off-by: Nitin Bindal <nbindal@nvidia.com>
Reviewed-on: http://git-master/r/90994
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: dc: disable disp.emc clock when 0 new rate is requested

Not disabling emc clock when it's being set to zero results in incorrect
reference count when a call is made to clear bandwidth. This happens when
two worker threads try to handle dc emc rate. A deep-sleep/wake-up cycle
easily shows this scenario.

With this fix, disp.emc's ref count is properly managed even after multiple
deep-sleep/wake-up cycles.

Bug 947228

Change-Id: I045fafbd483af1e3d492b8d0395275e45642d059
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: http://git-master/r/90100
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

video: tegra: host: Correct waitchk comparison logic

Change waitchk comparison logic to use the new
nvhost_syncpt_is_expired().

Bug 941327

Change-Id: Ib7de04ad7663990bb416e39f8d79a46a9f5955fa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/89769
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

arm: Tegra: Ventana: power gpio modification

Correction on the power_gpio assignement for SD and eMMC platform data.

TEGRA_GPIO_PI6 is assigned to power_gpio of tegra_sdhci_platform_data2

Since no gpio control is there for eMMC power rails power_gpio of
tegra_sdhci_platform_data3 is initialized to -1.

Change-Id: I5b18f09c01668e304425dee92f024be69d3e0448
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: http://git-master/r/86355
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>

Bluetooth: remove DEBUG macro from btwilink driver

Change-Id: I1721115a1d500f1101c856809ec3fd3ac4a3fe67
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: http://git-master/r/89409
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

cpufreq: Typecast compared integers

The min/max frequencies in cpufreq_policy are unsigned integers
but pm_qos_request() returns a signed int. Compare as unsigned,
frequencies are never negative.

Bug 949219

Change-Id: Iba0de9ad6bf221f7a2e5560f597aa56cbeb7b6f6
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/91214
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

cpufreq: set go_maxspeed_load to 85%

To get better performance setting it to 85% from 95%

bug 941275

Change-Id: I08bc711ea159d070cf6b62ce25506c8a5bdd7ac4
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/91159
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

Revert "ARM: tegra: dvfs: Set Tegra3 VDD_CORE min to 1.1V"

This reverts commit db462754240e2ee6cf85e1253b1475a330ea0dfe -
temporary work-around for bug 870300 is no longer needed.

Change-Id: I3b76c01eef89cd80134210926e6623f0494626dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/89874
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

ARM: config: tegra: enable advanced routing and multiple routing table

These options are needed for multiple PDP context support

bug 926236

Change-Id: I7a62db30403b1d610e0b801b2b0ef5ebee2f7f23
signed-off-by: Stephane Dion <sdion@nvidia.com>
Reviewed-on: http://git-master/r/89509
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

video: tegra: host: refactor for upstreaming

- split the nvhost clients into their own directories
- each client is a nvhost_device and nvhost_driver
- all the code related to host1x control node is centralized
at single place in dev.c
- all the code related to host1x modules nodes is centralized
at single place in bus_client.c
- update the copyright notice & year for new files

Bug 871237

Change-Id: Ief85064699e35ad02b48a7e54496928d7f085af4
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/83491
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

cpufreq: update target freq always

set determined target freq always

bug 941275

Change-Id: If72936ed145867abd32b43c5c5100290df2fc187
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/91010
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Satya Popuri <spopuri@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra: cardhu: Enable Enter key if RCK mode

Added support to change Power key to
Enter key in RCK mode

Bug 948270

Change-Id: I054aa98972494476ea26b5fd815032453a4231b0
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/90917
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

ARM: tegra: Add support to identify if image RCK

With this change, we can identify if system
enters RCK mode in kernel.

Bug 948270

Change-Id: I4240fd4171b6b71fbc5f1271f21a588d62db88b1
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/90914
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra: clock: Update parameterized cluster switch

Adjusted CPU rate during parametrized (enforced from sysfs) cluster
switch, so that target rate meets min/max constraints on both sides
of the switch. Updated local timer rate accordingly.

Bug 945975

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit c27f5a2e7380cb667f1f6a4ba61daf67c63ef2d4)

Change-Id: I130ec1a32ecaf8adfd7eff1ec2042f569b54ac54
Reviewed-on: http://git-master/r/90805
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

video: tegra: dsi: Clear host trigger bit explicitly on fifo empty

dsi HW does not clear host trigger bit automatically
on dsi interface disable if host fifo is empty.
This leads to hang. Clearing the bit explicitly.

Bug 930453

Change-Id: Id24359dc274f187f8ac634ad838ef4a6a29a6a5e
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/90043
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

ARM: tegra: Add AHB EMEM to MC Flush Register IO

Add the AHB EMEM to MC Flush Register
area to the statically mapped io regions

Bug 729267

Change-Id: I86542cd3ffec587e7213cbc34129e8b5124aab9c
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/88283
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

ARM: tegra: clock: Fix activity monitor resume

Properly restore Tegra3 actmon sampling period after suspend.

Bug 952739

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit eb6e96a39dbc5d310e8e59046d6e1b787b780e60)

Change-Id: I6a61c2aa1d384a8d17d7ef579000cf59ac218435
Reviewed-on: http://git-master/r/90804
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arm: tegra: fuse: let ODM production mode be world readable

Also, fixup some of the bit offsets that were leading to incorrect
values being returned from get_fuse() on T20/T30.

Bug 912862

Signed-off-by: Chris Johnson <cwj@nvidia.com>
Reviewed-on: http://git-master/r/89283
(cherry picked from commit f6323c7f32017b51202d478671cbf366beb0b0f5)

Change-Id: Ieb9f92e36760cbc470d63257d26c09388cec7e1e
Reviewed-on: http://git-master/r/90762
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Chris Johnson <cwj@nvidia.com>
Tested-by: Chris Johnson <cwj@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

arm: tegra: nvmap: Update nvmap_alloc api.

Update nvmap_alloc api to take heap_mask as arg.
This is to let clients specify the specific heap needed.

Change-Id: I9950b3e60e6dac0301b6dc66be3e9d0bab8e0fee
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/90471
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

video: tegra: host: Fix sync point comparison

Fix sync point comparison to take into account old expired values, and
do proper comparison taking into account wrapping.

Bug 941327

Change-Id: I70724637ba870b2e29bac695abc0ea2b968394d7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/84808
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ilan Aelion <iaelion@nvidia.com>
Reviewed-by: Acorn Pooley <apooley@nvidia.com>

arm: tegra: enable pll_p clocks by default

Setting pll_p init state to false may cause lp0 resume issue when
cpu_restore_complex tries to restore pll_p state on CPU cluster
switching.

Bug 932820

Signed-off-by: Peter Zu <pzu@nvidia.com>
Reviewed-on: http://git-master/r/86904
(cherry picked from commit 939e6c177927a4731b043ac77543f075ac17fca2)

Change-Id: I4513470515a20edcf54a9aa11a54e65838012fe5
Reviewed-on: http://git-master/r/90568
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

video: tegra: nvmap: Optimze nvmap page pool shrink time

Bug 925987

Change-Id: Ifab4e515c7dd06b92d798e7eb93094c35e02b878
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/89414
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Drivers: MTD: NAND: restore to the NAND controller

On entering the power saving mode NAND controller registers are getting reset.
With this change resume will restore the controller registers' values.

Bug 933291

Change-Id: Ia1a43827b4b4a91ab1383bf07c3c0fe3068b666b
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: http://git-master/r/90883
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra3: dvfs: Changed max values of clocks

Changed clock frequency of some clocks as per
Automotive POR.

Bug 882186

Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/75210
(cherry picked from commit 9cc17e9cddfedc6fe977f103c5e21ae3f82c3496)

Change-Id: Ibb0e79e75c2fca7d9f09d373c163ef08cc636819
Reviewed-on: http://git-master/r/90490
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

video: tegra: clean-up warnings and code style

fix some build warnings and bad code style.

Change-Id: I907296ce0e5437dfd6acd0b2b3c119b6dbde7b1c
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/89634
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

ARM: tegra: disable proximity sensor in defconfig

Disable isl29028 proximity sensor.

bug 946330

Change-Id: I7a5d9f1defbb1de5f02fe851f7a24cd70d49d47b
Signed-off-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-on: http://git-master/r/87897
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

regulator: tps65910: Provide settling time for DCDC voltage change

Settling time is require when there is dcdc rail's voltage change.
Returning proper delay time for dcdc voltage change to settle down
the output voltage to new value.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 18039e0f16d50c8243fe0388a587c25a3b155ece)

Change-Id: Ibd67d2661dd1d5b014754c221d44963baeb13726
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90518
Reviewed-by: Automatic_Commit_Validation_User

regulator: tps65910: Provide settling time for enabling rails

There is settling time for each rails when it is switched to
ON. Implementing enable time for returning proper settling time
of regulator rails when it is enabled.
Filling the on-time for each rail as per tps65910/tps65911
datasheets.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 0651eed5e094a079a0a9fccd80a41cb3e7f2aa99)

Change-Id: Ibdb05171cfb4c4e7a064c8f65193647997e8e9a8
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90517
Reviewed-by: Automatic_Commit_Validation_User

regulator: Fix the logic of tps65910_get_mode

We actually clear LDO_ST_ON_BIT for standby mode in tps65910_set_mode.
Fix the logic in tps65910_get_mode.

Supply state (EEPROM bits):
ST[1:0] = 00 : Off
ST[1:0] = 01 : On high power (ACTIVE)
ST[1:0] = 10 : Off
ST[1:0] = 11 : On low power (SLEEP)

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 585993932ccc44ab6a8c6dc590a2f3d6b2facb41)

Change-Id: I1cb46d05396a286ba34c84b1836b9070f0f78003
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90516
Reviewed-by: Automatic_Commit_Validation_User

regulator: Rename set_voltage_sel callback function name to *_sel

This change improves readability.

Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cherry-picked from mainline
94732b97c39859427cf99c34fc9de9750be7e5a5

Change-Id: Ie3eb5462a99cceab40ba0e26e4e3cdb93c5f3f0f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90515
Reviewed-by: Automatic_Commit_Validation_User

arm: tegra: p1852: Add proc interface for board specific info

1) /proc/board_serial will have the board serial number.
2) /proc/skuinfo will have 18 character sku information.
3) /proc/skuver will have 2 character sku version number.
4) /proc/prodinfo will have product information
5) /proc/prodver will have product version number.

bug 931053

Change-Id: I7daccf932d3ee55b13c89eb4aaa519f51d8dba3e
Signed-off-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-on: http://git-master/r/90378
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arm: tegra: p1852: instantiated audio drivers

Instantiated audio drivers for I2S and AHUB.
Instantiated the machine driver for P1852 boards.
Added clocks that were not initialized by QB which are needed to be on.

Bug 948478

Change-Id: I6e696f97ed114ae684a74d9b9869066606dfaa22
Signed-off-by: Nitin Pai <npai@nvidia.com>
Reviewed-on: http://git-master/r/90252
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Tested-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>

iommu: tegra/gart: use correct gart_device

Pass the correct gart device pointer.

Change-Id: Ia54c3df7ce013855bf8843161f5ee0816482bda6
Reviewed-on: http://git-master/r/90064
Reviewed-by: Vandana Salve <vsalve@nvidia.com>
Tested-by: Vandana Salve <vsalve@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

ARM: tegra3: cardhu: Enable TPS65910 configs

In order to use the mainline tps65910 driver for PMIC and
getting rid of NV's tps6591x driver, enabling config
variable for TPS65910 mfd and regulator driver.

bug 927501

Change-Id: I0dc30b248f648d554024adfdf7beb2dc3db7e844
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90049
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arm: tegra: configs: Enable LTR558 ALS

Enable CONFIG_SENSORS_LTR558 for Ambient Light and Proximity Sensor.

Bug 901133

Change-Id: I66245046add9ada58064490fa154c9b2190e15b9
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/89994
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

video: tegra: host: disable 3d powergating

this is a workaround for the SLI scissor bug which can happen
intermittently.

Bug 914785

Change-Id: I5b7071df5bbfdd03bfe8b6f6b12ac7279221bd4e
Signed-off-by: Donghan Ryu <dryu@nvidia.com>
Reviewed-on: http://git-master/r/87968
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

ARM: tegra: fuse: Implement caching of fuse sku_id

In place of reading the sku id from the fuse every time,
read once and stored it for future use.

Based on orginal change from Simon Je's
http://git-master/r/#change,51502

bug 950922
bug 949620

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/89647
(cherry picked from commit 8eda0d2b574f7dda5975115ba6990790a2d4e1cc)

Change-Id: I4aed1a7c34008b4b3f4df17f7a41e3446ad8fe4f
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90305
Reviewed-by: Automatic_Commit_Validation_User

spi: tegra: Make sure SCLK frequency to be in minimum require value.

Making sure that SCLK frequency should be maintain on minimum
require value during spi transfer. This is require to proper
functioning of spi controller.

bug 949393

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/89526

Cherry-picked from commit
7d83f658b39b2ab1a5105eec7649246fddea7325

Change-Id: I60fa0fef98e5f2882c646c29e1773194deddd6da
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90296
Reviewed-by: Automatic_Commit_Validation_User

ARM: tegra: common: Set SCLK to 40MHz for spi

Setting sclk frequency for spi to 40MHz.

bug 949393

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/89525
cherry-picked from
171f5693e4137e9fe5a8b4e496c0c5db3b7838f1

Change-Id: I34808a64b834111dfff1592dd9244a45e9d3312c
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90295
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

video: tegra: dsi: Add checks to dsi for HOST1X power

Add checks to ensure host1x is powered when DSI is used.

Change-Id: I2e61abdd5c0741571fb18262fd2efa16ffee71d9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/86361
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

ARM: tegra: clock: Entry for spi-sclk clock control

Tegra's spi requires some minimum sclk clock frequency for
proper functioning.
Making entry for spi-sclk clock so that spi driver can get the
proper clock for controlling the minimum rate of sclk.

bug 949393

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/89524
(cherry picked from commit 542cbe457b1b19b8fdf8cbf193e38a00027060c2)

Change-Id: I3f829b36b1b42bb8b1c6e4e21745855e113c17c1
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/90294
Reviewed-by: Automatic_Commit_Validation_User

Revert "crypto: testmgr: add support for aes ofb mode"

This reverts commit 2afef0391f30a2831f8beed6a89351682c8a81f6.

Change-Id: Ieef8fd28ba78334a4a0a1b7c64ba6fd4d0f4cb05
Reviewed-on: http://git-master/r/90082
Reviewed-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Tested-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

video: tegra: host: Refactor context handling logic

Currently nvhost hard codes usage of context handler and sync point
id. Split the context handler and context structures into generic and
host1x specific parts, and move the allocation to happen via a
function pointer in nvhost_device.

Also updates gr3d and mpe to use sync point id and waitbase from
nvhost_device.

Bug 926690

Change-Id: I7f00b450cac99f3816baa27b37ee4e4cf68cfe24
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/84901
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

arm: config: tegra3: enable wl12xx gps char driver

Bug 933797

Change-Id: I13c066f9902af43e1958a445dcb2b8e710b6e644
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: http://git-master/r/90117
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

video: tegra: nvmap: Fix issue in handle_page_alloc

Fix race condition in handle_page_alloc. Page allocations
should not try allocate from pool, once it fails for a
request. If it tries and allocation passes during subsequent
attempts, the page_index is not valid for CPA and cache won't be
flushed for all the necessary pages.

Change-Id: I5548e11b713f271cc8473a3f2ae193a69e832f99
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/89611
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

GPS: GPS Char Driver for Texas Instrument's Connectivity Chip.

This enables the GPS driver for TI WL128x BT/FM/GPS combo devices.
It will provide a character device for the TI GPS host software to
access the GPS core on the WL128x.
Bug 933797

Change-Id: If0ea53a1b246a88fc895a95599d8bd38689b72fc
Signed-off-by: Satish Chandra <x0141690@ti.com>
Reviewed-on: http://git-master/r/90110
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Maria Bornski <mbornski@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

net: wireless: bcmdhd: disable WLC_E_TXFAIL event.

In suspend mode WLC_E_TXFAIL event is causing autowake
when the device is connected to an AP,so discarding the
WLC_E_TXFAIL event initialization as per BRCM team suggestion.

Bug 880970
Bug 941420

Change-Id: I5db727004873a77b8b264e7dde2525e678519c54
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: http://git-master/r/90074
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arm: tegra: cardhu: registering ALS based on board sku

If board_info.sku is 0xb11 this board has ltr558 ALS on it
else isl29028 sensor.

Bug 901133

Change-Id: Id0fb5b59b55393e52147e7f9d8d114651a5e0561
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/89977
Reviewed-by: Automatic_Commit_Validation_User

power: smb349: fix otg driver callback function

Allows OTG enable/disable only while USB OTG state
swithes between SUSPEND and HOST

Bug 937188

Change-Id: If651dfb19db37f8822e6d1473aa573246aca8d45
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/89111
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

ARM: tegra: defconfig: disable kernel debug features

Following debug features are disabled:

- DETECT_HUNG_TASK
- DEBUG_SLAB
- DEBUG_MUTEXES
- DEBUG_SG

This helps in CPU performance boost. Most of these were already
disabled for tegra3.

Reviewed-on: http://git-master/r/76534
(cherry picked from commit 3ba53a37cfc02b44fe12db03a786b59b82152efd)

Change-Id: Ia1725b9f86d2d3132ecc77b826c70364cc9bca01
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/90065
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

video: tegra: hdmi: validate clocks per frame of HDMI mode

There are HDMI modes which have different margin/sync values
although resolution and pixel clock are the same. One example
is 1080p/24Hz and 1080p/30Hz case.

Those modes are not distinguished when we check if given two
modes are equal. So clocks per frame also should be validated
to decide sameness of the modes.

Bug 950935

Signed-off-by: Youngjin Kim <nkim@nvidia.com>
Reviewed-on: http://git-master/r/89026
(cherry picked from commit b9e6316850a47445be7545aaec85c6a247c44cb9)
Change-Id: I06d3c0f41e63d65f1908614d09df4d16028895f0
Reviewed-on: http://git-master/r/90030
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

ASoC: Tegra wm8903 machine: suspend/resume code for HP detection

Suspend and resume code included for headphone detection. Earlier,
it was causing problem in HP detection when device enters into LP0
state and headphone is plugged in. (Bug 937153)

Change-Id: If625f0e7b857b40b0535f8bc8d1c262650886fa7
Signed-off-by: Ankit Gupta <ankitgupta@nvidia.com>
Reviewed-on: http://git-master/r/89975
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

arm: tegra: kai: ehci0 USB host default enable

set ehci 0 USB host mode to default enable

Bug 937188

Change-Id: I89a3886df7b9a6574ab9f293e5b6164007990be4
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-on: http://git-master/r/89968
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

arm: tegra: enterprise: Add rated refresh rate for one-shot mode.

Bug 946370
Bug 934977

Change-Id: I33d1b15dc3d7612f44e79da04a13bae6d3446dc7
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/89879
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

ARM: kernel: flush console and disable irqs before machine_shutdown

Bug 952455

Change-Id: I7400b519eccb274c1b5251032696e10e16ee1c42
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/89876
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

ARM: tegra: use common console flush on reboot

Bug 952455

Change-Id: I5272bdf2fc726994f3a22fd42671bb807bc30a21
Signed-off-by: Tom Cherry <tcherry@nvidia.com>
Reviewed-on: http://git-master/r/89875
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

video: tegra: dc: Add rated refresh rate for one-shot mode.

We add this variable for two purposes. First, it would remind developer
to make sure actual refresh rate is larger than rated refresh rate.
Second, gralloc would read rated refresh rate for one-shot mode since
actual refresh rates of most devices are expected running at rated
refresh rate.

Bug 946370
Bug 934977

Change-Id: Ib4121337df1a388b40440b22687c39f373f08890
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/89871
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

video: tegra: dsi: Add phy timing check for hblank

Horizontal blank must be greater than phy timing for
HS transmission.

Bug 938043

Change-Id: I5afe68ec04341f7b83c2897c586d4618bd518222
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/89789
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

video: tegra: dsi: Fix phy timing HW increment

Adding support to accomodate hw increment to
phy timing reg values.

Bug 938043

Change-Id: I8de14648c0994b03c37a2ee455a656ff11c3cc34
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/89741
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

ARM: tegra: clock: Add tegra_cpu_user_cap_set function

To set cpu_user_cap in tegra drivers, added tegra_cpu_user_cap_set
function.

Bug 945552

Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/87109
(cherry picked from commit db954aafdfdbe1fa122466b8e8ec4ea4273efb90)

Change-Id: I765c44de4ed4ae908ef56914db53533605bd6d88
Reviewed-on: http://git-master/r/89740
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

video: tegra: host: Replace license information

Replace license information in nvhost with GPLv2. Also adds
copyright year 2012 in files which have been changed in 2012.

Change-Id: I86e8ed27095df13d99e0250e57e244d531fdacec
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/89735
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

ARM: tegra: power: Set awake system CPU rate floor

Set CPU rate floor to 100MHz when the system is awake (after boot,
or on late resume). Remove the floor when the system enters early
suspend.

Bug 922351

Change-Id: Ibaca50791a5b04b4b4165ceac5018d4cfd7c1bcf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/89587
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

power: max17048: update charging status at probe

Add update charging status at probe to fix unknown charging status.

Bug 951750

Change-Id: I5d828b38adfe74531925be4356d50214f8f8522e
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-on: http://git-master/r/89437
Reviewed-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

power: smb349: add callback to update charger

Add update_charger_status() function callback to fix unknown
charging status at start up issue.

Bug 951750

Change-Id: Ib264479b0a251a07d136c245afa85c3444754ee0
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-on: http://git-master/r/89436
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

video: tegra: host: Disable irq on shutdown

Disable interrupts when driver is being removed.

Bug 952600

Change-Id: I1d697c3c87aca935deadfe20b5e8fa8852b0e556
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/89405
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>

arm: tegra: kai: add ti_bluesleep support

Add ti_bluesleep support
Remove plat_kim_suspend and plat_kim_resume
Remove return from functions with void return type

Bug 933054
Bug 931931

Change-Id: I847e39de7444fe62ecd91f5e039f7b85ca64f1cf
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: http://git-master/r/89284
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Tested-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

arm: config: tegra: enable BT_TIBLUESLEEP

Bug 933054
Bug 931931

Change-Id: I3875000a1b109e3180d8f7481efc9b3083358bd8
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: http://git-master/r/89281
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

misc: bluetooth: clean ti_bluesleep patch

Remove dead code
Remove whitespace
Remove platform callback function and add wake_lock/wake_unlock
Fix compilation warnings

Bug 933054
Bug 931931

Change-Id: I5b0947ad2053f9e0437ffe89879df2c84786ec9c
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: http://git-master/r/89274
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Tested-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

cpufreq: Add a knob to treat IO wait as busy

The new sysfs node io_is_busy enables the interactive governor to
account any time spent by the CPU waiting for IO as non-idle time.
This helps us improve run-time of IO bound tasks by making up for
lost IO time in speeding up the CPU bound parts of the task.

Reviewed on http://git-master/r/#change,86894
cherry picked from 13a15aadc1134b5dae05cdcf9687396644f87411
Signed-off-by: satya popuri <spopuri@nvidia.com>
Change-Id: I4a14ed7fef5fbce00054bb02d52d2d3e0f011f70
Reviewed-on: http://git-master/r/89218
Reviewed-by: Satya Popuri <spopuri@nvidia.com>
Tested-by: Satya Popuri <spopuri@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

cpufreq: change min_sample_time

We prefer a min_sample_time of 30ms. This is tied to our cluster switch
and auto-hotplug artificial delays.

Signed-off-by: satya popuri <spopuri@nvidia.com>
original commit message:

cpufreq: reduce min_sample_time

Reduce the minimum amount of time the interactive governor spends at a
frequency before ramping down. This parameter (min_sample_time) was 80ms
now reduced to 30 ms based on perf and power sweep numbers.

Reviewed-on: http://git-master/r/86900 (cherry picked from commit
581f20a5b7b8c3e4ee2c211b28dbc81510af2ae7).
Signed-off-by: satya popuri <spopuri@nvidia.com>
Change-Id: I24f4cd52737950fd4e78a36b4ee34a84551e0e12
Reviewed-on: http://git-master/r/89217
Reviewed-by: Satya Popuri <spopuri@nvidia.com>
Tested-by: Satya Popuri <spopuri@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

TI Wl128x support of bluesleep & Wake on BT Driver changes

Bug 933054
Bug 931931

Change-Id: Id84bcc1791114a50d26547de41daeb4774f6026b
Signed-off-by: Anjan Rao <anjan.rao@ti.com>
Reviewed-on: http://git-master/r/89136
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Tested-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

power: smb349: set PGOOD to active low at OTG

1. Turn PGOOD to active low when OTG is enabled
2. Free irq in error handling and smb349_remove

Bug 937188

Change-Id: I94a58c8dfd9066034335ec4507b80d1607fe029f
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-on: http://git-master/r/89028
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>

dtv: Added description for interface configuration

fixed bug 947324

Change-Id: Ib85ee5d7e67def321cbde49ad41e2b194e1bd2e8
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/86483
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

rtc: max77663: Use alrm->enabled flag to enable rtc alarm irq

Use alrm->enabled flag to enable rtc alarm irq in rtc_set_alrm function.

Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/88048
(cherry picked from commit 41e8686fc049fbdc0e83ecfa3f68da06ff813b99)

Change-Id: Ieb3b9863233b9d5bfc06459ef479c47a5e700d3b
Reviewed-on: http://git-master/r/89739
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

rtc: max77663: Update read buffer before read RTC IRQ status register

To get actual current RTC IRQ status, it have to update read buffer
before read RTC IRQ status register.

Bug 918156
Bug 924219

Signed-off-by: Jinyoung Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/88037
(cherry picked from commit 50528b7d136624ef0014deecba18d7bd9b8d8cc8)

Change-Id: I5ffcc9b24fec0f3688f641ab9f7cf82a69d77aeb
Reviewed-on: http://git-master/r/89738
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

arm: tegra: ventana: use fixed regulator instead of direct gpio

Bug 925547

Change-Id: I81f87cef3a9767d9bd60b72e33a23620392ab5fc
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/89736
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

ASoC: tegra: p1852: Add P1852-board machine driver

Added machine driver for P1852 board.
The driver supports a plug/play architecture where the
details of the codec_driver/codec_dai will come from the top level
board config file.

Bug 948478

Change-Id: Id34a34b224e02b61475ca17253c1b13893a09e6c
Signed-off-by: Nitin Pai <npai@nvidia.com>
Reviewed-on: http://git-master/r/89474
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

arm: tegra: add support for P1852 machine driver

Added support for the platform data that needs to be passed for the
ASoC P1852 machine driver

Bug 948478

Change-Id: Iac2c0310bf87ceddb892fd4b1ed3c0890558f97b
Signed-off-by: Nitin Pai <npai@nvidia.com>
Reviewed-on: http://git-master/r/89473
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

ARM: tegra: power: Boost CPU rate before device resume

Boost CPU frequency in tegra platform resume finish phase, just
before driver resume. Boost level is specified by platform suspend
data (ignored if 0).

Bug 946301

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit eaedf228861e4456454ca13f0958ed97e799fc59)

Change-Id: Ica0cff28f9651e38787ec98f54563d95d876d79e
Reviewed-on: http://git-master/r/89353
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

ARM: tegra: power: Use CPU G mode in suspend prepare

Switch to CPU G mode in Tegra3 suspend prepare if CPU suspend
rate is high enough. By symmetry, it guarantees that device
resume will be happening in G mode as well.

Bug 946301

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 082be3604056c39442e1b42f5cfceeb089ffdaae)

Change-Id: I42e37ce8847e4916dd0fca9e4bd44096b65f7032
Reviewed-on: http://git-master/r/89352
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

ARM: tegra: clock: Update Tegra3 CPU suspend rate

Set Tegra3 CPU suspend entry rate to maximum LP mode rate - speed up
suspend, and still allow to switch to LP CPU mode on suspend entry.

Bug 946301

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5e7fa33ebcb5602093f9bf86e37f0478e389c633)

Change-Id: I5df4305579a9992817bae168925c4bb208934481
Reviewed-on: http://git-master/r/89351
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

video: tegra: dc: Fix the EMC bandwidth clear.

Bug 951626

Change-Id: Ia7c7474aa0f066cba8bd1519a98e302c4b3992e0
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/89076
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

tegra2: dvfs: enable dvfs for sdmmc

Enabled dvfs table for sdmmc clocks

bug 893886

Reviewed-on: http://git-master/r/82687
(cherry picked from commit 45c6c0426fdde8d338d10029cc83b598e7e49e61)

Change-Id: I26e07b45ef6331b99c57dd792ad0cc66a94242fb
Signed-off-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-on: http://git-master/r/89410
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

tegra: usb: host: Fix the race condition in hub control

Fix the race condition in tegra_ehci_hub_control which
is causing the usb not to work on usb instance 1.

Bug 948702

Change-Id: I3e8c7ecc90ee1ec96642292f9a83b09c413e9400
Signed-off-by: vjagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/89002
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>

ASoC: Tegra wm8903 machine: Fix to control names

Fixing the typos in the member of cardhu_controls.

Bug 946932

Change-Id: I26f2a5a60f40d55846a89aaa76dab00741e018d0
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: http://git-master/r/88824
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

arm: tegra: cardhu: properly map volume, back, menu GPIO keys

Specify proper GPIO pin assignments for volume up/down, back and menu keys.

Bug 915638

Change-Id: I8898aed002a0e9b6e4bd389fb1813cabb7f13c65
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Reviewed-on: http://git-master/r/86221
Reviewed-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Tested-by: Ashwini Ghuge <aghuge@nvidia.com>

arm: tegra: xmm: add usb interface check

BUG 928909

Signed-off-by: Xin Xie <xxie@nvidia.com>
Reviewed-on: http://git-master/r/82756
(cherry picked from commit f24375055ecba7c40c740a6b88ad03e38ea8b10c)

Change-Id: I2b3d59ea433555f595a1468cae3242b7dc54958a
Signed-off-by: Xin Xie <xxie@nvidia.com>
Reviewed-on: http://git-master/r/89565
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Steve Lin <stlin@nvidia.com>

ARM: tegra: pm: only identity map lowmem area

Bug 941380
Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/87095
(cherry picked from commit 72b72afb18f852ee0b352b0644bf30b4afeaa055)

Change-Id: I7e10b6180044a6fb58b2fee835991812c193d9b1
Reviewed-on: http://git-master/r/89564
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>