video: tegra: dtv: Remove check for dma req list before cancelling
Removing the checking whether dma req queue is empty or not
before canceling/stopping dma.
This function cannot guarantee correct result as there may be the
race between hw and sw status update.
If client wants to cancel dma req, it can directly call tegra_dma_cancel().
As the function tegra_dma_is_empty() does not return correct result,
it will be depreciated from the dma apis.
Alok Chauhan [Fri, 17 Feb 2012 09:47:38 +0000 (15:17 +0530)]
regulator: max8907: Add driver specific data for regulator
Adding the regulator driver specific information and passing
this information through regulator driver data. This struture
is containing delay operation which is require to voltage to
be settle down after enabling rail.
- as of now the resources needed by all the host1x
modules are part of resource list of host1x device
- now that each module is a nvhost_device of its own,
so it should hold the resources it needs instead of
host1x device holding it for them
- each device that needs its resources gets it in its
_probe() using a helper API in bus_client.c
arm: tegra: p1852: Use GMI to untristate gpio X5/6
Using SPI1/SPI2 as initial pinmux for gpio X5/6 affecting spi
controller. GMI A26/27 can be pinmuxed for SPI1_CS0 and SPI1_SCK balls.
It will not affect GMI behavior because A26/27 presently not used on
p1852.
Following tegra USB UTMIP issues are fixed:
1. Clear run bit directly in the command
register instead of updating the shadow variable.
2. Reset EHCI while resuming from LP0 for
tegra 2.
3. Wait for 25ms to ensure port is resumed.
Following tegra 2 UTMIP issues are fixed:
1. Remove unnecessary register programming
for tegra 2 while enable/disable OBS bus.
2. Clear run bit while disabling OBS bus.
Jon Mayo [Tue, 27 Mar 2012 20:55:31 +0000 (13:55 -0700)]
video: tegra: dc: avoid overflow in bw calculation
Change to using kbytes/sec to avoid overflowing 32-bit integer in
bandwidth calculation.
Changing efficiency adjustment to ~35%.
Bug 958016
Change-Id: Ia8bdf79e4b3e4bc65517db18d9f351a5f840805e Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/92658 Reviewed-by: Automatic_Commit_Validation_User
Commit d4c9c46147102dfc403691ed52609ae36ba5df08 moved
irq_enter()/irq_exit() calls around. This caused
irq_enter()/irq_exit() for ipi_timer() to be missing
when ipi_timer() was called from local timer IRQ.
Add the missing calls.
Context handler init functions are referred to from non-init section.
The functions should not have __init attribute, even though they're
only used in init time.
Thomas Gleinxer [Fri, 14 Oct 2011 11:44:41 +0000 (12:44 +0100)]
ARM: 7133/1: SMP: fix per cpu timer setup before the cpu is marked online
The problem is related to the early enabling of interrupts and the
per cpu timer setup before the cpu is marked online. This doesn't
need to be done in order to call calibrate_delay().
calibrate_delay() monitors jiffies, which are updated from the CPU
which is waiting for the new CPU to set the online bit.
So simply calibrate_delay() can be called on the new CPU just from
the interrupt disabled region and move the local timer setup after
stored the cpu data and before enabling interrupts.
This solves both the cpu_online vs. cpu_active problem and the
affinity setting of the per cpu timers.
Change-Id: I3ce734e674715f59d057a76821fc5f93706b875f Signed-off-by: Thomas Gleinxer <tglx@linutronix.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/87227 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
Russell King [Mon, 20 Jun 2011 15:46:01 +0000 (16:46 +0100)]
ARM: SMP: wait for CPU to be marked active
When we bring a CPU online, we should wait for it to become active
before entering the idle thread, so we know that the scheduler and
thread migration is going to work.
Change-Id: I0fa128768f575ddd0a5d976be66869dbd88f355e Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/87226 Reviewed-by: Simone Willett <swillett@nvidia.com> Tested-by: Simone Willett <swillett@nvidia.com>
Varun Wadekar [Fri, 30 Mar 2012 04:13:40 +0000 (09:43 +0530)]
ARM: tegra: rethink the cpu suspend-resume code path
The current kernel methodology expects that tegra_cpu_suspend
is actually the last function in the entire suspend sequence.
In order to achieve this, the code needs to be remodelled a
bit so that we actually execute native cpu_suspend at the end
of the suspend sequence. This allows us to leverage all the
cpu_suspend code developed by ARM in the upstream kernels.
Russell King [Thu, 1 Sep 2011 10:57:59 +0000 (11:57 +0100)]
ARM: pm: add L2 cache cleaning for suspend
We need to ensure that state is pushed out from the L2 cache when
suspending so that the resume paths can access their data before the
MMU and caches have been re-initialized. Add the necessary calls to
__cpu_suspend_save().
Change-Id: Idf7516347478731b722e62a37b5cc9f1c52be68e Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85729 Reviewed-by: Automatic_Commit_Validation_User
Russell King [Thu, 1 Sep 2011 10:52:33 +0000 (11:52 +0100)]
ARM: pm: convert some assembly to C
Convert some of the sleep.S guts to C code, which makes it easier to
use our macros and to add L2 cache handling. We provide a helper
function, __cpu_suspend_save(), which deals with saving the common
state, setting up for resume, and flushing caches.
The remainder left as assembly code is the saving of the CPU general
purpose registers, and allocating space on the stack to save the CPU
specific registers and resume state.
Change-Id: I0e8bc196fa7302cfe52c17d39675dadf25ea1004 Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85728 Reviewed-by: Automatic_Commit_Validation_User
Russell King [Sun, 28 Aug 2011 09:30:34 +0000 (10:30 +0100)]
ARM: pm: no need to save/restore context ID register
There is no need to save and restore the context ID register on ARMv6
and ARMv7 with a temporary page table as we write the context ID
register when we switch back to the real page tables for the thread.
Moreover, the temporary page tables do not contain any non-global
mappings, so the context ID value should not be used. To be safe,
initialize the register to a reserved context ID value.
Change-Id: I7de05e736dde5bc1b8ab682a8660eaaba52104cf Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85727 Reviewed-by: Automatic_Commit_Validation_User
Russell King [Wed, 31 Aug 2011 22:26:18 +0000 (23:26 +0100)]
ARM: pm: get rid of cpu_resume_turn_mmu_on
We don't require cpu_resume_turn_mmu_on as we can combine the ldr
instruction with the following code provided we ensure that
cpu_resume_mmu is aligned for older CPUs. Note that we also align
to a 32-byte boundary to ensure that the code can't cross a section
boundary.
Change-Id: I356eeff464eec48d167d98ee45b80b300d7c4c99 Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85726 Reviewed-by: Automatic_Commit_Validation_User
Varun Wadekar [Tue, 27 Mar 2012 11:56:39 +0000 (17:26 +0530)]
ARM: pm: only use preallocated page table during resume
Only use the preallocated page table during the resume, not while
suspending. This avoids the overhead of having to switch unnecessarily
to the resume page table in the suspend path.
Change-Id: Ib71c9b60b0ec39749aadc6f592549d213e6a852e Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85725 Reviewed-by: Automatic_Commit_Validation_User
Russell King [Fri, 26 Aug 2011 19:28:52 +0000 (20:28 +0100)]
ARM: pm: preallocate a page table for suspend/resume
Preallocate a page table and setup an identity mapping for the MMU
enable code. This means we don't have to "borrow" a page table to
do this, avoiding complexities with L2 cache coherency.
Change-Id: I625d3622359e961e4f358171e9a82b51bcecf9c2 Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/85671 Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra: Enterprise: Provide settling time for 3.3 Voltage rail
It is observed that voltage rails for 3V3 is taking around 400us
for setting it output. Providing the startup delay of 500us for this
rail so that rails are stablized at desired level before any consumer
uses that rail.
Wolfram Sang [Tue, 25 Oct 2011 13:16:47 +0000 (15:16 +0200)]
lib: devres: add convenience function to remap a resource
Almost every platform_driver does the three steps get_resource,
request_mem_region, ioremap. This does not only lead to a lot of code
duplication, but also a huge number of similar error strings and
inconsistent error codes on failure. So, introduce a helper function
which simplifies remapping a resource and make it hard to do something
wrong and add documentation for it.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Tejun Heo <tj@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
(cherry picked from mainline commit 72f8c0bfa0de64c68ee59f40eb9b2683bffffbb0)
dmaengine: add context parameter to prep_slave_sg and prep_dma_cyclic
Add context parameter to device_prep_slave_sg() and device_prep_dma_cyclic()
interfaces to allow passing client/target specific information associated
with the data transfer.
Modify all affected DMA engine drivers.
Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Cherry-picked from mainline 185ecb5f4fd43911c35956d4cc7d94a1da30417f
Add inline wrappers for device_prep_slave_sg() and device_prep_dma_cyclic()
interfaces to hide new parameter from current users of affected interfaces.
Convert current users to use new wrappers instead of direct calls.
Suggested by Russell King [https://lkml.org/lkml/2012/2/3/269].
Vinod Koul [Thu, 13 Oct 2011 09:45:27 +0000 (15:15 +0530)]
dmaengine: add new enum dma_transfer_direction
This new enum removes usage of dma_data_direction for dma direction. The new
enum cleans tells the DMA direction and mode
This further paves way for merging the dmaengine _prep operations and also for
interleaved dma
Suggested-by: Jassi Brar <jaswinder.singh@linaro.org> Reviewed-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
Cherry-picked from mainline 49920bc66984a512f4bcc7735a61642cd0e4d6f2
- current code does not turn off pll-a/p in LP1
irrespective of voice call status
- add a new flag to indicate voice call on-going
- use PMC_SCRATCH37 to hold this flag
- if it is set, do not turn-off pll-a/p during LP1
- save-restore PMC_SCRATCH37 if it was used to hold the
voice call on-going flag
- fix few misc formatting issues in tegra3_cpu_clk32k
tegra_audio: add default implementation for tegra_is_voice_call_active()
- mods kernel do not enable audio related configs in kernel
- tegra_is_voice_call_active() is defined only when audio
related configs are enabled
- this commit adds a default implementation for tegra_is_voice_call_active()
which can be called from generic pm code in mach-tegra
- it also makes the default implementation inline
CSUS clock can't be driven from any clk other than clk_m. So
updating its parent to clk_m.
Removing pll_m's entry as it's already enabled and running at
666 MHz which is our requirement.
Removing tegra_init_suspend() as it's not needed on p852.
The gpio_switch regulator is NV driver developed during
tegra3 bringup time. The driver functionality is upstreamed
to mainline into fixed regulator and it is accepted by community.
The required functionality is also downstream and required client
driver is moved to use the fixed regulator. Hence this driver
is just duplicating functionality with fixed regulator and hence
removing this.
ARM: tegra: cardhu: Use fixed regulator for open drain gpio
The gpio regulator which is controlled through the gpio, which
is open drain type, is using the gpio_switch regulator.
The open drain support is added into the fixed regulator
and hence moving the regulator to use fixed regulator.
Print only a warning message if vdd regulator is not registered.
Some board do not have a seperate vdd regulator and hence
print only a warning message in such cases.
Daniel Solomon [Sun, 1 Apr 2012 20:51:18 +0000 (13:51 -0700)]
ARM: tegra: kai: Update measured backlight output
Update measured backlight output for correct linearization.
Bug 962780
Change-Id: Ic35b159a0b951eafff7890e7a7487f3c94b468e8 Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/93744 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hu He <hhe@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Adam Jiang [Thu, 8 Mar 2012 12:34:53 +0000 (21:34 +0900)]
dc: enabled recovery from resetting
Enabled recovery of DC from resetting. When underflow triggered serveral
times(current > 4 for tegra2), DC driver will reset itself to prevent
data corruption. Reopend nvhost connection when resetting finished. That
helps system to show frames instead of a blank screen again.
Alex Frid [Fri, 9 Mar 2012 23:07:00 +0000 (15:07 -0800)]
ARM: tegra: clock: Set EMC and SCLK rates suspend floors
- On suspend entry set EMC rate floor high enough to select PLLM as
EMC clock source, since PLLM is always turned off in suspend.
- On suspend entry set SCLK (AVP) rate floor to speed-up system bus
during save/restore procedures.
Laxman Dewangan [Wed, 7 Mar 2012 10:28:33 +0000 (15:58 +0530)]
regulator: fixed: Support for open drain gpio pin
Adding flag on fixed regulator board configuration structure
to specify whether gpio is open drain type or not.
Passing this information to gpio library when requesting
gpio so that gpio driver can set the pin state accordingly,
for open drain type:
- Pin can be set HIGH as setting as input, PULL UP on
pin make this as HIGH.
- Pin can be set LOW as setting it as output and drive to LOW.
The non-open drain pin can be set HIGH/LOW by setting it to
output and driving it to HIGH/LOW.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
cherry picked from mainline commit a4d9f179cc788b7f4b735d32c2e4a3b2562e8240
- remove redundant 2nd argument to nvhost_module_suspend()
- also remove the debug_not_idle() as it redundant after
refactor of host1x code
- debug_not_idle() iterates through host1x's private instance
of channels to find out which client module is active (along
with host1x itself). we are going to remove these instances of
channels from host1x's device private data
- reduce the prints during suspend
Alex Frid [Sun, 1 Apr 2012 07:28:46 +0000 (00:28 -0700)]
ARM: tegra: clock: Fix emulation clock table
Configure PLLC on emulation platforms after SCLK is switched to PLLP.
This would avoid failure in case when emulation initialization script
set PLLC as SCLK source.
Change-Id: Ie0f48c066f6df7f6f3c67858de7e9d7608dcb7ff Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/93730 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Hoang Pham <hopham@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Manoj Chourasia [Wed, 21 Mar 2012 08:58:58 +0000 (14:28 +0530)]
ARM: tegra3: Make MC early ack feature configurable.
Add a config option to configure early acknowlegement
from memory controller.
Early acknowledgement is feature of memory controller
where MC acknowledged immediately to any write requests
from CPU. To maintain mermory coherency all the read
requests are blocked till all the early-acked writes
have reached to a point of coherency.
Viresh Kumar [Thu, 17 Nov 2011 10:31:29 +0000 (16:01 +0530)]
dmaengine/dw_dmac: Reconfigure interrupt and chan_cfg register on resume
In S2R all DMA registers are reset by hardware and thus they are required to be
reprogrammed. The channels which aren't reprogrammed are channel configuration
and interrupt enable registers, which are currently programmed at chan_alloc
time.
This patch creates another routine to initialize a channel. It will try to
initialize channel on every dwc_dostart() call. If channel is already
initialised then it simply returns, otherwise it configures registers.
This routine will also initialize registers on wakeup from S2R, as we mark
channels as uninitialized on suspend.
Now that we have the completed cookie in the dma_chan structure, we
can consolidate the tx_status functions by providing a function to set
the txstate structure and returning the DMA status. We also provide
a separate helper to set the residue for cookies which are still in
progress.
Everyone deals with assigning DMA cookies in the same way (it's part of
the API so they should be), so lets consolidate the common code into a
helper function to avoid this duplication.
dmaengine: move last completed cookie into generic dma_chan structure
Every DMA engine implementation declares a last completed dma cookie
in their private dma channel structures. This is pointless, and
forces driver specific code. Move this out into the common dma_chan
structure.
Laxman Dewangan [Thu, 29 Mar 2012 09:54:51 +0000 (15:24 +0530)]
mfd: max8907c: Do not use I2C_M_NOSTART in first message
It is not recommended to use the flag I2C_M_NOSTART in first
message.
The documentation kernel/Documentation/i2c/i2c-proocol says:
Flag I2C_M_NOSTART:
In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
point. For example, setting I2C_M_NOSTART on the second partial message
generates something like:
S Addr Rd [A] [Data] NA Data [A] P
If you set the I2C_M_NOSTART variable for the first partial message,
we do not generate Addr, but we do generate the startbit S. This will
probably confuse all other clients on your bus, so don't try this.
Chaitanya Bandi [Mon, 12 Mar 2012 10:48:07 +0000 (16:18 +0530)]
i2c: tegra: Avoid duplicate write into Tx fifo
Dvc I2C_DONE_INTR_EN interrupt bit is always enable into dvc
control register3. During normal transaction on dvc i2c bus
sometimes one transaction written two times in TX fifo buffer
because of triggered dvc interrupt. This is causing to corrupt
the next transaction header and send wrong address over dvc
i2c bus. To solve this issue dvc i2c interrupt has to disable
during filling of Tx fifo and enable after that.
Updated the following things in code:
(1) Add the code to mask/unmask I2C_DONE_INTR_EN into dvc control reg3
writing into Tx Fifo register.
(2) Put delay before resetting the controller