arm: tegra: enterprise: Enable battery charging based on kernel option

If kernel command line option have the power_supply as battery
then enable the battery charging functionality.

Reviewed-on: http://git-master/r/50673
(cherry picked from commit 4f36edabc585f3fea28e2f959558ac7e07dd2b5e)

Change-Id: I5a12105503f29e4e58991bcf4c020c709a97a7cd
Reviewed-on: http://git-master/r/56994
Reviewed-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Tested-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R9fa09e3c265fabefd14804def31100259bfd9730

arm: tegra: cardhu: Enable i2s3 and BT device

Enable i2s3 and bluetooth dit device for cardhu. Also add i2s2 clock in
clock table. It is needed to support BT SCO playback/record.

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: I3b702bbbd360db966447b099e982891383db27cd
Reviewed-on: http://git-master/r/62049
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R035bff07f147e9100956df6c238bf7df60d89e93

ASoC: Tegra: Add AHUB APIs to configure AHUB CIF channels

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: I0b777642681f5bf606a8faffb76142026902e538
Reviewed-on: http://git-master/r/62045
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Rebase-Id: R5bac01349656e799fed56b368265da13d6a4b02a

ASoC: Tegra: Support Tegra30 I2s DSP mode

Correct DSP-A/B mode logic and bitcnt calculation logic for DSP mode.
Also enable single slot for both I2s and DSP modes.

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: I9df935bfddde71b3c3a0df68cef73f530079176c
Reviewed-on: http://git-master/r/62024
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Sumit Bhattacharya <sumitb@nvidia.com>
Rebase-Id: R8ef4810768bbc7d3d091cc08054e952763d9087f

ASoC: tegra: Constraint period size to be multiple of 8

Constraint period size to be multiple of 8 as Tegra DMA double
continuous mode needs transfer size to be multiple of 8.

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: I848373d7d137200589c0ae3cd239cd2d29499d48
Reviewed-on: http://git-master/r/61914
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R49ecf7654c0d2e8d72bf1b6cb71d56cb66d37875

arm: tegra: clock: Change parent and init values

pll_m initialized to 0 so that it stays at the frequency configured
by BCT.

For AP25 pll_m runs at 760MHz. Peripherals connected to pll_m and
running at frequency not multiple of 760MHz switched to pll_c.

Bug 892505

Change-Id: Ie6abb47c4fac6d808aab5ed13a6b049c42126588
Reviewed-on: http://git-master/r/61491
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rcbbad7a6d277b7800e8e75962b96d533148fe1eb

ov5650: add fast set_mode

Resetting the mode does not need to reset all of the i2c
registers. This used to be called "fast set_mode". This
is added into the kernel driver in this change. This
change reduced 90ms from resetting the mode. It only
apply to still preview and capture resolutions

bug 816814

Change-Id: I2ff3ba13b2454a65ead4ce6ce290c5dd63713a10
Reviewed-on: http://git-master/r/61307
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rf030a95d60d4f319b160b1399b23119c6f6f18c2

ARM: tegra: gpio: Set a gpio to tristate or normal

Create mapping from gpio to pingroup and set gpio to
normal or tristate

Bug 866633

Reviewed-on: http://git-master/r/56557
(cherry picked from commit 321ded98d41170b9e32d60177c6808492ccdf115)

Change-Id: I3d1b979717f1c6b208af3df0a7dfe603e5272d21
Reviewed-on: http://git-master/r/61120
Tested-by: Bandi Krishna Chaitanya <bandik@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R5991c2cbc11aa35345fde7f08c0bfeb306e85e1e

media: video: tegra: ov5650: disable sensor soc AE

set the bits to enable manual control of AE and gains. Set
frame delay for application to 2 frames.

Bug 869749

Change-Id: I96c1aed6b4bd41dc3c1a3eb1ba8e158df31eaa32
Reviewed-on: http://git-master/r/57392
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit 543db4f05df3db2bfee4fc8bf8f6a7cec75dd91f)
Reviewed-on: http://git-master/r/57652
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-by: Robert Lin <robertl@nvidia.com>
Tested-by: Robert Lin <robertl@nvidia.com>
Rebase-Id: Rba4bb0b4496fd0ce9efa53d203a4ef38bf1605f9

sdhci: tegra: Don't use WARN_ON in error cases

Do not use WARN_ON when regulators are not found
as it would print the stack dump while booting. Use
dev_err to print the error message.

Change-Id: Ibe22cfe8d24719c2352084d7043f47d5203b84d0
Reviewed-on: http://git-master/r/61862
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R5f7ab8071b742843d960ce8b315e8095374af1b5

arm: tegra: fix compiler warnings

Reviewed-on: http://git-master/r/53296
(cherry picked from commit 12ed00a4b6024299617f7ff9cd2f0e718f5eb11e)

Change-Id: I5b5cf2d5f53ce83d0c278130db1b534eb8030b85
Reviewed-on: http://git-master/r/61687
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Redd22a72d2dc86d215c100f18eb5f4ad61467fd9

video: tegra: dsi: Fix value of PKT_WR_FIFO_SEL.

Bug 834959

Reviewed-on: http://git-master/r/54861
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit 8f2ce3c04c16331332d4ba12f097787fd82af2db)

Change-Id: I3e8c9039316459a563a432507e880c29f04260ba
Reviewed-on: http://git-master/r/61612
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Re5a1aab4caec5539d213697ed2cc90b2255a79be

ARM: tegra: enterprise: Increase refresh rate to catch up TE signal.

DSI clock rate is calculated according to the refresh rate 60Hz. However,
the real TE signal can be more or less than 60Hz. Increase refresh rate
to avoid missing TE signal.

Bug 878230

Reviewed-on: http://git-master/r/46455
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit c2081d32e93793bc5b16950a752367d31ab2d3d7)

Change-Id: I12d6e5cd363523bacd148eef72e22ba609ff1e83
Reviewed-on: http://git-master/r/61609
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rd9269b73fa432b176c609b872015dff81c3c51d0

ARM: tegra: enterprise: Fix backlight toggling on Enterprise.

Bug 873860

Reviewed-on: http://git-master/r/52178
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Robert Morell <rmorell@nvidia.com>
(cherry picked from commit 17efce7b49626cde29af8db695b18d4ab3db9099)

Change-Id: Ib168ef67c9cd7f6114da87da5a57c88ddd3abbb6
Reviewed-on: http://git-master/r/61608
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R184973927477f12329dbd1e8294e3d366dddf746

video: backlight: tegra: Add check_fb hook.

Bug 873860

Reviewed-on: http://git-master/r/52135
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Robert Morell <rmorell@nvidia.com>
(cherry picked from commit 92ec78210ee1526dc2c35b7775674105aa6f729b)

Change-Id: If8b1f7af86574af2158609742bc8e18a2585ad36
Reviewed-on: http://git-master/r/61607
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc3d4771e2f1c7250e7f8eacedfd7dad1790441b5

video: tegra: dsi: Adjust two CSI registers in DSI module.

Bug 829327

Reviewed-on: http://git-master/r/50871
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit 8d9aa14595348a2daa408710927471169447e73c)

Change-Id: Ib3e335dab5329ef29842354dc9934f8213ae3d58
Reviewed-on: http://git-master/r/61603
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R6ec4d12410e956f37db259fb337fd17d86622838

video: tegra: dsi: Adjust CSI register values to follow MIPI spec.

Bug 829327

Reviewed-on: http://git-master/r/50352
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
(cherry picked from commit 36eb87ff03c2bc6ee5b3821117b3afb225417034)

Change-Id: I1533f55d0817c76c3cd75890b13927b81a2f0c4b
Reviewed-on: http://git-master/r/61602
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R70593482503bd6de287d3cbf90e4b075c1cfb194

ARM: tegra: Add interface to read/write vi/csi module.

Bug 829327

Reviewed-on: http://git-master/r/50351
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Tested-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
(cherry picked from commit 43d66ead107fc584068e8b894ef0ccf067b78f35)

Change-Id: I466f8300ae8c8ade5f7ab2783baabe5e744da18a
Reviewed-on: http://git-master/r/61601
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R4aa7bd08edad8ad1cb81e5b04961d873e9d01b1a

ARM: tegra: power: Restore Tegra3 MC registers after LP0

On exit from deep sleep (LP0) restore from SDRAM Tegra3 MC registers
that are not saved in PMC scratch file for boot-rom restoration. Since
SDRAM after LP0 is running at boot rate, MC registers are saved only
once during initialization.

Bug 874351

(ported from commit 99966c242920978a92f3f51e5957ada30afc4b1d)

Change-Id: I9bf06ddb83fa6435a4f5bd29ec58bb195a189678
Reviewed-on: http://git-master/r/61045
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R272136c877818d44b0cf28f8b5f720af71623301

tty: serial: tegra: Avoid sleeping in atomic context

Avoid mutex_lock to be called in spin_lock conetxt.

Bug 890147

Reviewed-on: http://git-master/r/59545
(cherry picked from commit 7ebaaea25400d3708b6f3ac3585b61b65ab99a17)

Change-Id: I189dbf1ff3da5e7580b3688680565762fa457f6e
Reviewed-on: http://git-master/r/61871
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R167aaab6105b997d4a019c064ee5297e1982c5bb

video: tegra: dsi: Code clean-up

Fix indentation

Change-Id: I40edd117a454d0307e38bec93729cbe3f3fb86c5
Reviewed-on: http://git-master/r/61868
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Raeb8098dcf39d9a54208cee6ed14e754ea969a4f

video: tegra: host: Add timeout to low-pri throttle

Add timeout to throttling low-priority thread. Low priority threads are
allowed to push work either when push buffer is empty, or when they've
waited for a pre-defined period. Setting the period to 50ms for now.

Bug 864407

Reviewed-on: http://git-master/r/58330
(cherry picked from commit a9469db8c4c04fa7cd8f080bafdca26d99a3018c)
Change-Id: I5fa310acf6cf5563eda6b7343ad82679f76162af
Reviewed-on: http://git-master/r/61734
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R587f052c75a23b1a5a2349d4bf0feecc49cad898

ARM: tegra: power Limit CPU complex speed through sysfs

Added sysfs node /sys/module/cpu_tegra/parameters/cpu_user_cap to set
maximum CPU rate from user space. Unlike per-cpu frequency governor
limit (scaling_max_freq), this cap is applied directly to common CPU
complex frequency underneath per-cpu governors.

(cherry picked from commit 5fbd5b19ddb43a03391957000f23b729f394b05b)
(cherry picked from commit bf81c8efc2c98e5008527ce019669dc57718f44b)

Change-Id: Ic2f152e1fd58f2f0062489309c0cffd32a2462ae
Reviewed-on: http://git-master/r/61711
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R800c2a4d5e097bdd29fa1b0b901264a2723abff0

ARM: tegra: dvfs: Add dvfs table for Tegra3 x3 chips

Bug 841336

(cherry picked from commit fc2f899fe93cb4aea2e22c18d98b1b856429d572)
(cherry picked from commit 252d4bed817eec321dcefe9ba07c6f019b92f8f2)

Change-Id: I9522b1289dcd80c23ae47a6015521a85a3b954cc
Reviewed-on: http://git-master/r/61710
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R7ae4227a1a00ef79aa65018cb771b40c410050e3

ARM: tegra: clock: Increased Tegra3 CPU maximum rate

Increased maximum rate of CPU clock sources, and added cpufreq scaling
table to cover frequency range up to 1.7GHz for fast Tegra3 parts.

Bug 841336

(cherry picked from commit 4bb23d23321e976f08bb05b37df80e2b7df5a09c)
(cherry picked from commit ee9f100e74b7b6cf4428a1a7a66cc5f082fc6aae)

Change-Id: I4009f777793a6b78862f4712fcba6f435699e4eb
Reviewed-on: http://git-master/r/61709
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc1d6e48791296b07cab604843b65225a1b362dad

ARM: tegra: dvfs: Set Tegra3 VDD_CORE min to 1.1V

Change VDD_CPU and VDD_CORE dependencies so that VDD_CORE min is 1.1V
when G CPU is active.

(cherry picked from commit afdc5d559ef9630e412368492f85332d35468eca)
(cherry picked from commit 97c6508452b0e0f40179e8c62d84737839dc9ac2)

Change-Id: Ie038ac213c6a0cb817bb506fc3b925ab5e81c156
Reviewed-on: http://git-master/r/61708
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R4d9c5da8191468b56c16dae9f920194186454833

ARM: tegra: clock: Order memory and cpu clock updates

When voting on memory frequency based on cpu frequency, update memory
frequency before cpu frequency if cpu rate is increasing, and after cpu
frequency if cpu rate is decreasing (current code updates memory first
always).

(cherry picked from commit 9284039a4d86c22ee72e11d6c173b24a5b4f720e)
(cherry picked from commit 3cd676121913b1cd9eddff06d6966817dcd9de94)

Change-Id: I91b81f1eab91d575959a2fd9af3a8798f7ca6cf6
Reviewed-on: http://git-master/r/61707
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R64d5597f8360ca151ba5e017cb94915c63699aca

ARM: tegra: clock: Set Tegra3 2D/3D idle divisors

Enable 2nd level hardware controlled clock gating.

(cherry picked from commit 9dc6277e84a504d30dd5c07853301decf66c3060)
(cherry picked from commit 0f5ec1901932d78796e143c730ebd9e3f4ffc397)

Change-Id: I219a7fcd0e6ee47418cdd444cc101a1c6b266e1f
Reviewed-on: http://git-master/r/61706
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R65f5ecab707df40f9e98e954420245c9a4a2c476

ASoC: tegra machine: Correct spdif-dit codec name

Change SPDIF dai-link codec name from spdif-dit to spdif-dit.0 since
spdif-dit platform driver index has been changed from -1 to 0.

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: I3a234e237149607346301bf1f19d5a2e7f9e69b6
Reviewed-on: http://git-master/r/61509
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rdd42749aae8eb8f8eb5afbf541ba1f780fca9316

arm: tegra: ventana/whistler: Enable i2s2 and BT device

Enable i2s2 and bluetooth dit device for ventana and whistler platforms.
Also add i2s2 clock in clock table. It is needed to support BT SCO
playback/record on Tegra20.

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: I61f1f26cb502570ec5348137bbe0ac62e6c1f9e6
Reviewed-on: http://git-master/r/61504
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R424e4d712a1dd5f3647d2183c94138ef38e2ba4a

arm: tegra: Add dummy platform driver for BT and BB

Use dummy spdif-dit platform driver for bluetooth and baseband
platform driver.

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: I111e1f16d545d19b37c2a49c212160a210eea9f4
Reviewed-on: http://git-master/r/61503
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R058f68adf8951ba33dccdcaf6760875650de761e

ASoC: spdif: Add spdif dummy capture DAI

Add a dummy capture DAI to dit_stub_dai so that it can also be used
for audio capture path.

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: Ic7092931b02e323fa7ae07239d6a6e19880b6bc4
Reviewed-on: http://git-master/r/61481
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R2446d2806f96d0def7938a78a4117cdb69c22183

arm: tegra: Correct DAS base address

Bug 872652
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Change-Id: I27911d144c5636ce8be26c6c3830dea09b4a2cde
Reviewed-on: http://git-master/r/61234
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rb361a4da4573ba22c418a5c12fb820c9135292bb

asoc: max98088: set the dapm idle bias off flag

with the idle bias off flag set, dapm will turn
the codec bias off in standby

Bug: 862023

Change-Id: I21758bb08efbfba0e06dba5a129a57be38331cb9
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/61087
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc27d29eceff9ccfa2cf896b5aa08728b48cfe6f6

asoc: tegra: add code to enable/disable clocks

add code to enable/disable pll_a and cdev1 clocks

Bug: 862023

Change-Id: If5b6014f82651e2286802ba6d76f77b1b5419b41
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/61085
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rddb3206531e76e7ea28df691f6aa86a50f7c66d0

mfd: ricoh583: Correct typo in error message

Correcting typo in the error messages.

bug 822562

Reviewed-on: http://git-master/r/60414
(cherry picked from commit 0accfaa34f91a19ae2aa8eba1f9fc1853ee91576)

Change-Id: Id99fc31bf7c00cab452999c6d133125f16f04e76
Reviewed-on: http://git-master/r/61437
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: Rb88e19b9510813424033dee100dd3d10f75dca7a

arm: tegra: cardhu: Select debug console from kernel command line

Selecting debug console from linux command line.

bug 795847

Reviewed-on: http://git-master/r/51723
(cherry picked from commit ce5675f5a7607f9e549f84c42bea3df6f14c9008)

Change-Id: Ia242b6b0fed0b9d2fad6c66a14895e5574f6f5b9
Reviewed-on: http://git-master/r/61422
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R3fd2b06fefa1b153d2c739c5d7c55b2265659225

usb: gadget: fsl_udc_core: Fix race with vbus regulator

I observed udc_controller->vbus_regulator was set to an error value
during fsl_vbus_session - it was because fsl_udc_probe was still
running, and the regulator hadn't been set to NULL after printing out
the error condition.

Change-Id: I7f5dea54839ad1b63bc1c1854ff6f9ca0362f720
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/60471
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: R35a044979ffd3e053d55a5e09732beab9888be38

arm: tegra: initialise dam/ahub audio clocks

Bug: 862023

Change-Id: I62a66cdf12fb78132d78b2e6853d32c3f8a8d68a
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/58675
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: Rfa42d87cff0a75794fe69ffbecba6e501448509e

arm: tegra: rename tegra30 dam clocks to match dam driver's needs

Bug: 862023

Change-Id: Ib65ed2a54b4daf3ab91cbb826d8a1b661244d267
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/59864
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Rebase-Id: R9beac42bb660bfd8dcb122810594aae4aae2042f

asoc: tegra: switch on the compilation flag for dam driver

Bug: 862023

Change-Id: I953601b5f54b98aba868c4a2440f9e30a32e683d
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/59603
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Rebase-Id: R70ab13027c775aa383565e8bb42a6959bb0bb169

arm: tegra: register dam device in various boards

Bug: 862023

Change-Id: Ibdb12ce9ae50b30e4c25ea43adc4c8c7e6516858
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/59863
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Rebase-Id: R780104b6f8c11bc22c95245989ff517977244267

arm: tegra: add dam to devices.h

Bug: 862023
Change-Id: I135529efcb8bf4518802d950a07e6923690419b0
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/57881
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: R6c2419452e13142b07963e65a256e9da1e181ab2

asoc: tegra: add dam driver

Bug: 862023

Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Change-Id: I55206f3be702da9d969fca2c779e65363dd911fc
Reviewed-on: http://git-master/r/57879
Tested-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: R8cf6d6e004184b5a5a2c4bcf6578027c96d647f3

arm: tegra: Add support for vpr heap.

Bug 875847

Change-Id: Ieb237b3415f0861dfa13371fdbb7b3dbdac197b1
Reviewed-on: http://git-master/r/61246
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Rbed707e8bcba433aaed18fe9119c10902d4e618b

ARM: tegra: power: Add Tegra3 balanced throttling

Balanced CPU and core domains thermal throttling on Tegra3. When
throttling is enabled the new algorithm caps core bus frequencies
(EMC, cbus and sbus) along with CPU rate. The throttling steps, and
time spent on each step are pre-defined based on characterization
results.

(cherry picked from commit 0fa05e9904f369e201cad0c9be2b15e141d3624e)
(cherry picked from commit 977e6bf94297347d8979b19877cf228325377d8f)

Change-Id: I62bfcda7b5d6ba7b621e813f5d20ded7334a080f
Reviewed-on: http://git-master/r/61024
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R0e65df5536ed7153a4a11dd299c5cd383b51c190

ARM: tegra: dvfs: Add Tegra3 dvfs core cap interface

Added Tegra3 kernel dvfs throttling interface for VDD_CORE domains.
Requests from this interface are combined with sysfs capping requests
and the most aggressive (minimal) cap level is set.

(cherry picked from commit da2fa3965fb89ec7faeb49c7b9009bdd949f8fb7)
(cherry picked from commit 2b8b7d8d6feba48dde56c7fa3e92f57a9b26e75a)

Change-Id: Iadcb8cac04f0793fc2fdc8d8203d3bc973004a1d
Reviewed-on: http://git-master/r/61023
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Rc4cfbf50089133bd111c1a156d7a77586c6181c2

ARM: tegra: clock: Add shared floor EMC/cbus/sclk users

(cherry picked from commit 3c5a0b3d7bfbe30e1f312ae86d11eb8ee5bff7fa)
(cherry picked from commit 1017145476f4467536fd133dc679d5947a35d299)

Change-Id: I2968817f0148d10ca2f3fe14af018b2cc75d22da
Reviewed-on: http://git-master/r/61022
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Rb341188a0d72752b12e6137033c36cb892d9eb63

ARM: tegra: power: Lock force_policy_max update

(cherry picked from commit dc2f416df4664f5ddeba6f14f41cd6bcd717abab)
(cherry picked from commit caa79c7d6219231d02260ae91876eff4f411dee8)

Change-Id: I29eb42c73a7e3cd3f401e8b5d44bcf3f06478c2c
Reviewed-on: http://git-master/r/61021
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Ref5015bb8336d8106c80fa390911ff0371b3ec57

ARM: tegra: power: Enforce cpufreq policy maximum

Tegra cpu complex frequency is set by cpufreq driver to the maximum
of per-cpu target frequencies specified by the respective governors
running on each cpu core. It guarantees that final frequency is above
all per-cpu policy low limits, but policy high limit set on one core,
may be exceeded if the other core has higher target.

This commit implements complementary mode in cpufreq driver that set
final cpu frequency below all per-cpu maximum policy limits. The new
mode is disabled by default, and can be activated via

/sys/module/cpu_tegra/parameters/force_policy_max

(cherry picked from commit d52a93527778b13efd2e4b783ce0707513f53f26)
(cherry picked from commit bc1450eedb97fd2f37544e07dae15946d209866c)

Change-Id: I2b51738a50312e0b3ba747747e6fa68efddc6038
Reviewed-on: http://git-master/r/61020
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R2fa76e42f800220db708c8720a3fe6b1792e5c59

ARM: tegra: dvfs: Update Tegra3 speedo thresholds

Bug 817679

(cherry picked from commit 58c1334c299ebfbf6c220d97394199ee32209bea)
(cherry picked from commit 1a3cdc623eee4277402569da0ed42d5074126df7)

Change-Id: I1a8662ae2adc7c3b71e62a10cc241af9200be7d8
Reviewed-on: http://git-master/r/61019
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R156ba2bfe73d8e0d5961b2ff5b26c44a5caa52b1

media: video: tegra: ar0832: tune 800x600 sensor registers

Modify the READ_MODE and SCALING_MODE sensor register
for 800x600 sensor mode, making it same as other working
modes. This fixes the incorrect colors during camera
preview.

bug 873857
Original Gerrit: http://git-master/r/#change,59921
(cherry picked from commit 46ea121f9124cb18781f8c6653f57a77ffe9ef21)
Change-Id: I14efcf5cf435eb859b3b8837eb2cc33ba8f64a04
Reviewed-on: http://git-master/r/60776
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rcf483b037f211aa344589bd10477a7b76b84f764

media: video: tegra: ar0832: Sunny P8M01E support

Add support of Sunny P8M01E module (AKA aptina 8141)

This new module is identical with 8140 plus pixel improvement.
Use different recommended register settings for each sensor.
Add function to figure out the sensor id and let the odm driver
pick up the right config data.

Bug 868929
Original Gerrit: http://git-master/r/#change,53022
(cherry picked from commit f59f83468f71980c9ce3204df3a34f2aafffc512)

Change-Id: Ibed03f01b13a22a75753f8495ab17eb6077a99d3
Reviewed-on: http://git-master/r/60765
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R10688d303b3b7c401a58c8fb069654dade019d47

arm: tegra: usb: Adding phy_restore functions for null ULPI

Adding phy_restore_start and phy_restore_end functions for null ULPI.
Forcing ehci_restart after LP0 for null ULPI.

Bug 863224

Reviewed-on: http://git-master/r/58474
(cherry picked from commit 5f5e7961c8a6a5be853fcdba4ae10d0bd6efc5f3)

Change-Id: I635f456548674113a4e0e94ee22bd162d5bab04f
Reviewed-on: http://git-master/r/60703
Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Tested-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>
Tested-by: Steve Lin <stlin@nvidia.com>
Rebase-Id: R14132d927d965c6716c200c8f7ced640587cf01f

mmc: host: support runtime enable/disable SDCLK

Implement functions needed in struct mmc_host_ops to support
enable/disable SDCLK dynamically.

BUG 886285

Change-Id: Ic48ac63af495cea30ce926c39ec2e0a9f2d26244
Reviewed-on: http://git-master/r/57856
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rfae7d6001a827395824716fb858ef18d0d2c4d68

PM: remove redundant calculation

As max_num usage is not necessary, removing it.

Change-Id: I7b668bbbf0d5a388c8ade017194958976c861ea3
Reviewed-on: http://git-master/r/60855
Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Rebase-Id: R131970045a24c494f94de0a51eea6c73bdf994ea

ARM: tegra: power: Fix LP2/LP3 states accounting on Tegra3

- Made sure LP3 state is reported as last entered state to cpuidle
governor in case when LP3 is entered as a fall back from LP2 path.

- Accumulate idle time designated to LP2 state by cpuidle governor
and time actually spent in LP2 by each CPU separately. Update LP2
statistic output.

Change-Id: I55b461e94925ba7a41112756ed958f81fc0bc882
Reviewed-on: http://git-master/r/60381
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R240873bd1de225696d392ac5ba2c3d517c59d86e

input: touch: atmel_mxt_ts: Prevent touchscreen from becoming unresponsive in some situations

BUG 868649

Reviewed-on: http://git-master/r/50598
(cherry picked from commit ad1dbe0eda931f813b20d75400daaa9edf18c82a)

Change-Id: I29f353687c499ff830e98fcf038d8a786dc5608b
Reviewed-on: http://git-master/r/54841
Reviewed-by: Joel Kenny <jkenny@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Tested-by: Joel Kenny <jkenny@nvidia.com>
Rebase-Id: Rdde94e071f4a27250eccad562c819ca2f537ffcd

video: tegra: dc: fix range check in fbdev cmap

Bug 868060

Change-Id: Id9f0cca6670a3090941f18b0f4b663e07d9fc7e0
Reviewed-on: http://git-master/r/60813
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rd993acb0a3101f2d165108d215ef5f01ff6b1134

video: tegra: dc: support global fbdev gamma table

Add support to set a global gamma correction table via fbdev cmap
API. The 3 Tegra DC windows have their own local gamma tables, which
can either override or alter the global table.

Bug 868060

Change-Id: I0be1c5e4afa8fd8c010b772c7808c883c0848ab4
Reviewed-on: http://git-master/r/60201
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R7e613b1c8ac469242172bd81db9dfba25176e0c3

arm: tegra: cardhu: Reset Modem during init

Set GPIO direction to high on main k39 branch.

bug 817238

Change-Id: I2960b4a325d8013295528790a28daea4a58e10cd
Reviewed-on: http://git-master/r/58020
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R3a80bfd11cd3959fd2c760eda277f6db42ecb333

ARM: tegra: power: set enterprise default suspend mode to LP0

Bug 862504

Change-Id: I022206a4ca2aae50c2534268d3e974ecfaf87556
Reviewed-on: http://git-master/r/52945
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R41f3959e4f3386a3b5ef877105a7c854cd46bcca

ARM: tegra: power: set ventana default suspend mode to LP0

Bug 862504

Change-Id: Iabae1c9528d5ffa2904a509f9e4010fc547be959
Reviewed-on: http://git-master/r/52943
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R924a9542bcff40393bada5db36806abfda0e7165

ARM tegra: gpio: Correct gpio interrupt init sequence

It is possible for GPIO interrupt to occur when registering handler
since set_irq_chained_handler enables GPIO interrupt. Thus
all relevant variables are required to be initialized
before calling set_irq_chained_handler.

Also add initialization of interrupt status register.

Bug 884569

Reviewed-on: http://git-master/r/58218
(cherry picked from commit e03fe4cc1bf06fa6c32c0520e2ba31f009f9301d)

Change-Id: Ic76f95215b61d6e091ae1cfa11522f8af9c3eecd
Reviewed-on: http://git-master/r/60475
Reviewed-by: Daehyoung Ko <dko@nvidia.com>
Tested-by: Daehyoung Ko <dko@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R5340918dccc1a8b1d95c5b629cc985f44d45fb67

spi: tegra: Move clock controls api out of spin lock

The clock control apis can be sleepable in tegra platform as
spi require frequency/voltage boosting.
Moving the clock controls api out of spin lock context.

bug 874841

Reviewed-on: http://git-master/r/56869
(cherry picked from commit b316a4e4fd82f1af9af920079119c56bf271c3be)
Change-Id: I8fc824de02cb3af54f6331efa0500c79e806bb03
Reviewed-on: http://git-master/r/57315
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R601bd69547ec2612f42d24da29a2f8a5d3fb1fb8

video: tegra: Allow gradual phase in of adjustments on DIDIM

Adds phase_in_video field that slowly phases in changes to the
pixel modification and backlight values.  This should only be enabled
during video as its results with content that has non-deterministic
time between frame updates is sub-optimal.

Bug 888294

Reviewed-on: http://git-master/r/58426
(cherry picked from commit 27478be1820740080ed4b2a583846a0bb3c572b6)

Change-Id: If6fe099da1d63d742a906ec103911ebc207de644
Reviewed-on: http://git-master/r/60361
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R426a366a34085957659da342b9717bb4d7280898

video: tegra: Add priorities for DIDIM aggressiveness

Allows DIDIM to keep track of multiple aggressiveness settings
based on different priority levels.  Four Priority levels are supported
and the maximum priority currently specified overrules the other settings.

Lowest priority is given to the default kernel value and user specified values.

Bug 888292

Reviewed-on: http://git-master/r/58425
(cherry picked from commit 11a602308f6e4d0851c918933c6839b825e00dde)

Change-Id: Ic1081e52693e1cdb93501640caf6f12d56f4c58d
Reviewed-on: http://git-master/r/60359
Tested-by: Matt Wagner <mwagner@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Rebase-Id: Rea5ddc8fe837d2b57c696e80e6ca07e93b4fac38

arm: tegra: cardhu: enable LP0

Enable LP0 for cardhu family boards.

BUG 893759

Change-Id: Ic5cceeb1034104eefb3243036fbc2c3dc0125b43
Reviewed-on: http://git-master/r/60335
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rd7c4a6633a428895ebdb1e98932c696e7587271e

usb: ehci: tegra: Recovering 2LS WAR for non-UTMIP

Recovering 2LS SOF edge WAR for link-ULPI, null-ULPI and HSIC.

Bug 845989

Reviewed-on: http://git-master/r/57721
(cherry picked from commit ffa6f9b861b424c3c7d2042d1dbc8683cbc924ff)

Change-Id: Ib4b583b8a03f87063103e10a117eee00f8f14cea
Reviewed-on: http://git-master/r/60320
Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>
Tested-by: Steve Lin <stlin@nvidia.com>
Rebase-Id: R9e887cc6c11f953a6e0fa37ee524ba3dda4a8cf4

arm: tegra: baseband: add USB modem power management support

This platform driver enables the generic USB modem power management support
for out-of_band remote wakeup, selective suspend and system suspend/resume.

Bug 854339

Reviewed-on: http://git-master/r/44911
(cherry picked from commit f737bc30ee9509a79e499c975b61c5f58bb19bb3)

Change-Id: Ibf38afb593fd8097e6152197c816e95e8f457659
Reviewed-on: http://git-master/r/60313
Reviewed-by: Sheshagiri Shenoy <sshenoy@nvidia.com>
Reviewed-by: Steve Lin <stlin@nvidia.com>
Tested-by: Steve Lin <stlin@nvidia.com>
Rebase-Id: R2bc754d319b388ce477ab7f987352d7f307d11c3

ARM: tegra[3]: config: turn on USB net ASIX option

Mobile Sanity is using a USB Ethernet device for Linux sanity
that uses the USB_NET_AX driver. This enables the driver.

bug 881005

Change-Id: Ib2c0256ab80b61accfeb42de5534a0707f220fec
Signed-off-by: Matt Pedro <mapedro@nvidia.com>
Reviewed-on: http://git-master/r/60261
Reviewed-by: Allen Martin <amartin@nvidia.com>
Tested-by: Gerrit_Virtual_Submit
Reviewed-by: Mursalin Akon <makon@nvidia.com>
Rebase-Id: R842e88200dd73b2cacd3294e884e316cec33f054

ARM: tegra: clock: Remove Tegra3 initial pll_m refcount

Removed Tegra3 pll_m refcount from common and board initialization.
As a result pll_m is turned off when all client clocks are disabled.
Added pll_m disable/enable control via PMC registers - this one
actually works on Tegra3; kept clock register control in place, just
in case.

Originally implemented in dee91eaf47a7e6b392e9663170dcfdcdde73446c.

Bug 888476

Change-Id: Ifa70d25ce8d93abc12c741d3a51b32110db3f7dd
Reviewed-on: http://git-master/r/60129
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rf4201b6244e1dc202793730afa900a6b15b658b9

video: tegra: support display board PM313

This change supports PM313 with 19X12 panel.
The change uses PM313 in "Single input to Dual output" mode

Bug ID : 822980
Reviewed-on: http://git-master/r/50215
(cherry picked from commit b83e795747fa860b5b7fb66b2067ebe4f15bcfd0)

Change-Id: Iabf707ded2976e9877481c215d0b1f1940781f14
Reviewed-on: http://git-master/r/60085
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Re8eadc35c75fa21b0a5f3cb3bee0e8cb77dc3238

nvhost: Throttle low-priority tasks

Add interface for setting priority of a channel. When the priority is
low, wait for channel to become empty before submitting it.

Bug 864407

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/57237
(cherry picked from commit 75228616ee2c3073e391c529aecb3f82be3fc5a4)

Change-Id: I2f346918ae15427b826a2ec0c28bee6bc72dc859
Reviewed-on: http://git-master/r/59595
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rfb9ae7e88bec3a0c1e8f51f49f3e6f473d853b21

asoc: tegra: max98088 machine: report jack status at bootup

Bug: 890385
Bug: 862023

Change-Id: I154ba0c016c058bd7c3ca04b496c3fce9639ea4f
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/59104
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: Re63b865dff15841a27d692a078c327fc84b7edfe

asoc:tegra max98088 machine: Fixed Mic in naming

Fixed a typo in the names of the mic input.

Change-Id: Ib40672c44e57887389949f93f09b852188c8772a

Signed-off-by: ScottPeterson <speterson@nvidia.com>
Change-Id: Ifda29a75ccf2a160849090ceacbfdddd7d26808f
Reviewed-on: http://git-master/r/60005
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
Rebase-Id: Ra29a910c4737a1667d2640ce8cb9592ade7f1573

PM: fix calculation mistake in roll-over cases

In case of jiffies roll over, delta is made zero.
Hence fixing it, after taking roll over into consideration.

Change-Id: I7dacaa12deafbd2bd20705948c0e18292b718aa4
Reviewed-on: http://git-master/r/60147
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R0fa2027be53f95c16e11e8ea46c833c86182a3a9

ARM: tegra: Fix board-specific initcalls

These initcalls weren't ensuring that they're actually running on the
board they care about, which breaks on a multi-board kernel.

Change-Id: Ifd8a3e523c2523b68ec4d7e30c2b87969b939931
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/60010
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R2a4547ecd3b25da494799af15e42df89700b9fde

media: video: tegra: optimize writing gain register in ar0832

It used to set the same gain to four different registers
of each color component. Setting gain to global gain
register is equivalent to setting four registers.
This will save time to set gain.

Bug 889717

Reviewed-on: http://git-master/r/59443
(cherry picked from commit 618ebc7c8eda03fac467660520c9ad17043e467c)

Change-Id: Id58542c69c5c55befe8e045df0488770377bc126
Reviewed-on: http://git-master/r/59964
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Re463dd7b1c73428aa3fc77fbd40645176a2e4220

mfd: max77663: Update the driver to new mfd core

The mfd core was updated that removed size_t data_size and
renamed void *platform_data to void *mfd_data in struct mfd_cell.
The new mfd API, mfd_get_data(), was added for mfd device.
It return from struct platform_device to right value of mfd_data
and platform_data.

Change-Id: I21528879f2186d568f867f1c7e026f8d8e172b5a
Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/59891
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R4ee12a3ba5afec4255002e226f479e1c96a0f66c

mfd: mx77663: Fix build failure for undefined reference

Fixing build failure what undefined reference to max77663_xxx APIs when
didn't built-in max77663 mfd core driver.

Signed-off-by: Jin Park <jinyoungp@nvidia.com>
Reviewed-on: http://git-master/r/58579
(cherry picked from commit 99baa03a6d3401228f58c13a7dad5228f59d8718)

Change-Id: I971e132ec9ca12a4ce4bc47897c3722d07b93cbd
Reviewed-on: http://git-master/r/59890
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R0d9ce223d77c4005fa3c4c75dd5ac3221417a578

video: tegra: host: Fix misspelling in GPU detection

Fix misspelled configuration variable in tegra_gpu_register_sets().

Bug 889239

Change-Id: Id7da08e0eca16f28b1b6a17608b4f367311b5620
Reviewed-on: http://git-master/r/59889
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rf1d450abb59df99dcfdef6ff743fb32c9b254741

video: tegra: host: Fix incompatible function prototype

Change-Id: I3e5a7d17d80e863bf3ca8249cd0f557124d67057
Reviewed-on: http://git-master/r/59765
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R90fa53d3cba76abf9e2ff2686467f805a5485c4d

video: tegra: host: Separate clk and power gating

Separate clock and power gating from each other. There are now two
timeout values related to power management:
 * clockgate_delay: how long to wait before clock gating
 * powergate_delay: when to save context and power gate

If the module does not support power gating, that state is not used.
System suspend also explicitly power gates all channels before
suspending host1x.

Bug 875675

Change-Id: Id27f0fca7914ca2a135b27f623cb67af8a94a0ef
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry picked from commit eda8a5ccc474bc60d76e241f292573a8b6f30ab6)
Reviewed-on: http://git-master/r/59077
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Ra935e74f68b3d56479be1105e9858f2248ef6cd6

Revert "asoc: tegra: Remove HDMI-SPDIF path support"

This reverts commit 8e151ed243226aa68b1cd5a261694f48d606060f.

Change-Id: Iaf3bfab33da1c979c6b6140713e5eac70b632d1f
Reviewed-on: http://git-master/r/60269
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R7cd2bd07ee7a4783342fff1ccf22b8323ac10194

video: tegra: dc: preserve gamma/csc over suspend

Preserve YUV-to-RGB and gamma correction tables over suspend-resume

Bug 868060

Change-Id: I5ea2224f7ab0dfbe24d741b89d727034be3ebf68
Reviewed-on: http://git-master/r/58016
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R84115584b766900004b5c6cdc3cc8d693fb0db5a

video: tegra: set fb line_length to physical pitch

bug 867222

Change-Id: I782620ac5f9cc633b52bc525fecbdf56cef23002
Reviewed-on: http://git-master/r/54351
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R4df4ce6e36fa490ffad3233c1a7b09330c2a6f74

ARM: tegra: add missing 'static'

Change-Id: I0365550357de813b679f4ca8fdbff3909d151575
Signed-off-by: Colin Patrick McCabe <cmccabe@nvidia.com>
Reviewed-on: http://git-master/r/59756
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R4ab172dc3d4f284e4c1bc7f5f0f903c4f110d1a6

arm: tegra: enterprise: remove DIDIM serial prints

Reviewed-on: http://git-master/r/57991
(cherry picked from commit 0a1d4120620fa75ba69ed76478baa08ef37356b1)

Change-Id: I6e5bea4e16dd1e93d2a6c12929feab38fedd60eb
Reviewed-on: http://git-master/r/59692
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc1105fe074ef5542dac7169c8c89c4ea685a012c

asoc: max98088: report jack after enabling jack detection

Bug: 890385
Bug: 862023

Change-Id: Icec0be967ead5733aa600707c3ba4af99375e4ae
Signed-off-by: Nikesh Oswal <noswal@nvidia.com>
Reviewed-on: http://git-master/r/59102
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rc16aeac4ea1ba15e214fda504ef17aaef2c83ed5

arm: tegra: Add tegra_dc support for Harmony

This adds support for the Tegra dc driver for Harmony's internal
panel.

Signed-off-by: Robert Morell <rmorell@nvidia.com>
Change-Id: I9498b64dc4c5b05a39e1b8a2e7f1d584415038c2
Reviewed-on: http://git-master/r/58254
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rd195557fffa7093d0edf6d3f41ae6305491eef2a

arm: tegra: Add Harmony nvmap, host1x devices

This is necessary to use the Tegra accelerated device drivers.

Signed-off-by: Robert Morell <rmorell@nvidia.com>
Change-Id: I6c6f10f35654793b4fb713f4ac854f72640a5fef
Reviewed-on: http://git-master/r/58253
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rab19f5b8a98914619ff3d43f5a7eeeed0114f86a

ARM: tegra: Kconfig: Remove "default=y" for Tegra GRHOST

By default Tegra graphics host driver is turned on. This
CL removes the default 'yes' for this driver. However,
the option is turned on in defconfig files, for an easier
out of box experience.

Bug 888777

Change-Id: I1ec969f9b0097dc9beccb00ed8cee0ebc7608c41
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/57959
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: R5a0866bec84d1b17e8574026f35aee35439fbe50

ARM: tegra[3]: config: Turn on GRHOST

By default Tegra graphics host driver is turned on. This
CL removes the default 'yes' for this driver. However,
the option is turned on in defconfig files, for an easier
out of box experience.

Bug 888777

Change-Id: I600f3a3fdca1bec12585d6c58ced0efb33e3f8ff
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/57958
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rdb996fd0e4ab230d9fb1da90992e68b91f245b16

ARM: tegra[3]: config: turn on misc USB options

USB suspend, net and devices

Bug 876711, 876553

Change-Id: I06a5cdb9f0f28df3c583848d68293f7fb90ff42a
Signed-off-by: Mursalin Akon <makon@nvidia.com>
Reviewed-on: http://git-master/r/56828
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Re3e73b419d345cb59e2503baef105dafcf875471

HACK: Revert "USB: extend ehci-fsl and fsl_udc_core driver for OTG operation"

This reverts commit 83722bc9430424de1614ff31696f73a40b3d81a9.

Our OTG support doesn't play nice with the upstreamed OTG support, so
for now, revert the upstream commit.

Conflicts:

drivers/usb/gadget/fsl_udc_core.c

Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R5a4b466ee983307ee277a591e664c854b0ddd970

asoc: tegra: Remove HDMI-SPDIF path support

HDMI-SPDIF path is not supported on Tegra30. Remove WAR added to
make HDMI-SPDIF path partially functional.
Also remove hda2codec_2x clock access from SPDIF driver since this
is only required for HDMI-SPDIF path.

Bug 872652

Change-Id: Ibc90fa50813bd36808217b4935e58507a3f98a99
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/59640
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Rebase-Id: R1860c760d66a8a2d2d8294e7ccd23d9c5c3d5837

Revert "video: tegra: Add HDA clock management"

This reverts commit ec6673c1d2021df64e3920cc9c6a06e52e9ffbcb.

Revert this commit since HDA clock names will be changed in order
to add support for HDA driver.

Bug 872652

Change-Id: Ia4899672899189f199fae63a454b178dc29af812
Signed-off-by: Sumit Bhattacharya <sumitb@nvidia.com>
Reviewed-on: http://git-master/r/59617
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: R81e80436981bd78f47b20f2a24efd5d9d2a01cca

arm: tegra: use non-blocking api to cancel work from mc error isr

An api (del_timer_sync), which can sleep, should not be used in
hardirq context. This gives warnings for potential deadlock. Use
non-sleeping api to cancel the work instead. In this case, if the
work is already running, it would unthrottle mc error prints.

BUG 889717

Change-Id: I4c0205766d82a45a04d1c0125bb8ed5927757456
Reviewed-on: http://git-master/r/59604
Tested-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Prajakta Gudadhe <pgudadhe@nvidia.com>
Rebase-Id: R713c536217d0169f395ffb199ec2a97b274b9914

kernel: Add ioctl constants for i2s loopback tests

Add required ioctl constants for i2s loopback tests.
Audio test framework is using these ioctls for setting
pcm format paramters for I2S loopback test.

Change-Id: Id192668c5e9937e3cb42f8712a982f214e999289
Reviewed-on: http://git-master/r/59524
Reviewed-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Tested-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>
Rebase-Id: R5cb6bfb63d281559d992818c2a2a95cb00fba78d