Steve Lin [Thu, 12 May 2011 23:26:40 +0000 (16:26 -0700)]
usb: tegra: fix tegra ehci setup sequence
Fix tegra ehci setup sequence according to EHCI spec.
- move ehci_reset after ehci_halt
- avoid redundant ehci_reset after ehci_run. ehci_reset has a side effect
to cause phy reset for certain phy interface.
Bug 800301
Michael Hsu [Thu, 5 May 2011 19:12:47 +0000 (12:12 -0700)]
usb: cdc-acm: Add supported modem to CDC-ACM driver.
Prevent CDC-ACM driver from creating tty devices for each USB
interface on supported modem. Only create one tty device, leaving
other USB interfaces available for other uses (such as RAW-IP).
Original-Change-Id: I5b39fd8ea2284828e9cb3b5ce4330728e20b1662
Reviewed-on: http://git-master/r/15736 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I71ecd7c4426e7e82500f12d57b85a6bcc417065c
Rakesh Bodla [Wed, 4 May 2011 08:24:35 +0000 (13:54 +0530)]
usb: otg: tegra: Fix clock disable to match ref count
usbd clock is enabled during the probe and not disabled after the
functionality. Due to this clock reference count is non-zero and hence
usbd clock is not disabled during suspend. Fixed this by disabling
clock appropriately.
sclk minimum rate is set to 40MHz which is less than required by usb.
set sclk rate to 80MHz when usb is connected and disable sclk when usb is
not connected so that sclk will get clocked at minimum rate.
Steve Lin [Thu, 21 Apr 2011 22:39:20 +0000 (15:39 -0700)]
ARM: tegra: usb: Add Tegra3 NULL ULPI change
Integrate Tegra3 specific NULL ULPI changes to usb_phy.c.
- set ULPI clock to tristate before ULPI phy reset
- set USB host mode and HOSTPC register to ULPI mode
- add ULPIS2S slave0 and slave1 reset after enabling internal phy clock
Bug 800301, 787808
Original-Change-Id: I586f6655007838a2d5e5cb6c7b2f2d2b03f089c9
Reviewed-on: http://git-master/r/28131 Tested-by: Szming Lin <stlin@nvidia.com> Reviewed-by: Udaykumar Rameshchan Raval <uraval@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ib5de614c5358fbd29b81dc0bf728f7ec28af7689
Scott Williams [Mon, 18 Apr 2011 19:46:48 +0000 (12:46 -0700)]
ARM: tegra: usb: Fix compiler warnings
Fix "initialization from incompatible pointer type" warnings due to
a mixure of void and non-void functions used as initializers for
arrays of type tegra_phy_fp[]. All functions of type tegra_phy_fp
now uniformly return a status.
Original-Change-Id: I2fa80d329817ab6dffd789a34fc5dc3baca7dbff
Reviewed-on: http://git-master/r/28088 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Szming Lin <stlin@nvidia.com> Reviewed-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I5515a933c850b4e51315a3791cab6e0b81bc8444
ARM: tegra: Regulator power name independent of platform
Making the regulator power supply names independent of platform.
Now, power supply names should be given through board specific
files.
Bug 807534
Original-Change-Id: If83a23df91de9efd7d06733a7a306e57f3c89315
Reviewed-on: http://git-master/r/25058 Reviewed-by: Rakesh Bodla <rbodla@nvidia.com> Tested-by: Rakesh Bodla <rbodla@nvidia.com> Reviewed-by: Hanumanth Venkateswa Moganty <vmoganty@nvidia.com> Reviewed-by: Allen R Martin <amartin@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: If7c7600e49b9d1f4c1bcd5d1e6eba098df39cb0b
When host_pc is enabled ehci_bus_suspend is disabling the
usb phy by setting the PHCD bit in the HOST_PC register.
Due to this system is hanging during the bus_suspend procedure.
This PHCD bit should be set after completing the USB suspend
procedure. This PHCD bit is set as part of the phy suspend.
Fixing this by removing the code for disabling PHCD bit in
the suspend path.
Bitan Biswas [Fri, 4 Mar 2011 16:03:13 +0000 (21:33 +0530)]
tegra:otg: Fix clock disable to match ref count
usbd clock is enabled during the probe and not disabled after the
functionality. Due to this clock reference count is non-zero and hence
usbd clock is not disabled during suspend. Fixed this by disabling
clock appropriately.
- Since clocks are now turned off during suspend clock
needs to be enabled during fsl_udc_resume.
Robert Morell [Wed, 2 Feb 2011 03:06:29 +0000 (19:06 -0800)]
arm: tegra: usb_phy: Fix T20, error path
Commit 42274abc973de8565531fe56fae475c162cbfc84 moved the code to set up
the vdd_vbus_typea_usb regulator from T30-specific code to shared code.
This caused T20 to fail to boot, because it also didn't handle the error
case properly (it would notice the error and jump to the error handling
code, but never set the error code so the function would return 0).
Original-Change-Id: I926c0d0c716d409fee0188bc1f766631767a5e3d Signed-off-by: Robert Morell <rmorell@nvidia.com>
Reviewed-on: http://git-master/r/17978 Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ie039a639241021afef4774b46c6d87f852715eb7
Original-Change-Id: I0cf71fa97fd61e5e6358445fa338642db9793aae
Reviewed-on: http://git-master/r/17582 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ie9c06f83a25661bcf956cb3d26afa2237fb97bc0
Scott Williams [Tue, 25 Jan 2011 21:30:15 +0000 (13:30 -0800)]
arm: tegra: Fix compiler warnings
Original-Change-Id: I0914792c5fa170473d81eaad3c78582d23909f69
Reviewed-on: http://git-master/r/16950 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I370dfc82d528a06e820e0e321f48c8c0b67ecac5
Scott Williams [Mon, 10 Jan 2011 01:47:56 +0000 (17:47 -0800)]
arm: tegra: ehci: Fix warnings if CONFIG_PM is not defined
Original-Change-Id: Iaa8cbdf0ac37b295461c9e4accb5c3a15caa0f7f
Reviewed-on: http://git-master/r/15364 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I83c384ccdcc65bcb56f71804faa896997816d44c
Original-Change-Id: If13d61cce097ee90892132e775c5ac805a1f91e0
Reviewed-on: http://git-master/r/14922 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id331a2ef77522766e5b7f86131c6c981b37ba4c8
Suresh Mangipudi [Thu, 30 Dec 2010 10:38:27 +0000 (16:08 +0530)]
[usb/tegra] enabling support for usb device
enabling the usb device and adb is working.
Bug 770363
Original-Change-Id: Ic76dd8ba3ff10d7df00276696f6ed3d3ff5ed7da
Reviewed-on: http://git-master/r/14710 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ibf94d628921c1d923f0d2c223dfc3e5efe80fe28
Prashant Gaikwad [Tue, 29 Mar 2011 13:40:04 +0000 (19:10 +0530)]
tegra: otg: detect usb hotplug
Detect vbus and enable clock for usb otg using the interrupt received in
usb phy. usb phy interrupt is configured to max8907c usb detect interrupt to
get event for usb insertion when otg is suspended.
ARM: tegra: usb_phy: Setting USB_TXFILLTUNING for underrun issue
Setting the USB_TXFILLTUNING to 0x10, where as power on value
is 0x2. With this updated setting USB2 controller under run
are avoided. Setting this value after power_on and post_resume.
Bug 791857
Wen Yi [Mon, 21 Mar 2011 18:04:33 +0000 (11:04 -0700)]
usb: otg: tegra: disable usbd clock at end of probe
In the function tegra_otg_probe(), usbd clock is kept on
after probe function completes. Fix this by disabling the clock
before exiting the probe function.
Bug 803498
Original-Change-Id: I1aa7621f9dfcba1a249cc6d08a23b4106db3c1f2
Original-Change-Id: I3da69f72a312243b3c869543de3f841588bcce89
Reviewed-on: http://git-master/r/23207 Reviewed-by: Wen Yi <wyi@nvidia.com> Tested-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rabdd2fbd11cb3256b378f93a4d5c62cf565535bf
Venkat Moganty [Fri, 22 Jan 2010 04:56:45 +0000 (10:26 +0530)]
USB: fsl_udc_core: Fix USB chapter9 compliance tests.
In udc driver ch9getstatus() function is not mapping the status buffer's
virtual address to hardware for transfering the status data over dma.
On USB bus get status information is not going properly to the host.
Hence, few chapter9 tests are failing. Fixed this by maping the status
buffer address to the dmable address. With this fix USB chapter9
(usb command verifier) tests are passing.
Colin Cross [Fri, 29 Apr 2011 22:38:33 +0000 (15:38 -0700)]
fs: ext4: Fix computation of inodes per block group
857ac889cce8a486d47874db4d2f9620e7e9e5de (ext4: add interface
to advertise ext4 features in sysfs) added an error check that
exposes a bug in the computation of sbi->s_itb_per_group. If
the number of inodes per group is not a multiple of the number
of inodes per block,
Original-Change-Id: I8c60817dbb6feb43535b567ec7ea5ee0af709c37 Signed-off-by: Colin Cross <ccross@android.com>
(cherry picked from commit 8703a0ccb0135ae0de0d7011f29eeb6dc1caa486)
Todd Poynor [Tue, 15 Feb 2011 19:48:42 +0000 (11:48 -0800)]
ARM: Cortex-A9: Enable dynamic clock gating
Enable dynamic high level clock gating for Cortex-A9 CPUs, as
described in 2.3.3 "Dynamic high level clock gating" of the
Cortex-A9 TRM. This may cut the clock of the integer core,
system control block, and Data Engine in certain conditions.
Add ARM errata 720791 to avoid corrupting the Jazelle
instruction stream on earlier Cortex-A9 revisions.
Lajos Molnar [Fri, 9 Sep 2011 21:44:13 +0000 (16:44 -0500)]
video: fbmon: Add support for CEA pixel ratios.
CEA defines multiple timings with dual timing ratios that cannot
be distinguished from timings parameters. Added 2 new fb flags
to specify 4:3 or 16:9 display ratios.
Also added a flag that denotes CEA formats that require repeating
pixels.
Change-Id: I75d413babdcb4048a0ccce6548ed386ad0e52318 Signed-off-by: Lajos Molnar <molnar@ti.com>
JP Abgrall [Sat, 27 Aug 2011 01:39:17 +0000 (18:39 -0700)]
watchdog: tegra_wdt: give time for spinlock lockup detection to work
To allow the spinlock lockup detection to actually trigger after
60 seconds, the tegra_wdt heartbeat needs to be longer than that.
Bumping it to 120sec, as at the 50% marker the watchdog takes an
interrupt.
Colin Cross [Wed, 24 Aug 2011 02:26:33 +0000 (19:26 -0700)]
ARM: tegra: pm: hold cpus unti all have booted when exiting lp2
When exiting lp2, each cpu boots through cpu_resume, which
modifies the last used page table to add a 1-1 mapping in
order to turn on the mmu. The first cpu to boot triggers
booting the second cpu, and if allowed to continue immediately
may start executing a userspace task that is using the same
page tables as the second cpu is modifying during its boot
process. Hold each cpu in a loop until all cpus have
finished booting to ensure page tables are back to their
original state. Each cpu triggers a global tlb flush
after it restores the page table, so all cpus will see the
original values before they exit idle.
Change-Id: Iad91ae57e2abbbec3d6d491460c3e19411b519c0 Signed-off-by: Colin Cross <ccross@android.com>
Colin Cross [Wed, 24 Aug 2011 00:43:54 +0000 (17:43 -0700)]
ARM: tegra: sleep: flush tlbs when exiting wfi
tegra_sleep_wfi disables coherency to prepare for possibly
resetting the cpu. If an interrupt is received, it exits
wfi and re-enables coherency, but it was not flushing the
tlbs or the branch predictor array, which could have been
updated by broadcast tlb operations that were ignored.
Flush the tlbs and branch predictor array when exiting.
Change-Id: If2c6ca3f923baf2f883f461a2a90f08833c7e191 Signed-off-by: Colin Cross <ccross@android.com>
The prefetcher fetches a total of 128 bytes, and then responding to
sequential reads with this prefetched data. To avoid coherency issues,
it discards the prefetched data if a non sequential read occurs.
Allocate dtd with 128 bytes boundary to make 2 consecutive dtd 128 bytes
apart.
Submitted on behalf of Jay Cheng <jacheng@nvidia.com>
Change-Id: I2adc02c2ac7901d0617b487cb498a34ec7a63e18 Signed-off-by: James Wylder <james.wylder@motorola.com>
Nathan Connell [Mon, 2 May 2011 19:32:36 +0000 (14:32 -0500)]
usb: ehci: tegra: Correctly handle GetPortStatus during Resume
Multiple GetPortStatus requests can be made while the
USB bus is resuming. All requests must be handled
properly to prevent incorrect disconnect detection
during Resume and improper indentification of
Resume signaling as a remote wakeup event.
James Wylder [Fri, 11 Mar 2011 22:39:43 +0000 (16:39 -0600)]
usb: host: tegra: update memory frequency requests to 150 MHz
With the previous change in memory frequency (200 MHz
to 150 MHz) requests of 200 MHz will round up to full
speed. This negatively impacts current drain.
Change-Id: Ib67d8eaff57836a2f1756d84cce6533539911178 Signed-off-by: James Wylder <james.wylder@motorola.com>
James Wylder [Fri, 11 Mar 2011 22:39:43 +0000 (16:39 -0600)]
usb: gadget: tegra: update memory frequency requests to 150 MHz
With the previous change in memory frequency (200 MHz
to 150 MHz) requests of 200 MHz will round up to full
speed. This negatively impacts current drain.
Change-Id: Iefdb3a50aff338b44daa8311218400e4b4586152 Signed-off-by: James Wylder <james.wylder@motorola.com>