6 years agoregmap: name irq_chip based on regmap_irq_chip's name
Stephen Warren [Wed, 1 Aug 2012 17:40:48 +0000]
regmap: name irq_chip based on regmap_irq_chip's name

This is intended to give each irq_chip a useful name, rather than hard-
coding them all as "regmap".

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit ca142750f8ac3d01e45909e624ca783779894640)

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: I1dfe76e23fe60b46b33bfc2ef048b8498ffc8ac6
Reviewed-on: http://git-master/r/161551
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Stephen Warren <swarren@nvidia.com>

6 years agoregmap: store irq_chip inside regmap_irq_chip_data
Stephen Warren [Wed, 1 Aug 2012 17:40:47 +0000]
regmap: store irq_chip inside regmap_irq_chip_data

This will allow later patches to adjust portions of the irq_chip
individually for each regmap_irq_chip that is created.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 7ac140ec426ed304237205be77f99eedfc1186b5)

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Change-Id: Ib73deca2d8ca01d1ec49bdc94ebe20053c97981c
Reviewed-on: http://git-master/r/161550
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Stephen Warren <swarren@nvidia.com>

6 years agoregmap: irq: Only update mask bits when doing initial mask
Mark Brown [Wed, 1 Aug 2012 19:29:14 +0000]
regmap: irq: Only update mask bits when doing initial mask

Don't write the full register, it's possible there's bits other than the
masks in the same register which we shouldn't be changing.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
(cherry picked from commit 0eb46ad0c8d60943c1f46cef795fc537fbffd177)

Change-Id: I4e9f42422e961f9f842ab793227af7be25ca82cf
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/161549
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoregmap: fix some error messages to take account of irq_reg_stride
Stephen Warren [Fri, 27 Jul 2012 19:01:54 +0000]
regmap: fix some error messages to take account of irq_reg_stride

A number of places in the code were printing error messages that included
the address of a register, but were not calculating the register address
in the same way as the access to the register. Use a temporary to solve
this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
(cherry picked from commit 16032624f511b2fac0671cba5e7da40aa7e73a66)

Change-Id: I60e982d5f9f2bc5aba7a8a72e45893e23c4bb0d4
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/161548
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Stephen Warren <swarren@nvidia.com>

6 years agoasoc: tegra: Rt5640: modify DAPM route table
Vijay Mali [Mon, 5 Nov 2012 14:45:04 +0000]
asoc: tegra: Rt5640: modify DAPM route table

a) register DAPM route table with snd_soc_card structure and
remove the open-coded DAPM add route calls.

b) set card.fully_routed flag to request the ASoC core calculated
unused codec pins, and call snd_soc_dapm_nc_pin() for them.

Bug 1054060

Change-Id: I512b6329bf1328eff172f40d4cc6b59c763f1323
Signed-off-by: Vijay Mali <vmali@nvidia.com>
Reviewed-on: http://git-master/r/161249
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sumit Bhattacharya <sumitb@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>

6 years agoarm: tegra: sdhci: Set emmc voltage to 1.8V
rrajk [Mon, 5 Nov 2012 14:31:21 +0000]
arm: tegra: sdhci: Set emmc voltage to 1.8V

Set emmc supply interface voltage to 1.8V
Bug 1167307
Bug 1167312

Change-Id: I066fba8fe68b74d540a5803cc463ceef75cdfebb
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/161248
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agommc: tegra: Set proper emmc voltage
rrajk [Mon, 5 Nov 2012 14:23:47 +0000]
mmc: tegra: Set proper emmc voltage

Check interface supply voltage limit of emmc
and set it to 1.8V or 3.3V at resume
Bug 1167312
Bug 1167307

Change-Id: I2dda670ed9c270761f61eacb93233a7487894d84
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/161246
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agospi: tegra11: Set MODE bits before setting CS bit
Kunal Agrawal [Mon, 5 Nov 2012 09:25:15 +0000]
spi: tegra11: Set MODE bits before setting CS bit

Implemented change to set the MODE bits first and then
set CS and other bits of the command register.

Bug 1168218

Change-Id: I87bd94b8fac5821f11e575e53ee5694d6cad6d2c
Signed-off-by: Kunal Agrawal <kunala@nvidia.com>
Reviewed-on: http://git-master/r/161184
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: configs: Enable ROTH platform support
Pavan Kunapuli [Mon, 5 Nov 2012 08:47:53 +0000]
ARM: tegra: configs: Enable ROTH platform support

Change-Id: I2c56843f1fad3d962be811a4a83e0aae10dedaa5
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-on: http://git-master/r/161159
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: dvfs: Update miscellaneous dvfs tables
Alex Frid [Thu, 25 Oct 2012 07:07:38 +0000]
ARM: tegra11: dvfs: Update miscellaneous dvfs tables

- Updated dvfs tables for SBUS (system clock), Host1x, and VI clocks
- Updated maximum limits for Host1x and MSELECT clocks
- Allowed only integer divisors for Host1x, VI, and MSELECT clocks

Change-Id: I4128cde767609a6bf4ccc3dd85a0f060feaa2dcb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147681
(cherry picked from commit 03a2546f2745dab8a8adda72777a062b7c113865)
Reviewed-on: http://git-master/r/161070
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: clock: Do not allow 1:1.5 clock dividers ratio
Alex Frid [Thu, 25 Oct 2012 06:45:24 +0000]
ARM: tegra11: clock: Do not allow 1:1.5 clock dividers ratio

Change-Id: Iac26d1144b45247c3b5c70a47e26a1fba228b4d0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147680
(cherry picked from commit 723f73ae73cacb4274b2b671a8454f5741dae712)
Reviewed-on: http://git-master/r/161069
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: dvfs: Update LP CPU dvfs table
Alex Frid [Thu, 25 Oct 2012 05:59:18 +0000]
ARM: tegra11: dvfs: Update LP CPU dvfs table

Change-Id: I47c5f2eae9ad0cbb1685c232308cc30bf7b2e6bf
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147679
(cherry picked from commit ed29f1c25fe727023f8624536a78fbe45ab91689)
Reviewed-on: http://git-master/r/161068
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: dvfs: Updated dvfs tables of c-bus modules
Alex Frid [Wed, 24 Oct 2012 22:06:36 +0000]
ARM: tegra11: dvfs: Updated dvfs tables of c-bus modules

Updated dvfs tables of c-bus modules per characterization.
Moved EPP from c3bus and c2bus, since it is closely matching 2d/3d
rates. As a result bus assignments:

c2bus = 2D, 3D, and EPP modules
c3bus = MSENC, SE, TESEC, and VDE modules

Change-Id: I78f6336a459f7959a18071c91c299e0247dbeb6f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147326
(cherry picked from commit 034654b06d2b9d089202a193a872d47f2367d930)
Reviewed-on: http://git-master/r/161067
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: dvfs: Reduce core voltage range
Alex Frid [Wed, 24 Oct 2012 21:15:25 +0000]
ARM: tegra11: dvfs: Reduce core voltage range

For initial testing of core voltage scaling s/w reduced core voltage
range from [0.9V ... 1.125V] to [1.0V ... 1.120V].

Bug 116126

Change-Id: Ieb21a45d3ecb3a228c2a122cb78aeb2daaaef3d2
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/147325
(cherry picked from commit 1282fa23b54c2cfdedfeaa439a1cb5945d04b5ad)
Reviewed-on: http://git-master/r/161066
Reviewed-by: Matthew Longnecker <mlongnecker@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoarm: tegra: fuse: fix the minor number for T11x A01 version.
Krishna Reddy [Sat, 3 Nov 2012 00:53:19 +0000]
arm: tegra: fuse: fix the minor number for T11x A01 version.

The minor number is set to 0 instead of 1 for A01.

Change-Id: I5ffa98f740d4cb6d88ac96d787fe6b463feaf7f0
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/161039
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra: enterprise: Change Power Rail for nct1008
Xiaohui Tao [Fri, 2 Nov 2012 23:23:40 +0000]
ARM: tegra: enterprise: Change Power Rail for nct1008

The power rail for nct1008 is different for Enterprise A02 and
A03. The A02 uses ldousb_common and A03 uses ldo5. Modify entries
to provide the right one.

bug 1163476

Change-Id: I97592c4b0cb0a484e0846a265c79ad369d411a79
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/161014
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Tested-by: Shridhar Rasal <srasal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoRevert "asoc: tegra: cs42l73: VSPIN dapm route with DMIC event"
Rahul Mittal [Fri, 2 Nov 2012 09:10:36 +0000]
Revert "asoc: tegra: cs42l73: VSPIN dapm route with DMIC event"

This reverts commit 8bd50e3f390810fffdb63d3b0a32972e09db3000
Fix for pluto DMIC audio recording ANR
Bug 1167696

Change-Id: I58edab224d6527912869e8bafa7248c82c332556
Signed-off-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-on: http://git-master/r/160833
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: dalmore: fix multiple GPIO mapping
aghuge [Fri, 2 Nov 2012 09:07:46 +0000]
ARM: tegra: dalmore: fix multiple GPIO mapping

GPIO_PK4 is sued for TS_RESET and not for
EXT_MIC

Bug 1052495

Change-Id: Id078dc732be969b01a9348a01bdef30bd1ee0a3e
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/160830
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Robert Collins <rcollins@nvidia.com>
Reviewed-by: David Jung <djung@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoarm: tegra: Added platform data for max77665 haptics driver
Sumit Sharma [Wed, 31 Oct 2012 09:21:02 +0000]
arm: tegra: Added platform data for max77665 haptics driver

Added platform data for MAXIM77665 haptics driver in board file

Bug 1157818
Bug 1043388
Bug 1157811

Change-Id: I387f6d589c0e23b2cbdc1b74cc21e3d615f9c985
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/160766
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: config: Added max77665 haptics driver support
Sumit Sharma [Wed, 31 Oct 2012 09:06:41 +0000]
arm: tegra: config: Added max77665 haptics driver support

Enabled MAXIM 77665 haptics driver support config variable in defconfig

Bug 1157818
Bug 1043388
Bug 1157811

Change-Id: Id05c3fd545c1f6bae05d2a7b48b7f61b48995d4b
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/160765
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agobacklight: max8831: check power before updating bl
Kerwin Wan [Thu, 25 Oct 2012 10:38:57 +0000]
backlight: max8831: check power before updating bl

bug 1057856

Change-Id: I592f61432d4f628618fdf7420e29ff3f5e26046a
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/160406
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agopluto: add interface to check the power of bl
Kerwin Wan [Thu, 25 Oct 2012 10:37:30 +0000]
pluto: add interface to check the power of bl

bug 1057856

Change-Id: Ie30dc8a724f1c961be1aa9f1972d491b47c1bf64
Signed-off-by: Kerwin Wan <kerwinw@nvidia.com>
Reviewed-on: http://git-master/r/160405
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: Dalmore/pluto: Set drive strengths
Naveen Kumar Arepalli [Tue, 30 Oct 2012 07:01:28 +0000]
ARM: tegra: Dalmore/pluto: Set drive strengths

Enabling HSM for SD Pad groups: SDIO1, SDIO3, GMA
as per characterization team recommendations

Bug 1052592

Change-Id: I6c5f3033effa9f40420ff5f2300ffc0da3ae4041
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/159769
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra: Add support to parse pwr_i2c in command line
Chaitanya Bandi [Tue, 30 Oct 2012 06:53:03 +0000]
ARM: tegra: Add support to parse pwr_i2c in command line

Bootloader passes pwr_i2c=1000 if 1Mhz is supported with
PWR_I2C. Parsing this is kernel.

Bug 1158569

Change-Id: I5c6c87e905dceb9d67ef1f23eaf0b70768481061
Signed-off-by: Chaitanya Bandi <bandik@nvidia.com>
Reviewed-on: http://git-master/r/159768
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agotegra: dc: hdmi: Add 720p CVT mode
Shashank Sharma [Fri, 26 Oct 2012 10:54:16 +0000]
tegra: dc: hdmi: Add 720p CVT mode

Add 720p mode in supported CVT video mode list.

Bug 1065850
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Change-Id: I19b90254aa3b4a82965ae43fc7e09b38dad46cd8
Reviewed-on: http://git-master/r/149130
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: Separating out pmc from usb phy.
Venu Byravarasu [Fri, 26 Oct 2012 11:20:15 +0000]
arm: tegra: Separating out pmc from usb phy.

Taking out PMC from Tegra11x USB phy driver.
This would facilitate in having common PMC interface between XUSB and USB.

Change-Id: I695ac2794ff8324d73e3ed8e679ad5da54593fd4
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Reviewed-on: http://git-master/r/147480
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11x: flush L2 at entry of system suspend
Bo Yan [Wed, 31 Oct 2012 01:55:26 +0000]
ARM: tegra11x: flush L2 at entry of system suspend

since we are no longer flushing L2 cache in cpu_suspend, this has
to be done when we need to enter system suspend.

Change-Id: If84d1b4e8120e48aaea7fc850254ff71474a4399
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/160077
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: Tegra11x: defconfig: Build SND_HDA_INTEL as a module
Rahool Paliwal [Mon, 8 Oct 2012 13:21:00 +0000]
ARM: Tegra11x: defconfig: Build SND_HDA_INTEL as a module

Build SND_HDA_INTEL as a module. SND_HDA_INTEL is required for
audio on HDMI. Building it with "y" makes it default ALSA device,
which then blocks all multimedia audio use cases.

Bug 1154979

Change-Id: Id84f3b7d8a0934a9862dad493706c103aa72cce3
Signed-off-by: Rahool Paliwal <rpaliwal@nvidia.com>
Reviewed-on: http://git-master/r/142434
Reviewed-by: Shashank Sharma <shashanks@nvidia.com>
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
(cherry picked from commit 10bedbfd274014808a9f76808734775e91a12c87)
Reviewed-on: http://git-master/r/160783
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoarm: tegra: fix pinmux setting for 4.7in JDI panel
Karthik Ramakrishnan [Fri, 2 Nov 2012 02:50:26 +0000]
arm: tegra: fix pinmux setting for 4.7in JDI panel

Modify pinmux table to reincorporate smart panel related changes.

Change-Id: Ic6d4bca25e937bfae6260aff244ca7b4a549f4ed
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Reviewed-on: http://git-master/r/160761
Tested-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoARM: tegra11: clock: Propagate shared bus maximum limit
Alex Frid [Tue, 30 Oct 2012 06:03:01 +0000]
ARM: tegra11: clock: Propagate shared bus maximum limit

Propagated recursively maximum rate limitation down the possible
chain of shared buses (don't exist yet). Made sure shared user
rates are not increased while propagating new maximum rate.

Change-Id: Ie77a4212c75e15fd81a4364f8647a11bdb82ceff
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/160461
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Kaz Fukuoka <kfukuoka@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>

6 years agoARM: tegra11: clock: Rename bus user comparison ops
Alex Frid [Sun, 28 Oct 2012 06:28:58 +0000]
ARM: tegra11: clock: Rename bus user comparison ops

Renamed bus user comparison operations from "cbus_user_is_xxx"
to "bus_user_is_xxx", as they can be applied to non cbus users
as well.

Change-Id: Iced5166f368a688675509dfd0d2e37291d13dd1b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/160460
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoCHROMIUM: config: Add t114 splitconfig
Christopher Freeman [Wed, 31 Oct 2012 20:50:54 +0000]
CHROMIUM: config: Add t114 splitconfig

Adds config file for T114/Dalmore for ChromeOS

Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Change-Id: Ie9497a4310b73640bccff66db61fc29c69703128
Reviewed-on: http://git-master/r/160312
Reviewed-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Andrew Chew <achew@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

6 years agoArm: tegra: ahb: Enable AHB prefetch for sdmmc4
naveenk [Tue, 16 Oct 2012 15:19:59 +0000]
Arm: tegra: ahb: Enable AHB prefetch for sdmmc4

Change-Id: I32cbd108998fda75de5ba740370d4aeb9a0c8423
Signed-off-by: naveen kumar arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/159771
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agovideo: tegra: dc: remove log spam on mode change
Jon Mayo [Fri, 26 Oct 2012 18:12:33 +0000]
video: tegra: dc: remove log spam on mode change

Bug 1159399

Change-Id: I0c359fc080e9b45dcd068b73c97d8c8ca0c487fa
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/159920
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: configs: disble CONFIG_MMC_EMBEDDED_SDIO
Nitin Bindal [Mon, 5 Nov 2012 09:15:18 +0000]
ARM: tegra: configs: disble CONFIG_MMC_EMBEDDED_SDIO

Disble CONFIG_MMC_EMBEDDED_SDIO flag, so that CCCR information
can be read from WiFi chipset.

Bug 1162770

Change-Id: I08f913f528a9eccc246b606309eceae3581f5ea0
Signed-off-by: Nitin Bindal <nbindal@nvidia.com>
Reviewed-on: http://git-master/r/161164
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoarm: tegra: usb_phy: Fix HSIC phy power off
Abhishek Shukla [Thu, 1 Nov 2012 18:00:34 +0000]
arm: tegra: usb_phy: Fix HSIC phy power off

- Remove assignment of unused port_speed
variable for HSIC
- Remove HSIC reset during suspend state as
it is causing resume failure sometimes.
- Adding wait for shutting down PHY clock after
setting PHCD bit to turn off the PHY clock.

Bug 1159000

Change-Id: I34bc24a27fe664cb6a77095e51d9e4517d81216c
Signed-off-by: Abhishek Shukla <abhisheks@nvidia.com>
Reviewed-on: http://git-master/r/160623
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoARM: tegra: power gate skip update
rrajk [Tue, 30 Oct 2012 07:08:06 +0000]
ARM: tegra: power gate skip update

T11x power gate partition skip list updated. CPU and 3D partitions
are removed from skip list and power gate for these partitions
is controlled by respective modules.

bug 1053317

Reviewed-on: http://git-master/r/134739
(cherry picked from commit cc2038d4f030a57c0b450ee7d51e56776449427f)

Change-Id: Ia72b1b6b7e8620b1bb52eb034a8c6817465a2d61
Signed-off-by: rrajk <rrajk@nvidia.com>
Reviewed-on: http://git-master/r/159770
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Shashank Garg <sgarg@nvidia.com>

6 years agoarm: tegra: mc: Add config option for tegra errata 1157520.
Krishna Reddy [Wed, 17 Oct 2012 02:16:51 +0000]
arm: tegra: mc: Add config option for tegra errata 1157520.

Add config option for tegra errata 1157520.
Eanble the errata for t11x A01.
Bug 1157520

Change-Id: I9bbd4b0ae2d92bede85897203e88c295b245f38b
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/161037
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoinput: touch: Suspend/Resume correction
Xiaohui Tao [Fri, 26 Oct 2012 22:30:26 +0000]
input: touch: Suspend/Resume correction

Instead of using regulator_get/put, we are using
devm_regulator_get/put

Change-Id: I6e740704648497927bdefbb63f0d39c3323081b6
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/159380
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoinput: touch: Suspend/Resume updates
David Jung [Thu, 25 Oct 2012 23:10:05 +0000]
input: touch: Suspend/Resume updates

Nvidia updates for suspend/resume
for Raydium touch screen software.

Bug 1054288
Bug 1165520

Change-Id: I6405af7a66fe60120ad6c46b3423ff708457935f
Signed-off-by: David Jung <djung@nvidia.com>
Reviewed-on: http://git-master/r/147737
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agommc: block: replace __blk_end_request() with blk_end_request()
Naveen Kumar Arepalli [Fri, 2 Nov 2012 07:10:09 +0000]
mmc: block: replace __blk_end_request() with blk_end_request()

For completing any block request, MMC block driver is calling:
spin_lock_irq(queue)
__blk_end_request()
spin_unlock_irq(queue)

But if we analyze the sources of latency in kernel using ftrace,
__blk_end_request() function at times may take up to 6.5ms with
spinlock held and irq disabled.

__blk_end_request() calls couple of functions and ftrace output
shows that blk_update_bidi_request() function is almost taking 6ms.
There are 2 function to end the current request: ___blk_end_request()
and blk_end_request(). Both these functions do same thing except
that blk_end_request() function doesn't take up the spinlock
while calling the blk_update_bidi_request().

This patch replaces all __blk_end_request() calls with
blk_end_request() and __blk_end_request_all() calls with
blk_end_request_all().

Testing done: 20 process concurrent read/write on sd card
and eMMC. Ran this test for almost a day on multicore system
and no errors observed.

This change is not meant for improving MMC throughput; it's basically
about becoming fair to other threads/interrupts in the system. By
holding spin lock and interrupts disabled for longer duration, we
won't allow other threads/interrupts to run at all. Actually slight
performance degradation at file system level can be expected as we
are not holding the spin lock during blk_update_bidi_request() which
means our mmcqd thread may get preempted for other high priority
thread or any interrupt in the system.

These are performance numbers (100MB file write) with eMMC running
in DDR mode:

Without this patch:
Name of the Test Value Unit
LMDD Read Test 53.79 MBPS
LMDD Write Test 18.86 MBPS
IOZONE Read Test 51.65 MBPS
IOZONE Write Test 24.36 MBPS

With this patch:
Name of the Test Value Unit
LMDD Read Test 52.94 MBPS
LMDD Write Test 16.70 MBPS
IOZONE Read Test 52.08 MBPS
IOZONE Write Test 23.29 MBPS

Read numbers are fine. Write numbers are bit down (especially LMDD
write), may be because write requests normally have large transfer
size and which means there are chances that while mmcq is executing
blk_update_bidi_request(), it may get interrupted by interrupts or
other high priority thread.

Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Reviewed-by: Namjae Jeon <linkinjeon@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
(cherry picked from commit ecf8b5d0a378a0f922ffca27bd0a9101f246fa11)

Bug 1167555

Change-Id: I18ebd0e1423ff2abb16da78c354923fe3998b846
Signed-off-by: Naveen Kumar Arepalli <naveenk@nvidia.com>
Reviewed-on: http://git-master/r/160794
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>

6 years agoarm: tegra: USB: Fix phy_power_on condition
Petlozu Pravareshwar [Fri, 2 Nov 2012 06:42:12 +0000]
arm: tegra: USB: Fix phy_power_on condition

When the Phy is left powered on; the USB phy should not be programmed.

Bug 1160474

Change-Id: Ifa38769cda74a4be74ac2674e774574c2da574bf
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/160786
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agotouch: raydium: Update to board files
David Jung [Mon, 29 Oct 2012 19:51:10 +0000]
touch: raydium: Update to board files

Nvidia updates to
add names for platform id, clocks to data
descriptors. Correct 1.8V and 3.3V names
for touch screen.

Bug 1054288
Bug 1165520

Change-Id: I0ea7c63775ae64b8ec8386f5fdbe7503787a1e8f
Signed-off-by: David Jung <djung@nvidia.com>
Reviewed-on: http://git-master/r/159599
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoinput: misc: Add maxim max77665 haptic driver support
Syed Rafiuddin [Thu, 9 Aug 2012 11:24:51 +0000]
input: misc: Add maxim max77665 haptic driver support

Maxim max77665 is a companion pmic which includes haptic motor.

This patch adds the haptic motor driver

Bug 1157818
Bug 1043388
Bug 1157811

Change-Id: I5e395ea33426469496945d64df5b31c28ddafdf2
Signed-off-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-on: http://git-master/r/159459
Tested-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agodrivers: media: tegra: max77665: torch control fix
Charlie Huang [Thu, 25 Oct 2012 21:06:10 +0000]
drivers: media: tegra: max77665: torch control fix

the torch timer and led enable registers were not updated properly.

bug 1116953

Change-Id: If94a5a62e2cb36b3c75c1a69f22cebffdd8cbe27
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/147707
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Anton Poon <antonp@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

6 years agoinput: touch: raydium: add enable/disable
Mallikarjun Kasoju [Tue, 16 Oct 2012 12:51:48 +0000]
input: touch: raydium: add enable/disable

For 'enabled' sysfs provide enable and disable and
invoke respective suspend and resume PM. This functionality will
replace early suspend functionality.

Bug 1063749

Change-Id: I100c6b4d8d4d71861fdacc6b1c0d2efafc8a6b4c
Signed-off-by: David Jung <djung@nvidia.com>
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/147699
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoarm: tegra: power: Pluto keep 3.3 and 1.8 on
David Jung [Wed, 10 Oct 2012 21:00:45 +0000]
arm: tegra: power: Pluto keep 3.3 and 1.8 on

Modify to keep 3.3V and 1.8V always on
for touch screen and other devices
on those rails. They will use low power
sleep modes instead.
SysEng recommends that both rails be kept
on bc leakage was seen when only one rail
was shut off.

Bug 1155297

Change-Id: I66e5c46ce41a7c3100b6b04c10fc6d19f786cda3
Signed-off-by: David Jung <djung@nvidia.com>
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/147647
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agotouch: raydium: change SPI bus to 18MHz board file
David Jung [Tue, 2 Oct 2012 20:18:55 +0000]
touch: raydium: change SPI bus to 18MHz board file

Update Dalmore to 18 MHz SPI bus.

Bug 1054642

Change-Id: I4a3d9baf6f324271f0b4444176e1152596749a5b
Signed-off-by: David Jung <djung@nvidia.com>
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/147646
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: suspend/resume will mng clk
David Jung [Fri, 5 Oct 2012 00:08:13 +0000]
arm: tegra: suspend/resume will mng clk

Change board files so that touch suspend/resume
will handle the turning on/off of the clock.

Bug 1054288

Change-Id: I972b86f08f244ed53382da6c87e18bd0899e0206
Reviewed-on: http://git-master/r/#change,141056
(cherry picked from commit d0f27d136d632a1233e024ed4288fe5068979d1a)
Signed-off-by: Johnny Qiu <joqiu@nvidia.com>
Signed-off-by: David Jung <djung@nvidia.com>
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/147644
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: raydium board file slow scan updates
David Jung [Wed, 24 Oct 2012 23:22:35 +0000]
arm: tegra: raydium board file slow scan updates

Nvidia changes to update board files for slow scan.

Bug 1054801

Change-Id: Ibc40c81d8b8e5b6ddcd3abb92e59ab5f74e2ca9f
Signed-off-by: David Jung <djung@nvidia.com>
Reviewed-on: http://git-master/r/147363
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agoarm: tegra: raydium board files for slow scanning
David Jung [Wed, 24 Oct 2012 22:46:55 +0000]
arm: tegra: raydium board files for slow scanning

Raydium code drop.
Update board files for slow scan mode.

Bug 1054801

Change-Id: I7dab4fab23b3ee4bd1f662f9fba5a687199c259f
Signed-off-by: David Jung <djung@nvidia.com>
Reviewed-on: http://git-master/r/147345
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agoinput: touch: raydium: updates for slow scanning
David Jung [Wed, 24 Oct 2012 22:39:38 +0000]
input: touch: raydium: updates for slow scanning

Raydium code drop.
Update for Raydium touch for
Pluto slow scanning

Bug 1054801

Change-Id: Id182035bf7e51ba3431c392ee10a95b5bc518157
Signed-off-by: David Jung <djung@nvidia.com>
Reviewed-on: http://git-master/r/147343
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agospi: tegra: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 07:33:28 +0000]
spi: tegra: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
clk_prepare_enable and clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: I8e34e8bb7688369cb0f76f7f6b5ad68d4429bd52
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146799
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agommc: host: tegra: moving to clk prepare APIs
Sivaram Nair [Tue, 23 Oct 2012 07:33:05 +0000]
mmc: host: tegra: moving to clk prepare APIs

The clk_enable/clk_disable pair of APIs are replaced with
clk_prepare_enable and clk_disable_unprepare.

This is needed for the migration to common clk framework.

Bug 920915

Change-Id: I728c2ee188ca9cf6fa7fe7e85fafee29254b6c1b
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/146798
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: Remove A15 sim timer hack
Jeff Smith [Thu, 18 Oct 2012 21:35:34 +0000]
ARM: tegra: Remove A15 sim timer hack

Change-Id: Ifc98bac7bd609419d8d0774f8f129cf666d486c6
Signed-off-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-on: http://git-master/r/146077
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: usb_phy: Tracking circuit power down
srinivas [Wed, 12 Sep 2012 08:38:38 +0000]
ARM: tegra: usb_phy: Tracking circuit power down

1. Bring PD_TX out of power-down mode by writing
UHSIC_PADS_CFG1 register to 0.
2. Bring tracking circuit out of power-down mode by
clearing bit PD_TRK.
3. Add 25usec delay. This allows calibration complete.
4. Power down tracking circuit by setting PD_TRK=1.

Bug 1037962

Change-Id: Iae682af2387237eb15025c0ad705be5fd7293019
Signed-off-by: srinivas thaduvai <sthaduvai@nvidia.com>
Reviewed-on: http://git-master/r/131727
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agothermal: fix potential out-of-bounds memory access
Guenter Roeck [Sat, 21 Jul 2012 00:53:48 +0000]
thermal: fix potential out-of-bounds memory access

temp_crit.name and temp_input.name have a length of 16 bytes.  Using
THERMAL_NAME_LENGTH (20) as length parameter for snprintf() may result in
out-of-bounds memory accesses.  Replace it with sizeof().

Addresses Coverity #115679

bug 1059470

Change-Id: I401dc97f4fcab8df87697ddf7ea1543c08e5827f
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Cc: Len Brown <lenb@kernel.org>
Cc: "Brown, Len" <len.brown@intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-on: http://git-master/r/160236
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Introduce locking for cdev.thermal_instances list.
Zhang Rui [Tue, 24 Jul 2012 08:56:21 +0000]
Thermal: Introduce locking for cdev.thermal_instances list.

we need to go over all the thermal_instance list of a cooling device
to decide which cooling state to put the cooling device to.

But at this time, as a cooling device may be referenced in multiple
thermal zones, we need to lock the list first in case
another thermal zone is updating this cooling device.

bug 1059470

Change-Id: I9dfbfc397886e837d47c61ba019e5ca938aeb9f0
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/160235
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Unify the code for both active and passive cooling
Zhang Rui [Wed, 27 Jun 2012 06:14:05 +0000]
Thermal: Unify the code for both active and passive cooling

Remove thermal_zone_device_passive(). And use
thermal_zone_trip_update() and thermal_zone_do_update()
for both active and passive cooling.

bug 1059470

Change-Id: I712aa94fc927a93003bdfde2f64a3e0c5ad0ef13
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/160234
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Introduce simple arbitrator for setting device cooling state
Zhang Rui [Wed, 27 Jun 2012 06:13:04 +0000]
Thermal: Introduce simple arbitrator for setting device cooling state

This fixes the problem that a cooling device may be referenced by
by multiple trip points in multiple thermal zones.

With this patch, we have two stages for updating a thermal zone,
1. check if a thermal_instance needs to be updated or not
2. update the cooling device, based on the target cooling state
   of all its instances.

Note that, currently, the cooling device is set to the deepest
cooling state required.

bug 1059470

Change-Id: I07b503a2c2ca61f4e5b4b2e6828209def480f5a8
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/160233
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: List thermal_instance in thermal_cooling_device.
Zhang Rui [Wed, 27 Jun 2012 06:11:52 +0000]
Thermal: List thermal_instance in thermal_cooling_device.

List thermal_instance in thermal_cooling_device so that
cooling device can know the cooling state requirement
of all the thermal instances.

bug 1059470

Change-Id: I98042513defa42657e93cfdfe263b166bca55139
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159973
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Rename thermal_instance.node to thermal_instance.tz_node.
Zhang Rui [Wed, 27 Jun 2012 02:09:36 +0000]
Thermal: Rename thermal_instance.node to thermal_instance.tz_node.

thermal_instance should be referenced by both thermal zone devices
and thermal cooling devices.

Rename thermal_instance.node to thermal_instance.tz_node in this patch
and thermal_instanace.cdev_node will be introduced in next patch.

bug 1059470

Change-Id: Icd1638df5ed1d7bc9d026943c943b5aaba31d005
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159972
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Rename thermal_zone_device.cooling_devices
Zhang Rui [Wed, 27 Jun 2012 02:09:00 +0000]
Thermal: Rename thermal_zone_device.cooling_devices

Rename thermal_zone_device.cooling_devices
to thermal_zone_device.thermal_instances

thermal_zone_device.cooling_devices is not accurate
as this is a list for thermal instances, rather than cooling devices.

bug 1059470

Change-Id: I84db38d9c9e329ba99afda5f1bcd94af3e5c627b
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159971
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: rename structure thermal_cooling_device_instance to thermal_instance
Zhang Rui [Wed, 27 Jun 2012 02:08:19 +0000]
Thermal: rename structure thermal_cooling_device_instance to thermal_instance

This struct is used to describe the behavior for a thermal
cooling device on a certain trip point for a certain thremal zone.

thermal_cooling_device_instance is not accurate, as a cooling device
can be used for more than one trip point in one thermal zone device.

bug 1059470

Change-Id: I86484fa8cb5d502ccc21790569c1607e24921fdf
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159970
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Introduce thermal_zone_trip_update()
Zhang Rui [Wed, 27 Jun 2012 02:05:39 +0000]
Thermal: Introduce thermal_zone_trip_update()

This function is used to update the cooling state of
all the cooling devices that are bound to an active trip point.

This will be used for passive cooling as well, in the future patches.
as both active and passive cooling can share the same algorithm,
which is

1. if the temperature is higher than a trip point,
   a. if the trend is THERMAL_TREND_RAISING, use higher cooling
      state for this trip point
   b. if the trend is THERMAL_TREND_DROPPING, use lower cooling
      state for this trip point

2. if the temperature is lower than a trip point, use lower
   cooling state for this trip point.

bug 1059470

Change-Id: I01a713e5fed43369f3d43d0ef4999e5d478bdfea
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159969
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoARM: tegra: soctherm: Update thermal register
Joshua Primero [Tue, 23 Oct 2012 21:29:23 +0000]
ARM: tegra: soctherm: Update thermal register

Update soctherm driver's thermal register call due
to update in Linux Thermal API.

bug 1059470

Change-Id: Ib622f89e680a7fbb44d5212eba525be2c9a64a02
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/159968
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agodrivers: nct: tsensor: Update thermal register
Joshua Primero [Tue, 23 Oct 2012 21:27:18 +0000]
drivers: nct: tsensor: Update thermal register

Updated thermal register function for tsensor and nct thermal
drivers due to Linux thermal API change.

bug 1059470

Change-Id: Ic4ca347c6fcc1aad156122147a7c94a5f3880985
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/159967
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Remove tc1/tc2 in generic thermal layer.
Zhang Rui [Wed, 27 Jun 2012 01:51:12 +0000]
Thermal: Remove tc1/tc2 in generic thermal layer.

Remove tc1/tc2 in generic thermal layer.
.get_trend() callback starts to take effect from this patch.

bug 1059470

Change-Id: I69ea5306c9e76b0dae8eb6ad4b89335068e78f9b
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Valentin, Eduardo <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159966
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Introduce .get_trend() callback.
Zhang Rui [Wed, 27 Jun 2012 01:54:33 +0000]
Thermal: Introduce .get_trend() callback.

According to ACPI spec, tc1 and tc2 are used by OSPM
to anticipate the temperature trends.
We introduced the same concept to the generic thermal layer
for passive cooling, but now it seems that these values
are hard to be used on other platforms.

So We introduce .get_trend() as a more general solution.

For the platform thermal drivers that have their own way to
anticipate the temperature trends, they should provide
their own .get_trend() callback.
Or else, we will calculate the temperature trends by simply
comparing the current temperature and the cached previous
temperature reading.

bug 1059470

Change-Id: I85ca51d87ae8fde8429a83399a81979a41913218
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Valentin, Eduardo <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159965
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Tested-by: Joshua Primero <jprimero@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoarm: tegra: baseband: enable autosuspend for Icera PID 0x310
Neil Patel [Tue, 30 Oct 2012 18:54:34 +0000]
arm: tegra: baseband: enable autosuspend for Icera PID 0x310

Enable autosuspend for all Icera modems with product ID 0x310.

Bug 1167714

Change-Id: Ie94600e80be2fa305383cf36d5d77d92f8513149
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/159947
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: baseband: enable oob remote wake and reset detection
Neil Patel [Thu, 1 Nov 2012 14:43:02 +0000]
arm: tegra: baseband: enable oob remote wake and reset detection

Out of band remote wakeup and reset detection for Icera modems was
disabled during T114 bringup and needs to be re-enabled.

Bug 1169035

Change-Id: I0c720f18bcf91dab01051d6e15a866ae2c8053c7
Signed-off-by: Neil Patel <neilp@nvidia.com>
Reviewed-on: http://git-master/r/160601
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>

6 years agoARM: tegra11x: make SMP disabled compiles
Jong Kim [Fri, 19 Oct 2012 23:32:25 +0000]
ARM: tegra11x: make SMP disabled compiles

Make kernel compiles for disabled CONFIG_SMP.

bug 1057875

Change-Id: Ie7161a86279d31245290f4e74027c1cc5e646790
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/160361
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

6 years agoarm: tegra: isomgr: fix incorrect comparison in isomgr.
Krishna Reddy [Wed, 31 Oct 2012 00:14:42 +0000]
arm: tegra: isomgr: fix incorrect comparison in isomgr.

fix incorrect bandwidth available check comparison during reserve.
check for validity of clients.
support specifying the clients based on soc.
fix format issues.
add missing sysfs nodes for isomgr.

Change-Id: Iad7a95b923397e9e8210c9fc42981095f3045bcd
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/160056
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>

6 years agoARM: tegra11: dvfs: Update DFLL range configuration
Alex Frid [Sat, 27 Oct 2012 02:01:57 +0000]
ARM: tegra11: dvfs: Update DFLL range configuration

Replaced boolean DFLL usage configuration option with integer
TEGRA_USE_DFLL_RANGE option that specifies default range for
DFLL to be used as CPU clock source:
"0" - DFLL is not used,
"1" - DFLL is used as a source for all CPU rates
"2" - DFLL is used only for high rates above crossover with
PLL dvfs curve

Made sure that valid cvb tables for DFLL and PLL modes provide
crossover between DFLL and PLL dvfs voltage ranges.

Change-Id: Idf50ee15b7a30c10a15360f7be2079586c0118f4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/159728
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: Kconfig: enable soctherm by default
Joshua Primero [Sat, 20 Oct 2012 22:50:04 +0000]
ARM: tegra: Kconfig: enable soctherm by default

Soctherm is ready to be enabled.

bug 1169070

Change-Id: I51236e333267c88b07e3883813200007059ebb8f
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/146157
(cherry picked from commit e49070901be252c87811eaadf75668337433206a)
Reviewed-on: http://git-master/r/159500
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoARM: tegra11: secure os: disable normal os timer
Hyung Taek Ryoo [Fri, 26 Oct 2012 14:31:12 +0000]
ARM: tegra11: secure os: disable normal os timer

The timer is handled by the secure os for T11x.
Hence disable timer in normal os when secure os is enabled.

Change-Id: I64639e1f69bca39fdc6e149000f8de8c821ab485
Signed-off-by: Hyung Taek Ryoo <hryoo@nvidia.com>
Reviewed-on: http://git-master/r/159123
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agovideo: tegra: host: use platform bus/driver/device
Mayuresh Kulkarni [Fri, 26 Oct 2012 13:17:24 +0000]
video: tegra: host: use platform bus/driver/device

- this commit replaces the custom nvhost bus/driver/device
with platform bus/driver/device
- this is in preparation to add DT support
- following is the list of notable changes done:

1. chip_ops: The per SoC differences is encapsulated by chip_ops structure.
With nvhost_bus:
- It is hidden in nvhost_bus and exposed APIs to rest of the code.
These APIs land up in correct implementation for current SoC.
With platform_bus:
- I had to make this global and adjust the API accordingly.

2. nvhost_device
With nvhost_bus:
- The struct nvhost_device encapsulates both Linux device driver parts
as well as tegra specific parts.
With platform_bus:
- I had to move the current nvhost_device as a platform_data
for each platform_device. For this I renamed the struct nvhost_device
to struct nvhost_device_data.
- Also, since nvhost_driver is gone, I had to move all the
function pointers in it to struct nvhost_device_data.

3. Device specific private data: Host1x master device has its own
static data (called nvhost_master) which stores the per SoC
sync-point, IRQ info etc.
With nvhost_bus:
- This was stored as device specific platform_data.
With platform_bus:
- The device specific platform_data is now struct nvhost_device_data
(as mentioned above).
- I need to keep it common for all the devices whose code is
part of host1x directory, so that other parts of code that need per-device
info have a unique interface of platform_get_drvdata.
- As a result, I had to add a void * field in struct nvhost_device_data
which now holds per-device specific data and expose APIs to get/set this data.
- As of now, only host1x master parent device code uses this.

4. Per SoC device names:
With nvhost_bus:
- Per SoC device name is SAME for all the SoCs.
- The correct driver get linked to this device via the concept of id_table.
This id_table allows us to connect multiple devices to single driver code
and pass appropriate function pointer specific to SoC (you can check gr3d.c for details).
With platform_bus:
- The id_table usage of platform_bus is different from above.
- To adhere to its need, I had to append the per-SoC device name
with a version field (so gr3d for t20 became gr3d01, for t30 became gr3d02 etc).
- I adjusted the correct names in _probe of such devices.
Also, I adjusted the node names exposed to user space (/dev/host-gr3d etc)
to be consistent across SoCs.
- But this fails for the sysfs entries created by device registration code
of Linux, since during this time the _probe is not called.
So, device name is still appended with version field.

5. Per SoC device registration function: tegraXXX_register_host1x_devices
is the per SoC specific APIs which is called by board-file to register
the host1x and client devices. Host1x has strict requirements for the
parent->child relations i.e. any client of host1x device should have the
parent set properly BEFORE device registration.
With nvhost_bus:
- Setting of parent was taken care by nvhost_device_register call and other helpers.
With platform_bus:
- It is not possible to change parent till _probe of client device returns
(meaning not much of control in our hand). The device driver core,
takes a mutex lock of parent BEFORE calling _probe to avoid changing parent during _probe.
- So, to set correct parent, I changed the return type of
tegraXXX_register_host1x_devices to return pointer to master host1x parent device.

6. platform_get_drvdata calls:
With nvhost_bus:
- Only host1x master parent calls this.
With platform_bus:
- Almost all the common code ends up calling this.
Fortunately, we had designed the APIs such that they take nvhost_device * as argument.
So changing them to platform_device * is in a way easy.

7. Device list: The debug-fs dump code & module-reg-read-write
functionality rely on having a list of host1x devices registered currently.
With nvhost_bus:
- This is readily available since struct bus_type of Linux holds this list.
Moreover, it provides an iterators to access this list.
With platform_bus:
- Since it holds large number of devices in system, it is inefficient
to use the above iterators. Also, it is difficult to have a common matching
criteria for all the devices who have different platform_data.
- As a result, I had to add a simple list using Linux kernel's list implementation.
It holds the list of devices which have their code within host1x directory
and actually use channels (remember tegra-dc and nvavp are outside
host1x code && do not use physical channels they only need sync-point
and host1x hardware alive when they are alive).
I also had to provide 2 iterators one which is used for
module-reg-read-write and other for debug-fs dump.

8. I changed how tegra-dc and nvavp called the host1x externally exposed APIs
(such APIs end with _ext). In current code, they know little too much of
host1x code internals. I now changed to make them independent of host1x internal
implementation and structure know-how. They now simply send their own
platform_device * to the external visible APIs and these APIs
ensures that the call ends up in correct function call.

bug 1041377

Change-Id: I9cd4d506e6f3bde805923ce7c7bbbd37c9ec13c4
Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/131403
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: pluto: add ina219 power monitor devices
Mallikarjun Kasoju [Wed, 17 Oct 2012 15:10:57 +0000]
ARM: tegra: pluto: add ina219 power monitor devices

Bug 1156147

Change-Id: I9e4f01efb6e102c0637b662f6789439efca6a0c9
Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/160402
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoasoc: tegra: cs42173: modify DAPM route table
Dara Ramesh [Wed, 31 Oct 2012 17:40:24 +0000]
asoc: tegra: cs42173: modify DAPM route table

a) register DAPM route table with snd_soc_card structure and
remove the open-coded DAPM add route calls.

b) set card.fully_routed flag to request the ASoC core calculated
unused codec pins, and call snd_soc_dapm_nc_pin() for them.

Bug 1158489
Bug 1052069
Bug 1054060

Change-Id: I43e9f4dab812904e314d460edec0a2bd903f09c6
Signed-off-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-on: http://git-master/r/160252
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rahul Mittal <rmittal@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Reviewed-by: Scott Peterson <speterson@nvidia.com>

6 years agoTegra11x: defconfig: Add necessary camera devices
Rahool Paliwal [Wed, 31 Oct 2012 08:39:32 +0000]
Tegra11x: defconfig: Add necessary camera devices

This adds MAX776 flash device and AS364X torch device

Bug 1165148

Change-Id: Ied777a08e8f4ba01f6a073024a0e1edc2514aeea
Signed-off-by: Rahool Paliwal <rpaliwal@nvidia.com>
Reviewed-on: http://git-master/r/160141
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agoarm: tegra: USB: Disable STREAM_DISABLE
Petlozu Pravareshwar [Tue, 30 Oct 2012 11:50:33 +0000]
arm: tegra: USB: Disable STREAM_DISABLE

Setting STREAM_DISABLE = 0 for all USB controllers.

Bug 1166838

Change-Id: I6f540aac2175a920d5bd549e5545122b1c886a80
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/159864
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>

6 years agocpuidle: Export target residency
Antti P Miettinen [Mon, 29 Oct 2012 12:37:31 +0000]
cpuidle: Export target residency

Make cpuidle state target residency visible via sysfs.

Change-Id: Ie039bcfa943bdb4aca6cb30ac23356e4b48aa32b
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/159543
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoARM: tegra11:clock:update UTMIPLL register program
Rakesh Bodla [Wed, 31 Oct 2012 05:17:59 +0000]
ARM: tegra11:clock:update UTMIPLL register program

Update the UTMIPLL register programming sequence
to let hardware control UTMIPLL.

Bug 1057339

Change-Id: I38cca059b3f263de8382f56a5f2a0247e0df8743
Signed-off-by: Rakesh Bodla <rbodla@nvidia.com>
Reviewed-on: http://git-master/r/159449
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agocrypto: tegra-se: add chained scatter list support
venkatajagadish [Fri, 26 Oct 2012 09:07:23 +0000]
crypto: tegra-se: add chained scatter list support

This change adds chained scatter list traversing support
to S.E. Driver.

Bug 1010604

Change-Id: If4073b7cf9c8ac901b8d0bd21ddc035e1e6b7ffd
Signed-off-by: venkatajagadish <vjagadish@nvidia.com>
Reviewed-on: http://git-master/r/147890
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoarm: usb: phy: HSIC 2LS WAR using PMC resume
Vinod Atyam [Mon, 22 Oct 2012 10:23:43 +0000]
arm: usb: phy: HSIC 2LS WAR using PMC resume

Enable the 2ls war support during
AP resume and remote wakeup resume.

Bug 1028940

Change-Id: I09dc3c71b95bd83b8612624aa40a94b89d98dda7
Signed-off-by: Vinod Atyam <vatyam@nvidia.com>
Reviewed-on: http://git-master/r/146340
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoarm: tegra: pluto: enable powergate for ve
Daniel Solomon [Thu, 1 Nov 2012 00:15:22 +0000]
arm: tegra: pluto: enable powergate for ve

Enable powergate for VE.

Bug 1059495

Reviewed-on: http://git-master/r/142731
(cherry picked from commit f0706776cd7bd90eaaca3823eeb55256fac013c5)

Change-Id: I66c4c3a6a9a18ba175cc61269f3f4bd95af1ad17
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/145997
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>

6 years agoarm: tegra: rename pinmux device/driver name
Pritesh Raithatha [Fri, 19 Oct 2012 09:30:47 +0000]
arm: tegra: rename pinmux device/driver name

rename all tegra pinmux device/driver with similar names.
platform device name has size limit of 20 char.

Bug 1003210

Change-Id: Idd162fad662a364812010630856c1657b9af9c35
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/145910
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

6 years agoarm: tegra: emc: Fix the freq to bw conversion API's.
Krishna Reddy [Tue, 30 Oct 2012 23:44:11 +0000]
arm: tegra: emc: Fix the freq to bw conversion API's.

Fix the emc freq to bw conversion and vice versa API's to
return real emc freq and bandwidth numbers based on SOC.

Bug 1167105

Change-Id: I6f244d0f6626e59ed5a3707a2a564ee711a45c43
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/160043
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra: soctherm: Update bind function
Joshua Primero [Tue, 23 Oct 2012 01:11:34 +0000]
ARM: tegra: soctherm: Update bind function

Updated bind function to reflect new Thermal API.

bug 1059470

Change-Id: I77bff7ac080d663018a938ccd2fa887884ab84a5
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/159964
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agodrivers: nct: tsensor: Update bind function
Joshua Primero [Tue, 23 Oct 2012 01:09:57 +0000]
drivers: nct: tsensor: Update bind function

Update the bind function in the tsensor and nct driver to
reflect the new Thermal API.

bug 1059470

Change-Id: I527383d426ff1f70fe531a02d600735cbedea7b8
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/159963
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoThermal: set upper and lower limits
Zhang Rui [Tue, 26 Jun 2012 08:35:57 +0000]
Thermal: set upper and lower limits

set upper and lower limits when binding
a thermal cooling device to a thermal zone device.

bug 1059470

Change-Id: I90f4c79fa2af79896cb93a528fb4e4263f02587c
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159962
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Introduce cooling states range support
Zhang Rui [Tue, 26 Jun 2012 08:27:22 +0000]
Thermal: Introduce cooling states range support

As the active cooling devices can have multiple cooling states,
we may want only several cooling states for a certain trip point,
and other cooling states for other active trip points.

To do this, we should be able to describe the cooling device
behavior for a certain trip point, rather than for the entire thermal zone.
And when updating thermal zone, we need to check the upper and lower limit
to make sure the cooling device is set to the proper cooling state.

Note that this patch will not bring any different behavior as
upper limit is set to max_state and lower limit is set to 0
in this patch, for now.

Next patch will set these to real values.

bug 1059470

Change-Id: I2fcb4e01849f18d471e1481ffc9940162e60a3ec
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Eduardo Valentin <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159961
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Introduce multiple cooling states support
Zhang Rui [Tue, 26 Jun 2012 08:26:40 +0000]
Thermal: Introduce multiple cooling states support

This is because general active cooling devices, like fans,
may have multiple speeds, which can be mapped to different cooling states.

bug 1059470

Change-Id: Ibebf71a0faca1980269db48a40dc8bb7db0d2357
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Valentin, Eduardo <eduardo.valentin@ti.com>
Reviewed-on: http://git-master/r/159960
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Documentation update
Zhang Rui [Wed, 25 Jul 2012 02:11:00 +0000]
Thermal: Documentation update

With commit 6503e5df08008b9a47022b5e9ebba658c8fa69af,
the value of /sys/class/thermal/thermal_zoneX/mode has been changed
from user/kernel to enabled/disabled.
Update the documentation so that users won't be confused.

bug 1059470

Change-Id: I40e33813ad4ebb4b033c2064664b8b1fbeed31ea
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-on: http://git-master/r/159959
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agoThermal: Add Hysteresis attributes
Durgadoss R [Wed, 25 Jul 2012 02:10:59 +0000]
Thermal: Add Hysteresis attributes

The Linux Thermal Framework does not support hysteresis
attributes. Most thermal sensors, today, have a
hysteresis value associated with trip points.

This patch adds hysteresis attributes on a per-trip-point
basis, to the Thermal Framework. These attributes are
optionally writable.

bug 1059470

Change-Id: I701a72ee65048ffcdbcfa8ff88dccc170cd3715e
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Signed-off-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Reviewed-on: http://git-master/r/159958
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>

6 years agovideo: tegra: dc: Move PRISM update to V_PULSE2.
Kevin Huang [Tue, 16 Oct 2012 04:50:40 +0000]
video: tegra: dc: Move PRISM update to V_PULSE2.

Add support to update PRISM at V_PULSE2_INT. Use V_PULSE2 for PRISM
if the chip supports.

Bug 1156207

Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Change-Id: I5b908b206d647c3efce7037578b0ed86e9bb2d22
Reviewed-on: http://git-master/r/159945
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: clock: Don't convert EMC shared user requests
Alex Frid [Tue, 30 Oct 2012 03:43:00 +0000]
ARM: tegra11: clock: Don't convert EMC shared user requests

Removed conversion of EMC shared bus users bandwidth requests to EMC
bus width. Let the client drivers do it.

Bug 1167105

Change-Id: I5b7aae3d87f76171bc67cfb9cb6d8480e2122f75
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/159732
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: fb: Update fix line_length
Shashank Sharma [Thu, 25 Oct 2012 09:41:39 +0000]
arm: tegra: fb: Update fix line_length

Update framebuffer's fix line_length parameter when changing
video mode dynamically.The new line_length should be according
to new x resolution. On addition, check the return value from
dc driver while setting a mode.

Bug 1163682
Bug 1056767
Bug 1056782
Signed-off-by: Shashank Sharma <shashanks@nvidia.com>
Change-Id: Ib0ab48474f0af3235556a7f7f0d8354af3b50994
Reviewed-on: http://git-master/r/147511
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: Enterprise: Add power regulator for atmel.
Xiaohui Tao [Thu, 25 Oct 2012 01:13:52 +0000]
ARM: tegra: Enterprise: Add power regulator for atmel.

Add power regulator support for atmel

Bug 1063749

Change-Id: I0793f7f497ff75a538d1f6b2d8e31b059b5e326b
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/147120
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: Cardhu: Add power regulator for atmel.
Xiaohui Tao [Thu, 25 Oct 2012 01:12:57 +0000]
ARM: tegra: Cardhu:  Add power regulator for atmel.

Add power regulator support for atmel

Bug 1063749

Change-Id: I009cf857628486ba4d8bb2ba2c23d9aae12d3a07
Signed-off-by: Xiaohui Tao <xtao@nvidia.com>
Reviewed-on: http://git-master/r/147119
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>