6 years agoPM / Runtime: Fix rpm_resume() return value for power.no_callbacks set
Rafael J. Wysocki [Wed, 15 Aug 2012 19:31:45 +0000]
PM / Runtime: Fix rpm_resume() return value for power.no_callbacks set

For devices whose power.no_callbacks flag is set, rpm_resume()
should return 1 if the device's parent is already active, so that
the callers of pm_runtime_get() don't think that they have to wait
for the device to resume (asynchronously) in that case (the core
won't queue up an asynchronous resume in that case, so there's
nothing to wait for anyway).

Modify the code accordingly (and make sure that an idle notification
will be queued up on success, even if 1 is to be returned).

Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Cc: stable@vger.kernel.org
(cherry picked from commit 7f321c26c04807834fef4c524d2b21573423fc74)
Change-Id: Iad6e733535469a54932ab89574c1da356ce749a5
Reviewed-on: http://git-master/r/145852
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: pluto/dalmore: set VGP4 pinmux
Charlie Huang [Fri, 5 Oct 2012 20:30:57 +0000]
ARM: tegra: pluto/dalmore: set VGP4 pinmux

set the default mux to VGP4 and remove the gpio override in
board-pluto-sensors.c

Change-Id: Id08d0d53b75a67bc48df50cfe3a4fef7f1697be1
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit 5abc81df675eae63f69780d230fb54b37775d904)
Reviewed on: http://git-master/r/#change,142064
Reviewed-on: http://git-master/r/145668
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoARM: tegra: config: enable flash AS3648
Charlie Huang [Sat, 8 Sep 2012 01:16:55 +0000]
ARM: tegra: config: enable flash AS3648

Device is enabled in both tegra3 and tegra114 defconfig files.

bug 1048411

Change-Id: Ib66684870262b73cfc7c315d4571e2967b75a95c
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit 481e9d0dcdb141abe49f8a1c4285b5e5beee194e)
Reviewed on: http://git-master/r/#change,133127
Reviewed-on: http://git-master/r/145662
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sivasubramaniam Venkataraman <svenkatarama@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agomedia: tegra: as3648: initial driver bring up
Charlie Huang [Fri, 7 Sep 2012 20:43:16 +0000]
media: tegra: as3648: initial driver bring up

New flash controller with dual led outputs, as well as over-current
protection, low-voltage protection, flash timeout control, etc.

bug 1048411

Change-Id: I20a74229cc357a4b93ed3ed70e663ef0acc258d9
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit f84be39819cd40e2bfbc839ca7dd74c1143893be)
Reviewed on: http://git-master/r/#change,133114
Reviewed-on: http://git-master/r/145660
Reviewed-by: Sivasubramaniam Venkataraman <svenkatarama@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoMerge "Merge commit 'maxtouch-v3.0-16-Oct-2012' into ToT_2012-10-16_10-30-AM" into...
Simone Willett [Tue, 23 Oct 2012 01:38:18 +0000]
Merge "Merge commit 'maxtouch-v3.0-16-Oct-2012' into ToT_2012-10-16_10-30-AM" into android-tegra-nv-3.4

6 years agoARM: tegra11: clock: keep pll_re_vco disabled by default
Amit Kamath [Tue, 16 Oct 2012 11:34:38 +0000]
ARM: tegra11: clock: keep pll_re_vco disabled by default

Increases power consumption on rail AVDD_PLLE_AP
Bug 1158466

Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/144870
(cherry picked from commit b95079cbffdbdde0ef707b3a5472ef69145b625d)

Change-Id: I5121b335bf995c90f84d879e65e06b9d89efcc26
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146355
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: Tegra: clock: Change default state of pll_p_out3
Prashant Gaikwad [Mon, 15 Oct 2012 13:40:37 +0000]
ARM: Tegra: clock: Change default state of pll_p_out3

pll_p_out3 was kept on since some peripherals had it as
fixed parent. Currently all drivers for those peripherals
implement enable/disable for clocks derived from it.
No need to keep it enabled all the time.

Bug 1155689

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/144572
(cherry picked from commit aa8df6af70b835eff2e150bd1f11e71313f982fa)

Change-Id: I33b3268bcf1abcdf483b4166df993538324f2b26

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: I7ea5d46a219138b14cb540c60dbbdf80d341526b
Reviewed-on: http://git-master/r/146354
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: decrease sclk min limit
Amit Kamath [Wed, 3 Oct 2012 09:24:12 +0000]
ARM: tegra11: clock: decrease sclk min limit

Change-Id: Iacd2339ba423363c89e6d81109cb88bb965115d5
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/141213
(cherry picked from commit 7720d2de96f9d726de0ddafddccee25760b2687c)
Reviewed-on: http://git-master/r/145587
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: pluto: Trim EMC DFS table
Alex Frid [Fri, 12 Oct 2012 22:51:41 +0000]
ARM: tegra: pluto: Trim EMC DFS table

Removed experimental low frequency entries from EMC DFS table.
Updated 408MHz and 204MHz entries.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/144242
(cherry picked from commit 7f48e9d4e0f183dda38cac487e5a7cb7840b121c)

Change-Id: Ied785e86dd1d8ee7a3903000bb6a17c9c826c451

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: Iddea47f41ad3ba7eaf2be2b5c693d5b08cf909d4
Reviewed-on: http://git-master/r/146339
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: pluto: Change clock source pll_m to pll_p
Vijay Mali [Tue, 2 Oct 2012 21:09:10 +0000]
ARM: tegra: pluto: Change clock source pll_m to pll_p

Change clock source from pll_m to pll_p for lower emc frequencies

Signed-off-by: Vijay Mali <vmali@nvidia.com>
Reviewed-on: http://git-master/r/143406
(cherry picked from commit bdd5886c50ba44a3092b2dc39d5c341dedab3d76)

Change-Id: I869a274d0f895bdc3609f81304d3ea1a5e8f9dd6

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: I4d9fb86966fbef670506f30153524724fe75d2b0
Reviewed-on: http://git-master/r/146338
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Tested-by: Vijay Mali <vmali@nvidia.com>

6 years agoARM: tegra: pluto: Update EMC tables
Daniel Solomon [Sun, 30 Sep 2012 07:29:01 +0000]
ARM: tegra: pluto: Update EMC tables

Update EMC tables with preliminary values, power
features included.

Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/143298
(cherry picked from commit a0a5bb60ac100e239b9d1c21580efaad96e78caf)

Change-Id: I1d2178d3ac613f3c7c0591356a0270dd89f2e35c

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: If9a104c26be9c04389cb6f1f7d81312b6f4aed8f
Reviewed-on: http://git-master/r/146337
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: fix build errors with tegra3 boards
Bharat Nihalani [Mon, 22 Oct 2012 07:35:05 +0000]
ARM: tegra: fix build errors with tegra3 boards

Dalmore and Pluto boards still get built for tegra3. Fix build
errors for such combination. This needs to be cleaned up as we
no longer need this combination to be supported.

Also fix issues that complain for 'defined but un-used' errors.

Change-Id: Ie41021cdf15ea62d1e704ea6e6e22d9f2224220d
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146290
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: clock: Switch from DFLL to PLL at low rate
Alex Frid [Thu, 11 Oct 2012 01:21:10 +0000]
ARM: tegra11: clock: Switch from DFLL to PLL at low rate

Added an option to automatically switch CPU clock source from DFLL
to PLL when target CPU rate is below DFLL minimum rate (instead of
using skipper). This option is disabled by default, and it is
controlled by /sys/module/tegra11_clocks/parameters/use_pll_cpu_low
parameter.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145169
(cherry picked from commit 0996421f20bedc55d605c89451f4680b616ba093)

Change-Id: Ieef31928d3f76c82fc4ced018c87acebbf84a5ac
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146289
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dvfs: Force CPU rail update
Alex Frid [Wed, 17 Oct 2012 03:08:56 +0000]
ARM: tegra: dvfs: Force CPU rail update

To force CPU rail update on exit from DFLL mode:

- altered by 1mV recorded rail level in DFLL mode, so that it won't
match any target level after switch from DFLL to PLL (actual level
in DFLL mode is approximately close to the recorded, anyway)

- altered by 1mV maximum limit requested from regulator, so that
core regulator call is not resolved as NOP (tegra dvfs would not
call core API to set the same voltage, with the exception of special
cases like switch from DFLL - and in these cases we do not need core
second guess).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145168
(cherry picked from commit e18df75763f0d9f6980a2d77ed8e532afda4e96d)

Change-Id: I45271085bc1cdd9176a9a136b389292c6336ed35
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146288
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Fix G-to-G CPU switch
Alex Frid [Thu, 18 Oct 2012 01:47:49 +0000]
ARM: tegra11: clock: Fix G-to-G CPU switch

Made sure that forced G-to-G CPU cluster switch does not mess up
CPU clock sources (it was erroneously switching from DFLL to PLL).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145452
(cherry picked from commit 2ce09a9506200c96410842d1714ca294c7b81344)

Change-Id: If4e5d783c92e7d970b79448cf2368168034edb87
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146287
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Use cvb model for pll clock source
Alex Frid [Tue, 16 Oct 2012 23:54:58 +0000]
ARM: tegra11: dvfs: Use cvb model for pll clock source

Added separate cvb coefficients for calculating CPU dvfs table with
pll clock source (instead of just adding margin on top of dfll source
voltage). This data is preliminary, pll source is disabled by default.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145167
(cherry picked from commit 02fb97ea8f2c47716760e64405ab19af9d8bbd0c)

Change-Id: I6adbcfa04ac7982a2f1bb27eb6e0b07f68b05304
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146286
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Don't apply dfll min voltage in pll mode
Alex Frid [Thu, 4 Oct 2012 05:17:13 +0000]
ARM: tegra11: dvfs: Don't apply dfll min voltage in pll mode

- do not apply minimum dfll voltage limit in pll mode, and allow
voltage to go as low as cvb dvfs table output suggest.
- do not strip dvfs frequencies with predicted cvb voltage below
minimum dfll voltage, since they can be reached in pll mode

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141748
(cherry picked from commit 008ede787fbe6c10773e2b872a589f2870b033d4)

Change-Id: I0d5d5f756f76913a021b86c562daa13090938e81
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146285
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Move min millivolts to dfll_data
Alex Frid [Thu, 4 Oct 2012 03:19:20 +0000]
ARM: tegra11: dvfs: Move min millivolts to dfll_data

Moved minimum millivolts entry from upper level cpu dvfs data to
dfll specific data, since it should be applied in dfll mode only
(for now, it is still applied in both pll and dfll modes).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141747
(cherry picked from commit d0b1b98c07bcce2e321d0db6e10ffcdb0425f43e)

Change-Id: I4ecc0505316a137151112b00a41d93a2142a7ba2
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146284
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dalmore: Add EMC DFS table for E1611 board
Alex Frid [Sat, 6 Oct 2012 03:31:30 +0000]
ARM: tegra: dalmore: Add EMC DFS table for E1611 board

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/144371
(cherry picked from commit 1766f2e6193282d7b2d4e8d471017631acab2e8f)

Change-Id: I3db76ce78c3370e2d06e98e943b91032c5172a18
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146283
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update DFLL switch error handling
Alex Frid [Thu, 11 Oct 2012 02:35:44 +0000]
ARM: tegra11: clock: Update DFLL switch error handling

The changes below provide WAR for possible I2C deadlock if CL-DVFS
output is disabled while the I2C request is pending.

- Switch to Open Loop mode at the beginning of unlocking API (this
guarantees at most 2 outstanding transaction), drain pending (if any)
transactions, and then disable output.

- Separated cl_dvfs output_enable() and output_disable() operations.
Swap the order of waiting for output interface quiet and disabling
the output: first wait for quiet interface, and then disable output.
Re-enable interface if pending request is set again and continue
waiting until quiet state is confirmed or timeout is expired. Passed
timeout error to the caller of unlocking API.

- When switching CPU clock source from DFLL to PLL, restore DFLL
clock source and DFLL rail control in case of switch error,
including unlock timeout error.

- When switching from CPU G mode to CPU LP mode, re-lock DFLL in
case of switch error, including unlock timeout error.

- When switching CPU clock source from PLL to DFLL, move control
of VDD_CPU rail to DFLL even if it failed to lock (lock failure
should never happen here, and WARN() will be replaced with BUG()).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/144305
(cherry picked from commit 6c2782755b082b005fc7ce8e82e9f051e64bfbf1)

Change-Id: I4b4229f2737eed9bdffca2efbd08fc9a5ac058e3
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146282
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Remove pll table restriction
Alex Frid [Sat, 13 Oct 2012 05:28:59 +0000]
ARM: tegra11: clock: Remove pll table restriction

Removed requirement for dynamic ramp PLLs tabulated configuration to
always use post-divider 1 for rate above VCO minimum. Too restrictive,
and not necessary.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/144306
(cherry picked from commit 3ae859c123866d5270234af745790b4bb8fa36b9)

Change-Id: If1ffc488d1b826ae3e648a9354db0c63f31e7271
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146280
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Add PLLC rate initialization
Alex Frid [Thu, 11 Oct 2012 19:43:54 +0000]
ARM: tegra11: clock: Add PLLC rate initialization

Added explicit PLLC rate configuration to clock table in case of
dual cbus (for a single cbus it is configured implicitly as part
of cbus initialization).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/143818
(cherry picked from commit 00018f0040b4628bd8424da64d89cc4fd2e2ee32)

Change-Id: I9ebf3b2aa2f69df2c5b265238a9bd9aa4c532657
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146279
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Initialize pll_re_vco to 312 MHz
Alex Frid [Sat, 6 Oct 2012 00:21:28 +0000]
ARM: tegra11: clock: Initialize pll_re_vco to 312 MHz

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142128
(cherry picked from commit 218e7e5f5fc097198d56980818b0c510b588be3b)

Change-Id: Ia152b61a9f3df7662a9be67bc13afe0b1d7f978e
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146278
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Dynamically allocate cl dvfs object
Alex Frid [Tue, 9 Oct 2012 07:44:14 +0000]
ARM: tegra11: dvfs: Dynamically allocate cl dvfs object

Dynamically allocated cl dvfs object by the cl-dvfs driver, and
hide cl_dvfs structure definition from clock framework.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142851
(cherry picked from commit a2adb1710edc52c61b1fa336e5253aa5735ec717)

Change-Id: I6dd1af043d15aba143bdf02bb53dd1e796784626
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146277
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Acquire CL-DVFS clocks in probe
Alex Frid [Tue, 9 Oct 2012 06:00:48 +0000]
ARM: tegra11: dvfs: Acquire CL-DVFS clocks in probe

Acquired CL-DVFS clocks in driver probe function (instead of
pre-populating during dfll initialization).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142850
(cherry picked from commit 66dc99a9ce766bb464a1ddfab49cf89776fc006b)

Change-Id: I9b94f9c61f7b0a76ae3433fe752b0ed5e1941cb6
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146276

6 years agoARM: tegra: pluto: Add EMC DFS table
Alex Frid [Fri, 28 Sep 2012 21:39:55 +0000]
ARM: tegra: pluto: Add EMC DFS table

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139824
(cherry picked from commit f751de8bd24dcdd3387b3ecc9c8fb59d01890cdf)

Change-Id: I222518dae63800f7800bc893e1d30ad92ece466b
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146275
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Enable PLLE VREG
Alex Frid [Wed, 10 Oct 2012 02:00:28 +0000]
ARM: tegra11: clock: Enable PLLE VREG

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142829
(cherry picked from commit 099ccea9a52f351826a1200759e67718213ac1a1)

Change-Id: I95aa4bc199633693810fda505156444137da120e
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146274
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Put PLLU under h/w control
Alex Frid [Mon, 8 Oct 2012 23:14:26 +0000]
ARM: tegra11: clock: Put PLLU under h/w control

Put PLLU under h/w control, let s/w enable bits for secondary PLLU
dividers to be cleared.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142507
(cherry picked from commit 971e348d8317416b4f51d32c3515087c7c6dc18a)

Change-Id: I0b3692f1ba653eaea31c4cdd329ee5e5ed01f0d7
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146273
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dalmore: Add E1611 EMC DFS table template
Alex Frid [Fri, 5 Oct 2012 21:45:26 +0000]
ARM: tegra: dalmore: Add E1611 EMC DFS table template

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142127
(cherry picked from commit df6a6a5a2685655d1fa940485632264e5e1d0abd)

Change-Id: Ifdbe8190e08a27d9123e1bb12006430282a0a162
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146272
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update PLLC2/C3 configuration
Alex Frid [Tue, 25 Sep 2012 21:50:06 +0000]
ARM: tegra11: clock: Update PLLC2/C3 configuration

- Lower vco min to 600MHz
- Do not allow multiples of 3 as post divider values
- Extend unlock frame number

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/138754
(cherry picked from commit 8dea2e5438e76717931b34f5ee3d1f9a88703f0b)

Change-Id: I9fb441f5cadc23ab78f836438ee8aefade6b310d
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146271
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Add CL-DVFS platform device
Alex Frid [Sun, 7 Oct 2012 05:10:00 +0000]
ARM: tegra11: dvfs: Add CL-DVFS platform device

Added CL-DVFS platform device. Converted CL-DVFS module to platform
device driver, used driver registration to get CL_DVFS platform data
instead of calling board level API.

Change-Id: I5283e80c5d43f0259743b55bd3ad6783c639b090
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142169
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146270
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: dvfs: Update CL-DVFS max voltage dynamically
Alex Frid [Wed, 3 Oct 2012 23:02:17 +0000]
ARM: tegra11: dvfs: Update CL-DVFS max voltage dynamically

Dynamically update CL-DVFS maximum voltage when target frequency
is changed (instead of keeping it at chip reliability limit always).
New maximum level is matching safe dvfs table entry for the requested
frequency.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141746
(cherry picked from commit e37e77eba2307e34489f9ac012d7fb7b5c405a29)

Change-Id: I01f6c8b3204e272441ddeafa1e2dc4bb5c3e252c
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146269
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Return CL-DVFS monitored rate
Alex Frid [Tue, 2 Oct 2012 20:33:57 +0000]
ARM: tegra11: dvfs: Return CL-DVFS monitored rate

When reading CL-DVFS monitor, convert readout into Hz.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141138
(cherry picked from commit 4fd847d5c6fa487b7ca4d1824af7afa55f5964d6)

Change-Id: Ib424c2aa27fc95664748ed8ddc47157710663ae7
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146268
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Select TEGRA_USE_DFLL config option
Alex Frid [Tue, 25 Sep 2012 04:45:26 +0000]
ARM: tegra11: dvfs: Select TEGRA_USE_DFLL config option

Change-Id: Ibd45d2de42fbbb9ecd87f7cdec53df73bd7b7ecb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/135001
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146267
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Remove CL-DVFS I2C fast clock
Alex Frid [Tue, 2 Oct 2012 20:08:40 +0000]
ARM: tegra11: dvfs: Remove CL-DVFS I2C fast clock

Since CL-DVFS I2c controller does not have i2c_fast clock, removed
the latter from CL-DVFS list of clocks.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141137
(cherry picked from commit 4478aca99834686e338636798f2c9e6841ddda9b)

Change-Id: Iac84c6968502a6b7023025a92e900900ded1a5d1
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146266
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Add DFLL resume operation
Alex Frid [Sun, 30 Sep 2012 02:58:53 +0000]
ARM: tegra11: clock: Add DFLL resume operation

- Implemented DFLL resume including CL-DVFS state restoration.
- Moved G-CPU clock resume after DFLL.
- Made sure that LP-CPU clock is enabled before cluster switch on
entry to LP0 (it can be disabled on tegra11 if G-CPU is on DFLL).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/140004
(cherry picked from commit 09f59e09eab56e855ab36c43244f0e04a3246216)

Change-Id: I90cf3f5c8c54bb99303851b30b42da49b47e208f
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146265
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update cpufreq table construction
Alex Frid [Mon, 1 Oct 2012 20:31:28 +0000]
ARM: tegra11: clock: Update cpufreq table construction

Use G CPU dvfs table step (102 MHz) to fill in the gap between
maximum LP CPU and minimum G CPU rates for construction of cpufreq
table

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/140757
(cherry picked from commit 826d7351d94518a19df5d7a9739d76e35a60e1f8)

Change-Id: I24cfecc466254ef0085112253f17980c41f0d8a4
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146264
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Fix CL-DVFS output mapping
Alex Frid [Mon, 1 Oct 2012 20:11:21 +0000]
ARM: tegra11: dvfs: Fix CL-DVFS output mapping

Since commit 4adbd45cddd9efdbc12e0e668cf562aca3bed38d allows two
top entries in dvfs frequency list with the same (maximum) safe
voltage, updated CL-DVFS output mapping procedure, to continue
mapping when maximum voltage is reached.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/140756
(cherry picked from commit ef925a158c7a52b9761f653787f57faac21f106e)

Change-Id: I5134ccea757e380660b484bdaa20020b1bad9440
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146263
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Increase maximum EMC rate at nominal voltage
Alex Frid [Mon, 1 Oct 2012 07:11:44 +0000]
ARM: tegra11: dvfs: Increase maximum EMC rate at nominal voltage

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/140554
(cherry picked from commit 181455d601f3c1e6a25d32b9a0bd23d37e20362f)

Change-Id: I7b1a8796d313c00c8b9414e3851873a8b615074f
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146262

6 years agoARM: tegra: power: Suspend/resume cpu dfll mode
Alex Frid [Sat, 29 Sep 2012 02:57:41 +0000]
ARM: tegra: power: Suspend/resume cpu dfll mode

If DFLL is used as CPU clock source switch to open loop mode before
cpu rail is turned off when rail-gating during idle (LP2 last), or
suspending the system (entering LP1 or LP0 states). Consolidated this
controls in pm.c file.

Change-Id: I8ed7f29a733225533dd94cce0b14f66dad258310
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139930
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146261
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Add dummy EMC ccfifo write
Alex Frid [Sun, 30 Sep 2012 03:32:18 +0000]
ARM: tegra11: clock: Add dummy EMC ccfifo write

Added dummy EMC ccfifo write to read-only register to make sure that
at least one ccfifo write is pushed after stall-after-change marker.
Without this dummy write EMC ccfifo (and the entire system) will hang
after clock change that does not update other registers via ccfifo.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139974
(cherry picked from commit 2c57e98d8b4e2781666412773f10794e707d2e7f)

Change-Id: I9784986c129fd60dcdf17af2fd7eb0088fbaf43e
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146260
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Round up CPU dvfs frequency list
Alex Frid [Sat, 29 Sep 2012 04:52:11 +0000]
ARM: tegra11: dvfs: Round up CPU dvfs frequency list

When predicted cpu voltage in dfll mode crosses maximum limit, keep
the respective frequency in the dvfs table ("round the list up"). The
voltage limit will be enforced anyway, and when the top frequency is
requested dfll will settle at whatever high rate it can reach on the
particular chip.

This change is relevant only until cvb coefficients characterization
is completed. With production coefficients predicted voltage will
never exceed maximum limit.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139929
(cherry picked from commit 4adbd45cddd9efdbc12e0e668cf562aca3bed38d)

Change-Id: I7bb034d193385b726742d7ee1ff83a5ade8f63cf
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146259
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Update CPU rate and voltage range
Alex Frid [Fri, 28 Sep 2012 20:11:16 +0000]
ARM: tegra11: dvfs: Update CPU rate and voltage range

- Set CPU voltage range 1.0V ... 1.230V
- Extended CPU frequency range up 1836 MHz

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139799
(cherry picked from commit df0d52bd4b2f8f90b756674c4e6d23bc7fd20345)

Change-Id: Ia8e7dac2d543d5de46d3396f9fbd9b2b02e9fe30
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146258
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: pluto: Add EMC DFS template
Alex Frid [Fri, 28 Sep 2012 03:09:50 +0000]
ARM: tegra: pluto: Add EMC DFS template

Created EMC DFS template and registered EMC device (with empty
table, for now).

Change-Id: I83e4ad4660855f3a50fc644b358641b5c10e493d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139558
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146257
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dalmore: Add EMC DFS template
Alex Frid [Thu, 20 Sep 2012 23:46:12 +0000]
ARM: tegra: dalmore: Add EMC DFS template

Created EMC DFS template and registered EMC device (with empty
table, for now).

Change-Id: Icf1e8d6decb9de36f884ada44536b02f8f7064ca
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139289
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146256
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: pluto: Add CL-DVFS platform data
Alex Frid [Sun, 23 Sep 2012 06:42:01 +0000]
ARM: tegra: pluto: Add CL-DVFS platform data

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134650
(cherry picked from commit bd48d0c476a63dde113449796517650dd30d04fc)

Change-Id: I33beb954484d0f4a817b29c4c2a7f5a14bb95a1d
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146255
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: dvfs: Add TEGRA_USE_DFLL config option
Alex Frid [Tue, 25 Sep 2012 04:27:41 +0000]
ARM: tegra: dvfs: Add TEGRA_USE_DFLL config option

Change-Id: Ie8766c6860dbc87f3b36618cafb9f6792b3fef02
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/135000
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146254
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Increase PLLX vco max limit
Alex Frid [Tue, 25 Sep 2012 07:11:18 +0000]
ARM: tegra11: clock: Increase PLLX vco max limit

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/135025
(cherry picked from commit d6ebf5cecb2a6ca27b5921d7a990266bcdf05f6c)

Change-Id: Icaf66d47df756992ac92f758693caddb980ea16a
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146253
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Keep PLLE under s/w control
Alex Frid [Tue, 25 Sep 2012 07:07:31 +0000]
ARM: tegra11: clock: Keep PLLE under s/w control

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/135024
(cherry picked from commit 1709a98df3d07ff549b20eb5a11d93fdde2da4d3)

Change-Id: I38f73ca41d46782db8f1468b6aca750cbb5874bd
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146252
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: fuse: Read speedo values from chip fuses
Alex Frid [Tue, 25 Sep 2012 04:15:27 +0000]
ARM: tegra11: fuse: Read speedo values from chip fuses

Based on original work by Matthew Longnecker <mlongnecker@nvidia.com>

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134999
(cherry picked from commit d7b619c8ea77cf52c90a27448d1183b3e0899218)

Change-Id: I327d0d39efccfd7e189c02370c9c7f95252172fc
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146251
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Increased CPU min voltage limit
Alex Frid [Mon, 24 Sep 2012 21:22:12 +0000]
ARM: tegra11: dvfs: Increased CPU min voltage limit

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134921
(cherry picked from commit d938033c90cf017bf75f2360da1dc98a8eebadec)

Change-Id: I64b4df3a28d4ce9ae98487c7524d8951ae71735f
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146250
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update PLLC2/C3 settings
Alex Frid [Sun, 23 Sep 2012 05:14:39 +0000]
ARM: tegra11: clock: Update PLLC2/C3 settings

Bug 1053337

Change-Id: I2dd8e376d198e442b1a0b7a4de76785c263bc76d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134649
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146249
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update EMC DFS table format
Alex Frid [Thu, 20 Sep 2012 22:03:20 +0000]
ARM: tegra11: clock: Update EMC DFS table format

Moved trimmers registers from common burst array to per-channel
trimmers arrays. Change array order in table structure. Fixed
start timing rate calculation.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134259
(cherry picked from commit 0505cfc8f5b9c6e11adf60d68788ef3c0f385222)

Change-Id: I33fc718e234234efbda0e34acc657cdaaecd1455
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146248
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Modify dqs preset operation
Alex Frid [Sun, 16 Sep 2012 06:44:30 +0000]
ARM: tegra11: clock: Modify dqs preset operation

Modified dqs preset operation during EMC clock change to work on
separate settings for EMC channel 0 and 1.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/133065
(cherry picked from commit b487cbda920e8eaf783d3b8ea0fb7a9dba0a5f4f)

Change-Id: Ia802a3194495df784a198859f33ee6ea004af6bd
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146247

6 years agoARM: tegra11: clock: Add use dfll parameter callback
Alex Frid [Thu, 20 Sep 2012 07:01:42 +0000]
ARM: tegra11: clock: Add use dfll parameter callback

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134268
(cherry picked from commit 1766f138bd046c83b1f5b684f0d15a9106961e83)

Change-Id: If1a7fa26785819f649e4351965968b4130aad15c
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146246
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update switch to/from dfll clock source
Alex Frid [Wed, 19 Sep 2012 23:28:05 +0000]
ARM: tegra11: clock: Update switch to/from dfll clock source

- Updated dvfs state variables and stats when switching to/from dfll
clock source.
- Made sure nominal voltage level is restored when switching from dfll
with disabled rail scaling.
- Round down target rate when switching from dfll to pll if it exceeds
pll mode maximum limit
- Implement 1-step dfll to pll switch directly to the new rate (instead
of 2-step switch from dfll to pll at the old rate, and then to the new
rate already on pll).

Change-Id: I13cfb89b47905cbc7c8b27a30cbc6472d4f651f3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/133969
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146245

6 years agoARM: tegra11: power: Read LPDDR2/3 temperature
Alex Frid [Thu, 30 Aug 2012 06:39:48 +0000]
ARM: tegra11: power: Read LPDDR2/3 temperature

Change-Id: I52ab569c3568f7e47c5d4a5ce6f151fa51bbad08
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/132380
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146244
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dalmore/pluto: fix palmas init
Pradeep Goudagunta [Fri, 12 Oct 2012 08:46:19 +0000]
ARM: tegra: dalmore/pluto: fix palmas init

Fix palmas platform data initialization.

Reviewed-on: http://git-master/r/144026
(cherry picked from commit df44ead1c39ca281f87f4242d10512cb39e14203)

Conflicts:

arch/arm/mach-tegra/board-dalmore-power.c

Change-Id: I9fecaab84dac6e90e3a159f5eca0b7dc5c13b6f8
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/145891
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agomfd: palmas: Change regulator defns to better suite DT
Graeme Gregory [Tue, 28 Aug 2012 11:47:39 +0000]
mfd: palmas: Change regulator defns to better suite DT

In order to better fit DT parsing in of regulator definitions re-arrange
the platform data struct slightly which requires the definitions of
the regulator IDs earlier in the include file.

Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
(cherry picked from commit 7cc4c92fbc1b539597c00656b3236a57d76022f4)

Conflicts:

include/linux/mfd/palmas.h

Reviewed-on: http://git-master/r/144024
(cherry picked from commit bb762eccf74e729a907f22ee570d2743fada10f2)

Change-Id: Ic429548c054f2c8448c7a7aeb1d574d0631db62c
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/145889
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: pluto: pinmux: fix UARTA
Pradeep Goudagunta [Fri, 21 Sep 2012 22:58:35 +0000]
ARM: tegra: pluto: pinmux: fix UARTA

KB pins are configured to UARTA in BL so make them
RSVD1 to deselect/clear UARTA selection.

Bug 1047414

Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/134261
(cherry picked from commit 8f05f246dbc87001363132b6af95d14be3a94dd1)
Change-Id: I0bc7b62e8eb353e19506b80165b85c38582dfe57
Reviewed-on: http://git-master/r/145885
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: dalmore/pluto: increase framebuffer size
Jon Mayo [Thu, 18 Oct 2012 18:47:33 +0000]
ARM: tegra: dalmore/pluto: increase framebuffer size

Increase reserved framebuffer size to be twice the maximum resolution.
This is required for android recovery to do double buffering on /dev/fb0.

Change a spammy print from info to debug.

Bug 1054266
Bug 1159399

Change-Id: Icdcdec23133190e19de8d26c98f8b2f6ec8d9c24
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/145673
Reviewed-by: Automatic_Commit_Validation_User

6 years agomedia: tegra: imx091: fix pinkish preview issue
Frank Chen [Thu, 11 Oct 2012 18:04:13 +0000]
media: tegra: imx091: fix pinkish preview issue

Do software reset instead of standby before
programming the new sensor mode.

Bug 1156556

Change-Id: Icba79ff790905c810ed88533b74287b458d98423
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/143791
(cherry picked from commit 816c361834aa5a8c7a490a79088ae52047fe38f7)
Reviewed-on: http://git-master/r/145641
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Patrick Shehane <pshehane@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agoChromeOs: enable config TEGRA_PREPOWER_WIFI
Wei Ni [Mon, 8 Oct 2012 08:42:03 +0000]
ChromeOs: enable config TEGRA_PREPOWER_WIFI

Use brcmfmac for both bcm4329 and bcm4330.
Enable TEGRA_PREPOWER_WIFI:
enable it, so that the sdhci driver can scan the wlan.
Disable BCMDHD
disable bcmdhd driver,which is for bcm4330.

Change-Id: I4c08638a7038349019ce515abe477f8faa2b5726
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: http://git-master/r/143991
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: e1853: add WXGA touch panel support
Dongfang Shi [Tue, 4 Sep 2012 23:49:20 +0000]
arm: tegra: e1853: add WXGA touch panel support

Support WXGA display and touch input for e1853.

bug 1036173

Change-Id: Ia66119c1f05dd61a46346a1b7e5dc5bbbeb43495
Signed-off-by: Dongfang Shi <dshi@nvidia.com>
Reviewed-on: http://git-master/r/129521
(cherry picked from commit a766194a31b6fe7e9834959a19c88d375c15d6de)
Reviewed-on: http://git-master/r/143774
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: e1853: Config LVDS for display 1.
Dongfang Shi [Wed, 29 Aug 2012 21:36:48 +0000]
arm: tegra: e1853: Config LVDS for display 1.

Program FPDLink Serializer for display 1.

bug 966833

Change-Id: I6eba4655eae4418480f16089abd3a406e2111721
Signed-off-by: Dongfang Shi <dshi@nvidia.com>
Reviewed-on: http://git-master/r/128283
(cherry picked from commit 2920d48bb5a8c00d1d731199ab4cfd01e5b30c98)
Reviewed-on: http://git-master/r/139034
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agoRevert "ARM: config: tegra3: Enable PLATFORM_ENABLE_IOMMU"
Mrutyunjay Sawant [Mon, 22 Oct 2012 12:52:50 +0000]
Revert "ARM: config: tegra3: Enable PLATFORM_ENABLE_IOMMU"

This reverts commit cde08d2ba6697f307e95493f24ba91d06242951c.

Change-Id: Iea2328e5e8168f7f01a82538626bd9e7bb209aca
Reviewed-on: http://git-master/r/146398
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agomedia: video: tegra: tegra_camera: remove reset
Jihoon Bang [Mon, 8 Oct 2012 18:30:01 +0000]
media: video: tegra: tegra_camera: remove reset

Resetting VI, ISP and CSI is taken care of by
tegra_powergate_partition and tegra_unpowergate_partition api.
tegra_camera doesn't have to reset them again.

Bug 1059495

Reviewed-on: http://git-master/r/142451
(cherry picked from commit 3c08187fe1d5c8f44de6e40c96de1ce6e71f34eb)

Change-Id: Ia98e1ccfc5ea9c5080b99c3c74b929c771232e31
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/145665
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

6 years agoRevert "arm: tegra: optimize L2 enable/disable paths for secureos"
Deepak Nibade [Wed, 17 Oct 2012 15:19:20 +0000]
Revert "arm: tegra: optimize L2 enable/disable paths for secureos"

With this revert, Dalmore enters LP0 state in Main
Otherwise NULL exception is encountered (variable l2x0_base)
Revert is required till we get proper secureos code and we
ensure that T114 does not enter l2x0 code

This reverts commit 7274dfdea8e1512b863438d4f34074a67b5b4a97.

Change-Id: Ib3ff4f1664fdc1693c2768eb3ecc0205a456c982
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/145288
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agopm: EDP: enable updates via sysfs
Sivaram Nair [Wed, 17 Oct 2012 12:37:03 +0000]
pm: EDP: enable updates via sysfs

This patch allows the user space to issue E-state and threshold change
requests. E-state updates are allowed only if the change is guaranteed
to be approved.

Change-Id: Id31f06ebb95f0b1fdfce205cb17038cb7a9eb30e
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/145256
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoarm: tegra: raydium: fix coverity issue
Sri Krishna chowdary [Tue, 16 Oct 2012 13:12:01 +0000]
arm: tegra: raydium: fix coverity issue

Check return values of gpio_request
and gpio_direction_input/output for touch.

Bug 1046331

Change-Id: I804d74657d1769c40727b3d8ae318f12f1d83098
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/144901
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agoarm: tegra: pluto: fix coverity issue
Sri Krishna chowdary [Tue, 16 Oct 2012 12:54:57 +0000]
arm: tegra: pluto: fix coverity issue

Check return value.

Bug 1046331

Change-Id: I313d5868e1a47110f30345d6b19b188fd025c09c
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/144893
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agoarm: tegra: enterprise: fix coverity issue
Sri Krishna chowdary [Tue, 16 Oct 2012 09:10:30 +0000]
arm: tegra: enterprise: fix coverity issue

Check return values for gpio_return and
gpio_direction_input/output for panel and
touch.

Bug 1046331

Change-Id: Ib7ab615a699e4d506d13540b3def98c46820bd11
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/144811
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agomfd: Added rtc resources & fixed interrupt init
Sumit Sharma [Tue, 16 Oct 2012 05:37:39 +0000]
mfd: Added rtc resources & fixed interrupt init

Added rtc resources for tps65910-rtc
Fixed interrupt initialiazation for tps65910

Bug 1055083

Change-Id: Idbb5098830075fe459020d5bdf264d9414b7cb8d
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/144779
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agogpio: tps65910: Added gpio to irq support
Sumit Sharma [Tue, 16 Oct 2012 03:35:14 +0000]
gpio: tps65910: Added gpio to irq support

Added gpio to irq mapping support for tps65910

Bug 1055083

Change-Id: I6cf48361a0d54c588698438bc1f57a19b2b94bd8
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/144736
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoarm: tegra: Add MAX1749 platform device
Sumit Sharma [Wed, 17 Oct 2012 03:49:43 +0000]
arm: tegra: Add MAX1749 platform device

Added MAX1749 vibrator platform device in cardhu board file

Bug 1154522

Change-Id: I6464c0cf9739bae91d9c4d8b86b86be5a57a5b57
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/144518
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agousb: gadget: tegra: fix coverity issue
Sri Krishna chowdary [Sun, 14 Oct 2012 07:00:36 +0000]
usb: gadget: tegra: fix coverity issue

name cant be NULL, it is static array.
Add check if name is empty string.

Bug 1046331

Change-Id: I2615ae0d24e44025b7528e10d0dafb124d355b4f
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/144374
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoasoc: tegra: wm8903: Fix the bug that wm8903 device is init twice
Shaoming Feng [Fri, 12 Oct 2012 22:35:17 +0000]
asoc: tegra: wm8903: Fix the bug that wm8903 device is init twice

Bug: 1056985

Change-Id: Id57093ccfbcb0673b660cd8cb0157d48078173c4
Signed-off-by: Shaoming Feng <shaomingf@nvidia.com>
Reviewed-on: http://git-master/r/144190
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: power: fix coverity issue
Sri Krishna chowdary [Sat, 6 Oct 2012 09:58:27 +0000]
arm: tegra: power: fix coverity issue

Fix Unsigned can't be less than zero issue.
tegra_dvfs_predict_millivolts returns int, so
voltage_mV can't be unsigned int.

Bug 1046331

Change-Id: I7973c3a434beef1cc54c4d61024b0b381c4fc66f
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/142152
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agoARM: config: tegra3: Enable PLATFORM_ENABLE_IOMMU
Hiroshi Doyu [Mon, 16 Jul 2012 07:48:13 +0000]
ARM: config: tegra3: Enable PLATFORM_ENABLE_IOMMU

Make all platform device IOMMU'able. Those device drivers are expected
to use DMA API correctly.

Bug 956490

Change-Id: I0ff010cbf4d8a5b88bd07c9c56644dbb07469667
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/139662
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra3: enable brcmfmac in defconfig
Wei Ni [Fri, 19 Oct 2012 09:50:20 +0000]
ARM: tegra3: enable brcmfmac in defconfig

Use brcmfmac for both bcm4329 and bcm4330.
Enable BRCMFMAC:
wlan driver, enable as module. Use in-band interrupt.
Enable TEGRA_PREPOWER_WIFI:
enable it, so that the sdhci driver can scan the wlan.
Disable BCMDHD
disable bcmdhd driver,which is for bcm4330.

Change-Id: I69f26b5842576ef96b47050961be8e517d79d320
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: http://git-master/r/139623
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Syed Rafiuddin <srafiuddin@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dc: Fix bootloader to kernel display transition
Animesh Kishore [Fri, 28 Sep 2012 04:38:10 +0000]
video: tegra: dc: Fix bootloader to kernel display transition

Bug 1053029

Change-Id: I7e0386f94f305842439884a0dbd549f09b61cde0
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/139571
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/145892
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: clock: warn only when error not expected
Sang-Hun Lee [Sat, 29 Sep 2012 23:12:42 +0000]
ARM: tegra11: clock: warn only when error not expected

 - tegra11_is_dyn_ramp would return false if dynamic ramp is disabled
 - As such, warn about dynamic ramp up / down failure only if dynamic
   ramp is enabled. Otherwise, a failure would be expected.

Bug 1057334

Signed-off-by: Sang-Hun Lee <sanlee@nvidia.com>
Reviewed-on: http://git-master/r/139955
(cherry picked from commit 3d6c0350ab7ea83fbe6285c61a80fdb491124e9f)

Change-Id: I59a8030eb0a8e13db5085734ced2fab17aa239b1
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/145859
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoregulator: palmas: Fix warning message
Mallikarjun Kasoju [Mon, 1 Oct 2012 12:03:23 +0000]
regulator: palmas: Fix warning message

Fix warnings of unused function/variable by removing them

Signed-off-by: Mallikarjun Kasoju <mkasoju@nvidia.com>
Reviewed-on: http://git-master/r/140612
(cherry picked from commit 523318f6f93d50096b3f075ead7d9959d30b5dd4)

Change-Id: I167fc5ba361ae1d3bfd1c1464edace4a59f6291d
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/145290
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoPM / cpuidle: Add driver reference counter
Rafael J. Wysocki [Sat, 16 Jun 2012 13:20:11 +0000]
PM / cpuidle: Add driver reference counter

Add a reference counter for the cpuidle driver, so that it can't
be unregistered when it is in use.

Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
(cherry picked from commit 6e797a078824b30afbfae6cc4b1c2b21c51761ef)

Change-Id: I41efc4cd5f99cbcfd1431ca2ac47e9aac1a11127
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/145221
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoPM / Domains: Add preliminary support for cpuidle, v2
Prashant Gaikwad [Sun, 14 Oct 2012 17:59:57 +0000]
PM / Domains: Add preliminary support for cpuidle, v2

On some systems there are CPU cores located in the same power
domains as I/O devices.  Then, power can only be removed from the
domain if all I/O devices in it are not in use and the CPU core
is idle.  Add preliminary support for that to the generic PM domains
framework.

First, the platform is expected to provide a cpuidle driver with one
extra state designated for use with the generic PM domains code.
This state should be initially disabled and its exit_latency value
should be set to whatever time is needed to bring up the CPU core
itself after restoring power to it, not including the domain's
power on latency.  Its .enter() callback should point to a procedure
that will remove power from the domain containing the CPU core at
the end of the CPU power transition.

The remaining characteristics of the extra cpuidle state, referred to
as the "domain" cpuidle state below, (e.g. power usage, target
residency) should be populated in accordance with the properties of
the hardware.

Next, the platform should execute genpd_attach_cpuidle() on the PM
domain containing the CPU core.  That will cause the generic PM
domains framework to treat that domain in a special way such that:

 * When all devices in the domain have been suspended and it is about
   to be turned off, the states of the devices will be saved, but
   power will not be removed from the domain.  Instead, the "domain"
   cpuidle state will be enabled so that power can be removed from
   the domain when the CPU core is idle and the state has been chosen
   as the target by the cpuidle governor.

 * When the first I/O device in the domain is resumed and
   __pm_genpd_poweron(() is called for the first time after
   power has been removed from the domain, the "domain" cpuidle
   state will be disabled to avoid subsequent surprise power removals
   via cpuidle.

The effective exit_latency value of the "domain" cpuidle state
depends on the time needed to bring up the CPU core itself after
restoring power to it as well as on the power on latency of the
domain containing the CPU core.  Thus the "domain" cpuidle state's
exit_latency has to be recomputed every time the domain's power on
latency is updated, which may happen every time power is restored
to the domain, if the measured power on latency is greater than
the latency stored in the corresponding generic_pm_domain structure.

[Prashant: Resolved conflicts]

Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Reviewed-by: Kevin Hilman <khilman@ti.com>
(cherry picked from commit cbc9ef0287ab764d3da0129efa673808df641fe3)

Change-Id: I1ec4dda167b2a687986bb5da491d43941b8f6ae8
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/145220
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoPM / Domains: Do not stop devices after restoring their states
Rafael J. Wysocki [Fri, 15 Jun 2012 22:02:34 +0000]
PM / Domains: Do not stop devices after restoring their states

While resuming a device belonging to a PM domain,
pm_genpd_runtime_resume() calls __pm_genpd_restore_device() to
restore its state, if necessary.  The latter starts the device,
using genpd_start_dev(), restores its state, using
genpd_restore_dev(), and then stops it, using genpd_stop_dev().
However, this last operation is not necessary, because the
device is supposed to be operational after pm_genpd_runtime_resume()
has returned and because of it pm_genpd_runtime_resume() has to
call genpd_start_dev() once again for the "restored" device, which
is inefficient.

To make things more efficient, remove the call to genpd_stop_dev()
from __pm_genpd_restore_device() and the direct call to
genpd_start_dev() from pm_genpd_runtime_resume().  [Of course,
genpd_start_dev() still has to be called by it for devices with the
power.irq_safe flag set, because __pm_genpd_restore_device() is not
executed for them.]

This change has been tested on the SH7372 Mackerel board.

Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
(cherry picked from commit 80de3d7f416f1accd03f2e519ead32d6fde4fcf4)

Change-Id: Id6999532ec29ba7ac3199301d3e54868ae181cce
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/145219
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agovideo: tegra: dc: enable cp with global alpha
Prashant Malani [Thu, 11 Oct 2012 01:50:57 +0000]
video: tegra: dc: enable cp with global alpha

When global alpha is enabled, color palette also
has to be enabled, for the change to take effect.

This also enabled global alpha for 11x

Bug 672060

Change-Id: Ic2759dd7f15fa58a134ac5dfbaa968096e8a750a
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/143417
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agobrcmfmac: Handling IRQ in ISR directly for non-OOB
Wei Ni [Wed, 26 Sep 2012 07:58:18 +0000]
brcmfmac: Handling IRQ in ISR directly for non-OOB

In case of inband interrupts, if we handle the interrupt in dpc thread,
two level of thread switching takes place to process wifi interrupts.
One in SDHCI driver and the other in Wifi driver. This may cause the system
instability.
Because the SDHCI calls sdio_irq_thread() to handle the irq, this thread locks
mmc host and calls wifi handler. It expects WiFi handler to be quick and
enables sdio interrupt from card at end. If wifi handler defers this work for
a different thread, sdio_irq_thread() will be stuck on next wifi interrupt
since mmc lock is not freed.

Handling the interrupt in ISR directly will prevent thread context switching
in wifi driver. It can fix the instability problems.

Change-Id: I1d0208f09d16d01a154d446f52f24356ebf7cddc
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: http://git-master/r/142591
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agomfd: MAX77665: carry over platform data for each cell
Charlie Huang [Wed, 12 Sep 2012 02:03:15 +0000]
mfd: MAX77665: carry over platform data for each cell

Add feature to transfer design specific platform data from board
file(s) to the cell device drivers.

Change-Id: I788082a1606bd07d72835d81e39ef7cd04e67c1c
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit e10e95036f2678aef17afe3b527fa4ec17866679)
Reviewed on http://git-master/r/139118
Reviewed-on: http://git-master/r/141852
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoARM: tegra: pluto: sensor: fix power down issue
Charlie Huang [Mon, 17 Sep 2012 01:16:22 +0000]
ARM: tegra: pluto: sensor: fix power down issue

Fixes the issue that the system will crash if the sensors are
powered on the 2nd time.

Change-Id: Iae8c24498a4e0f99e2892a8446204bb51ee8f401
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit 5baf326afb8005d0a40df948b85d96839fa7894a)
Reviewed on http://git-master/r/133134
Reviewed-on: http://git-master/r/141850
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agovideo: tegra: host: Add SW WAR for tegra11
Wei Sun [Wed, 10 Oct 2012 23:33:04 +0000]
video: tegra: host: Add SW WAR for tegra11

Add WAR for bug 982750
Add comments for bug 976976
Add comments for bug 990395
Add Comments for bug 951938

Change-Id: Id01ddafc82b84ac488f249ebe7f024bcb80cf61a
Signed-off-by: Wei Sun <wsun@nvidia.com>
Reviewed-on: http://git-master/r/143385
(cherry picked from commit ecda3f6db53cc2238a270f0f8f46d01d4f1a7df0)
Reviewed-on: http://git-master/r/145546
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 years agoRevert "video: tegra: host: temp increase the syncpt check period"
Terje Bergstrom [Thu, 18 Oct 2012 08:12:20 +0000]
Revert "video: tegra: host: temp increase the syncpt check period"

This reverts commit 7a4937502cbc8dd00531a1a73b7c88fb71a86577.

Change-Id: If707c986b9e4b0d9e9dbc880496136dcf974abb0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/145545
Reviewed-by: Automatic_Commit_Validation_User

6 years agoCHROMEOS: config: disable DEBUG_LL
Rhyland Klein [Wed, 17 Oct 2012 16:14:10 +0000]
CHROMEOS: config: disable DEBUG_LL

Now that the kernel won't crash if DEBUG_LL is disabled and the
bootloader passes the 'D' in the uart scratch register to signal the
debug uart, disable the extra unnecessary kernel logging.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Change-Id: Ic296993011aa0c1f8fc9dd155a946922633928e9
Reviewed-on: http://git-master/r/145297
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Allen Martin <amartin@nvidia.com>

6 years agomisc: nct: section mismatch fix
Bitan Biswas [Wed, 12 Sep 2012 09:45:04 +0000]
misc: nct: section mismatch fix

Fix section mismatch error for nct thermal sensor driver

Bug 1038578

Change-Id: I39c86896ab50a11b30c3b975b9d20190417bebb3
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/132797
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/145291
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoarm: tegra: dalmore/pluto: Fix section mismatch warning
Animesh Kishore [Thu, 27 Sep 2012 05:28:52 +0000]
arm: tegra: dalmore/pluto: Fix section mismatch warning

Bug 1055400
Bug 1038578

Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/139220
(cherry picked from commit e94c0f27d4905934d354fb949573592c7f710231)

Change-Id: I09204704b6d4f1abbbead396f67e0b288c94a94a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/145289
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoasoc: tegra: Have single platform data for VCMs
Nitin Pai [Wed, 29 Aug 2012 13:49:53 +0000]
asoc: tegra: Have single platform data for VCMs

Rename the file tegra_p1852_pdata.h to tegra_vcm_pdata.h for using
generically across all the VCM based platforms.
Added config structure to pass the DAP/DAS configuration for P852
Added support to configure the DAP/DAS on Tegra2.

Bug 1040171

Reviewed-on: http://git-master/r/128224
(cherry picked from commit fca5e1c5407f17d6860003ca4db4e27b459a0fbe)

Change-Id: I9dba53f6e182550b8267666a37533317d07433db

Signed-off-by: Nitin Pai <npai@nvidia.com>
Change-Id: I7ef9052fb32c680d1d3be623e61669000deccd2e
Reviewed-on: http://git-master/r/145263
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bob Johnston <bjohnston@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoarm: tegra: p1852, e1853: enable TASK_SIZE_3G_LESS_24M
Sumeet Gupta [Wed, 17 Oct 2012 12:10:31 +0000]
arm: tegra: p1852, e1853: enable TASK_SIZE_3G_LESS_24M

Enabling this config for P1852 and E1853 gnu Linux configs.

Bug 1047425
Bug 1160254

Reviewed on: http://git-master/r/134408
Change-Id: Ie2e2bfb3bd21f8d048eff070f5887fc66a96955f
Signed-off-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-on: http://git-master/r/145246
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoPM / Domains: Use subsystem runtime suspend/resume callbacks by default
Rafael J. Wysocki [Fri, 15 Jun 2012 22:02:22 +0000]
PM / Domains: Use subsystem runtime suspend/resume callbacks by default

Currently, the default "save state" and "restore state" routines
for generic PM domains, pm_genpd_default_save_state() and
pm_genpd_default_restore_state(), respectively, only use runtime PM
callbacks provided by device drivers, but in general those callbacks
need not provide the entire necessary functionality.  Namely, in
general it may be necessary to execute subsystem (i.e. device type,
device class or bus type) callbacks that will carry out all of the
necessary operations.

For this reason, modify pm_genpd_default_save_state() and
pm_genpd_default_restore_state() to execute subsystem callbacks,
if they are provided, and fall back to driver callbacks otherwise.

Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
(cherry picked from commit 0b589741b8b83a33e25fb32bb714ea1b972af5aa)

Change-Id: I573c7f62ea6ebd24a4dc643eb69da73d4b543017
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/145218
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agonor: Assigning static mapping for 64MB NOR Flash.
Sumeet Gupta [Wed, 17 Oct 2012 08:08:18 +0000]
nor: Assigning static mapping for 64MB NOR Flash.

VMALLOC_END has been pushed up by 16MB to accomodate NOR.

Non-static mapping hogs a lot of vmalloc space.

Bug 1036361
Bug 1160254

Rviewed-on: http://git-master/r/128178
Change-Id: I9913d5983721a0f35116a761131f7338ba26a0c8
Signed-off-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-on: http://git-master/r/145183
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoarch: arm: tegra: regulator calls need the device name
Petlozu Pravareshwar [Wed, 17 Oct 2012 07:34:20 +0000]
arch: arm: tegra: regulator calls need the device name

Device name is passed to the regulator_get API.

Bug 1158664

Change-Id: Iac26dba79964fc49a95eb5f3cecd4ae10019f461
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: http://git-master/r/145166
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Reviewed-by: Rakesh Bodla <rbodla@nvidia.com>