Liang Cheng [Fri, 7 Oct 2011 17:55:39 +0000 (12:55 -0500)]
arm: tegra: issue a warning message per run
A large trunk of warning message and stack trace storms kmesg
when a very small sample quantum is supplied. This eventually
causes the system unresponsive.
This change fixes this issue by warning once per run.
Dan Willemsen [Wed, 5 Oct 2011 22:26:57 +0000 (15:26 -0700)]
ARM: tegra: fuse: Fix tegra_chip_uid
This now matches what the bootloader thinks the chip ID is (and the lot
code is no longer all zeros).
Change-Id: I46dc677b983dd28f7f77e49919860fef66da8f51 Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/56316 Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rfb7b961acd57447df95600d4f1678d84242ed1b9
Alex Frid [Thu, 29 Sep 2011 05:42:06 +0000 (22:42 -0700)]
ARM: tegra: power: Update Tegra3 LP2 time prediction
Use local timer count to predict time to be spent by secondary CPU
in LP2 state instead of scheduler timing. This is more accurate, as
local timer wakes CPU after counts down to zero.
Change-Id: I28fe6c3153e1c527abf4cf66b556d64516582a35
Reviewed-on: http://git-master/r/55629 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Rebase-Id: R577246dfe6bce06bf7a1f87d0ab488322d98b631
since the dvfs init was being called before the kernel commandline was
parsed, it resulted in an incorrect core_edp voltage being set further
leading to an incorrect emc clock.
move parsing of core_edp voltage value to early_param handler.
Nitin Kumbhar [Tue, 4 Oct 2011 06:31:55 +0000 (12:01 +0530)]
arm: tegra: clock: fix clk debugfs init by using duplicate clocks
Clocks added for nvavp with same name result in a failure in
debugfs_mknod() with EEXIST error when a node for a clock is being
created in /d/clock/ directory. Resolve this by adding duplicate
clocks for nvavp.
Alex Frid [Sat, 1 Oct 2011 23:00:51 +0000 (16:00 -0700)]
ARM: tegra: clock: Re-factor shared bus locking
Current code:
- on tegra2 unnecessary covers with bus lock shared user state update
- on tegra3 does not cover shared bus rate update at all
Modified to cover with bus lock shared bus rate update only on both
tegra2 and tegra3.
Change-Id: Iaa2597136a521adf4285c61eb579c917c2c7965c
Reviewed-on: http://git-master/r/55640 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com> Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R1b28f32ae37d47c56855023b18c943bf8fd93c74
- Do not save/restore local timer configuration across secondary CPU
LP2 state. It is always preserved, since local timer is neither power
gated nor reset when secondary CPU is in LP2.
- Do not configure external timer for secondary CPU wake up, since we
can use local timer instead. Moreover, in current code external timer
interrupt is registered too late on secondary CPU after it is brought
on-line, so the timer may not always be able to wake CPU up from LP2.
Change-Id: I864e9910fe7112bbce3ea4dbaef12be4b42fb5dc
Reviewed-on: http://git-master/r/55070 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R3407f05d200d81e29994daf278170d3619714bef
Alex Frid [Wed, 21 Sep 2011 06:37:36 +0000 (23:37 -0700)]
ARM: tegra: timer: Update twd suspend/resume
- Preserve twd periodic load register across suspend and LP2 on main
CPU. Keep timer disabled on resume, since it will be re-configured
later when timekeeping switches from global system timer.
- Generate "load equal zero" warning in twd suspend/resume code only
when timer is in periodic mode.
Change-Id: If7df8be08c0ef4e355f315e3f0b7e3cf1b358f0f
Reviewed-on: http://git-master/r/55068 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R75f3950a915e0953a098620dea9ea32a7d5e9482
Alex Frid [Wed, 21 Sep 2011 01:45:53 +0000 (18:45 -0700)]
ARM: tegra: power: Flush cache just before cpu shutdown
Re-arranged cpu die procedure to flush L1 cache just before shutdown.
This is necessary as code executed after L1 flush included spin-lock
protected sections, and the unlock operation was not properly detected
by SCU. As a result CPUs that stayed on-line hanged trying to acquire
the same spin-lock.
Bug 864256
Change-Id: I415160d60686094059e62d91cdcf4b264a4fb69f
Reviewed-on: http://git-master/r/53637 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Gaurav Sarode <gsarode@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R0663eac9b5c3c84d8b7380873bde6af6b2a74a9f
Jin Qian [Wed, 14 Sep 2011 03:33:37 +0000 (20:33 -0700)]
ARM: tegra: clock: add low speed uart clocks
K39 disable uart clocks in LP0 suspend with irq disabled so they cannot
sleep. Add new uart clocks with low speed parents so that clk_disable
doesn't sleep.
Change-Id: I92109acff588591904f15dceac49acb89962ab9b
http://nvbugs/876144
Reviewed-on: http://git-master/r/52215 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R7e184ad00f065747656272b4a9cac13a2a79d284
Jin Qian [Mon, 12 Sep 2011 19:33:15 +0000 (12:33 -0700)]
ARM: tegra: power: fix build error on tegra_pm_enter routines
Change-Id: I2f22bf2b416eb7617c2d845b6f7a9f293eb32c1c
Reviewed-on: http://git-master/r/51852 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R986d6156129b2d62176e68aa01ae3c11e4ef6861
arm: tegra: iovmm: Remove unnecessary and harmful lock in IOVMM
Bug 862658
Reverting to K36 code.
Google invented the lock (originally as spinlock). The lock surrounds
a read-only list and is not only unnecessary but also affects
atomicity of lower layers. Should real protection be necessary in
a lower layer, the layer would be responsible for the proetection.
The SMMU layer does not need protection.
Change-Id: I45641cfde3eebc536f57d14db447b03f4ea814b5
Reviewed-on: http://git-master/r/50349 Tested-by: Hiro Sugawara <hsugawara@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R9c0fdcdbc673c0ba353a8d0731dcf4e4bf3a81fa
Jin Qian [Fri, 2 Sep 2011 23:24:01 +0000 (16:24 -0700)]
ARM: tegra: power: do not check time after kernel time suspend
cluster switch for LP0 is called after linux timekeeping suspend,
which turns off timer.
Bug 862504
Change-Id: I5d154248a23fc07a18fdde42eb5308b8c84806fe
Reviewed-on: http://git-master/r/50611 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R53bc77ecf9e8a14f40d0ff6e76c3589492af297a
Jin Qian [Fri, 2 Sep 2011 23:22:18 +0000 (16:22 -0700)]
ARM: tegra: power: save cluster switch status before entering LP0
warm boot reads SCRATCH4 to choose wake-up from LP or G
Bug 862504
Change-Id: I5ee4697c6268d379a6708e6a87e3f7df12f2994a
Reviewed-on: http://git-master/r/50610 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R7e61acb99f023449c2416054c44b75837c3aff94
Jin Qian [Thu, 1 Sep 2011 02:47:26 +0000 (19:47 -0700)]
ARM: tegra: power: move cluster switch to syscore for LP0
move printk as well since they rely on uart resume in syscore
Bug 862504
Change-Id: Iad62c87dbb01d07bf731babb62cb480d62b9402e
Reviewed-on: http://git-master/r/50240 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R8c5b23f5045260160a4906da425cc297fae5b59b
Jin Qian [Thu, 1 Sep 2011 02:39:57 +0000 (19:39 -0700)]
ARM: tegra: power: fix lp0 suspend
enable pllm and skip io_dpd for lp0
Bug 862504
Change-Id: Ie68778564283f0b947aa682b8ca2f480f795f2f7
Reviewed-on: http://git-master/r/50239 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R0c0da8c489620856cf7bb1883af115b0d33842e0
Jin Qian [Wed, 31 Aug 2011 00:23:55 +0000 (17:23 -0700)]
ARM: tegra: power: move cluster switch prolog/epilog from suspend
They're called only when doing cluster switch so move them to
cluster control function.
Change-Id: Ic258dd06ab454aa5eb96673665607b373284a43c
Reviewed-on: http://git-master/r/49952 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R1b68449702767a8555fff82b5fb8c88e1acbe363
Change-Id: Ife9154a9fe0bad9be7039fac41c86df2f0b8ebef
Reviewed-on: http://git-master/r/49053 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R976249827c7a9fdd255e6f0968a8e26d1234528f
Jin Qian [Wed, 31 Aug 2011 18:07:19 +0000 (11:07 -0700)]
ARM: tegra: clock: convert tegra3 suspend/resume to syscore_ops
Bug 862504
Change-Id: I5a1f3a7689f09e73b30e35b5f5ebb5773d0c0440
Reviewed-on: http://git-master/r/50090 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R87bf48392cc199b37d1f5ca272203a53b1d7b0c5
Jon Mayo [Thu, 28 Jul 2011 00:01:57 +0000 (17:01 -0700)]
ARM: defconfig: tegra3: use REPORT_PRESENT_CPUS
enable reporting of present cpus in /proc/cpuinfo and /proc/stat
Bug 849167
Original-Change-Id: I8651079ff63c7399942d937cb0af126aa67a2fd7
Reviewed-on: http://git-master/r/43632 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: R24122a5d7e8b2517e99518a698f89ac3946a76ec
Jin Qian [Wed, 24 Aug 2011 01:15:32 +0000 (18:15 -0700)]
ARM: tegra: power: restore reset handler after lp0
Bug 862504
Change-Id: I910f4f229a2040d13d79e2a4f64fd2558509d9e7
Reviewed-on: http://git-master/r/50241 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R3c4d055f1c2ebad76ad2a9305d5e02f5a4411400
Scott Williams [Wed, 7 Sep 2011 00:19:18 +0000 (17:19 -0700)]
ARM: tegra: Clean up the chip revision decoder
Replace the chip revision decoder with something that is more
extensible and maintainable.
Change-Id: I1c31cbded4ca14e7949be551995b4aaa75f5c1fb Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50931 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com>
Rebase-Id: Raf389b9daa8a8312c38f281dcf05ea19b2018136
In T30, different pad ctrl group registers have
different pull up and pull down drive strength field
offsets and maximum values. Modified drive_strength
structure to be able to pass the offsets and masks of
each group to ensure that drive strengths are properly
configured.
Alex Frid [Wed, 24 Aug 2011 05:52:42 +0000 (22:52 -0700)]
ARM: tegra: power: Tune Tegra3 hotplug algorithm
- Account for EDP affect on total available MIPS when bringing on-line
(removing off-line) new cpu core. Add multi-core overhead (in percent)
as a parameter - set by default to 10%.
- Add balance level parameter: level value (in percent) defines minimum
speed ratio used by hotplug algorithm to determine if current CPU cores
are balanced, so that another core may be brought on-line. By default
set to 75%
Scott Williams [Wed, 31 Aug 2011 15:37:27 +0000 (08:37 -0700)]
ARM: tegra: pinmux: Prevent access to uninitialized pin groups
There is no guarantee that every element in the pin group array
will be used (i.e., initialized) for a particular SOC. Prevent
access to pin group array elements that are not initialized.
Original-Change-Id: I90ea3616f8508b12ffe4a7daf9ff4b2bac057075 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50059 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Rebase-Id: Rd6c206b805d180fb3c52be52edfeebed701ca73d
Terje Bergstrom [Thu, 25 Aug 2011 11:30:52 +0000 (14:30 +0300)]
nvhost: power: Separate module shared clocks
Register clocks that are shared amongst modules (emc, epp) as separate
clocks. This way setting EMC clock for 2D does not interfere with EMC
clock needs for 3D or MPE.
Bug 868554
Original-Change-Id: I5c7dddc8f1d67969865918e577bd24b274d9e897 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/49603 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: R81c4b506c9bd451ab38f4ac28f9f38e0d3232e21
Scott Williams [Thu, 1 Sep 2011 23:20:47 +0000 (16:20 -0700)]
ARM: tegra: Use SATA and PCIE SOC architecture conditionals
Use the SOC architecture conditionals for determining the
presense of PCIE and SATA.
Change-Id: I312d0d1b45fc08e4938260b978d083b113ed9d66 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50379 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Ra949d477a8e96ccc7760c4974ae93909ea054bbb
Scott Williams [Thu, 1 Sep 2011 22:07:44 +0000 (15:07 -0700)]
ARM: tegra: Clean up makefile conditionals
Change-Id: I7789a192aad504957770b7632d4f5f9cd01b8c5d Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50358 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R94f5bab7f502627ce9bda7e07ea5afe4518bb1e2
Scott Williams [Thu, 1 Sep 2011 22:03:48 +0000 (15:03 -0700)]
ARM: tegra: Clean up power gating code
Clean up conditionals.
Use the generic name of CELP for the LP partition.
Change-Id: Iaad7fa36b76ee6d694eca56f11dba8fad009a447 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50357 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R06d260a102540afae03bb0684fde4efe4c144a1a
Scott Williams [Thu, 1 Sep 2011 21:59:01 +0000 (14:59 -0700)]
ARM: tegra: Remove unnecessary SOC conditionals
Change-Id: I4ad09ea97db373dbed0764214fc5d98be2e29f7a Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50356 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R5c2b9b638a4e150eb1fa6e1d4f587bb71622efea
Scott Williams [Thu, 1 Sep 2011 21:55:13 +0000 (14:55 -0700)]
ARM: tegra: Use ARCH_TEGRA_DUAL_3D for GPU regsiter sets
Determine the number of GPU register sets based upon the setting
of ARCH_TEGRA_DUAL_3D.
Change-Id: I66e860fba2a979921ac4e4bd39bed99fb305996e Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50355 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R443612bad1ec0f745a51b8f301a322b5bb8cef96
Scott Williams [Thu, 1 Sep 2011 21:47:32 +0000 (14:47 -0700)]
ARM: tegra: Only Tegra3 has TSENSOR
Change-Id: I232d3ae5e037d491d1d8d185e75c1c9a7035cd4c Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50354 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R899f3aaf97ca7f21785749a8675ba1bc461f81f9
Scott Williams [Thu, 1 Sep 2011 02:24:56 +0000 (19:24 -0700)]
ARM: tegra: Use forward looking architecture conditionals
Change-Id: I31f2717327a627ad83e4cc2f083b71fd68fb1465 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50221 Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rcaef7248cf06aa01c40b8e5eae13e3a20ed097d3
Scott Williams [Thu, 1 Sep 2011 15:56:31 +0000 (08:56 -0700)]
ARM: tegra: Add SOC architectural capabilities
Add architectural capabilities the at are selected by the top-level
architecture type rather than deriving this knowledge directly from
the top-level type in the code.
Change-Id: I1c1e5d986a65301cf2e474d866f01e4f8c2a5505 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/50298 Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R118b523b4c6cac8f4f530f01a1d14ed961d5a085
Change-Id: I61b97e033413f7d61c06da83d9b6f971df9019cc
Reviewed-on: http://git-master/r/49685 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com> Tested-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Raf5717982cd8768f948f446bfaa48265bfd723f6
Scott Williams [Thu, 25 Aug 2011 21:28:10 +0000 (14:28 -0700)]
ARM: tegra: Fix warnings
Change-Id: Ic2cecccf0f4f6e6ca612af2ee07acdbca2ce07a5 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49281 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R59e04e0a46099403284a036de7f35d21c6188d81
Yudong Tan [Thu, 18 Aug 2011 22:29:08 +0000 (15:29 -0700)]
ARM: tegra: power: Call cluster_switch_prolog/epilog for LP1
cluster_switch_prolog is needed to set up car/flow controller registers
for LP1 entry. epilog is needed to clean up some flags in flow controller
after LP1 exit.
Bug 862502
Change-Id: Ib9eeac6fc541cfa644d782071dbd4187255404d8
Reviewed-on: http://git-master/r/47585 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R2c72673ba1b7f04ffa1b760ff54aaf73cf23f09e
Change-Id: I728d5163bff3fb2bd4a2ea7946d2e57cb0854589 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49346 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R470db120396c95bdcafc48ba357652a43d63da82
Scott Williams [Fri, 26 Aug 2011 01:39:56 +0000 (18:39 -0700)]
ARM: tegra: power: Fix build error on non-SMP systems
Can't use NR_CPUS on non-SMP systems. Just use the maximum.
Change-Id: Ie0d6289c3b8bdaada6335e4670c9f6b5ab2bcc93 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/49344 Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R58abf556bf542b8cf0ee6dd0f091806235f49623
arm: tegra: pinmux: fix the Tegra2 pinmux table for RSVD values
The pin-func set by board-xxx-pinmux.c should be one of the 4 possible
values of the pin-func in master pinmux table. Also the safe pin-func
setting should follow the same rule.
If this is not followed then, warnings will be seen whenever a driver
tries to set a pin-func that is not in the master pinmux table. This is
specically seen for the mux values RSVD_X.
The hardware is always programmed with the bit value of setting
(00, 01, 10, 11) which is the position (0, 1, 2, 3) in master pin-mux table.
For bug 865503
Change-Id: I3933ca0002e099376798cc131690922fefa16868 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/48197 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R6d5a11f9f3ab523a2557a512ab85c3ef5f90815a
APIs lock_name(), od_name(), ioreset_name() are called from code for
Tegra3 and above. However, their implementation was not taking care
of this. This was causing 3 warnings during Tegra2 builds.
Change-Id: I4ac4d394c68fd1f8bab5938b2af76c8b92d04a64 Signed-off-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-on: http://git-master/r/48195 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com> Tested-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R4e7e7a4ec3cd7b31a2297bdeedccedc8cbcb5a01
Scott Williams [Tue, 23 Aug 2011 22:52:45 +0000 (15:52 -0700)]
ARM: tegra: Fix build errors when PM_SLEEP is not selected
Change-Id: I2037be4b1309ac1fe9af0ec3e644e0a1a4924857 Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48796 Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R0840ee98b17984f73f9a5396ab6f86d4d92b744e
Do not switch to clock event broadcast mode until the final CPU
is going into LP2. Switching into broadcast mode on the secondary
CPUs can cause double ticking and/or kernel panics on the primary.
Change-Id: I92076f053bdae7de57e5d7453170b43558b094cc Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/48743 Reviewed-by: Jin Qian <jqian@nvidia.com> Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Daniel Willemsen <dwillemsen@nvidia.com>
Rebase-Id: R18bd87d171133d210a5edf732960d1c011e1e9a5
ARMv6+ architecture does not allow ioremap on system memory.
lp0 is relocated using ioremap on DRAM. If lp0 vector start address
is in system memory then use memblock_reserve and do not relocate.
Else if it is overlapping with carveout/fb then first remove the
carveout/fb using memblock_remove and then use ioremap.
LP0 vector is allocated by BL and address is shared to kernel.
For platform with memory less than 1GB it was allocated in
the overlapping region of carveout memory. Because of it
during AVP operation it gets corrupted, which prevents resume.
Relocate AVP vector to some other location where overlapping will
not occur.
This function should be safe to call after all other CPUs
have been stopped. It is better to call it after reboot callback
functions have been called, so that any extra prints can be
flushed.
Conflicts:
arch/arm/mach-tegra/common.c
Original-Change-Id: I2e2e07b78f2773a5e26cd893d955bdf9c678c3f0
Reviewed-on: http://git-master/r/47339 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rc7dff9d9fb92f882334d2d771c674ad9cd1c6c72
Kaz Fukuoka [Thu, 26 May 2011 01:21:32 +0000 (18:21 -0700)]
media: tegra: avp: Clear interrupt registers when AVP starts
There was no code to clear interrupt registers for AVP. First run
of AVP was OK because those registers start from reset value.
But because those registers were not cleared, when the second
time AVP was started, some interrupts were enabled too early.
That caused interrupts coming before handlers were ready.
This change also removes the workaroud for the bug.