6 years agoARM: tegra: Fix build break for T30
Bo Yan [Tue, 2 Oct 2012 01:26:20 +0000]
ARM: tegra: Fix build break for T30

- It's obvious that the XUSB is only supported in T11x

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/140800

Change-Id: I685e4b8eeb47784291ee5e38d3554444d99f2f8f
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146489
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra11x: Fix CRAIL power up sequence
Bo Yan [Thu, 18 Oct 2012 00:24:20 +0000]
ARM: tegra11x: Fix CRAIL power up sequence

When switching cluster from slow to fast, it's desirable to power
up CRAIL first to introduce some parallism with software context
save.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/145430
(cherry picked from commit f81caa0a9ef390d326b344ca5c1dd2f6550df1d0)

Change-Id: I4cef9ff32bbf0118fad34aa202e20a2be0c7925a
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146488
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoasoc: tegra: Fix the dependency in Kconfig
Bo Yan [Wed, 17 Oct 2012 17:30:06 +0000]
asoc: tegra: Fix the dependency in Kconfig

Since CS42L73, RT5639, and RT5640 also depend on
SND_SOC_TEGRA30_SPDIF, this obviously can't be limited to
tegra30.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/145309
(cherry picked from commit b86c825cd00813c71baaaf7534089e39cb600fa5)

Change-Id: I24009899ad8a2c0a2639e3cc4c03e44a154e35d0
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146487
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra11x: fast cluster power down control
Bo Yan [Mon, 15 Oct 2012 05:37:02 +0000]
ARM: tegra11x: fast cluster power down control

Currently, we are using "power_gating" to control what power down
mode to choose for fast cluster. With this change, a new sysfs
node "fast_cluster_power_down_mode" is used for that purpose. This
node is an unsigned integer with only 2 LSB used. '00' means power
gating CPU only, '01' means power gating non-CPU partition as well,
'10' means rail-gating the entire fast cluster, '11' means emulation
mode, which shall not be selected in production environment.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/144769
(cherry picked from commit 08cf1b25cbcfbb46822f76d08313ed1a9be6fc28)

Change-Id: I1a8a79cbd9f1f3ddce0b0f3d42fb3747284ac58e
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146486
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra11x: Control power gating of each CPU
Bo Yan [Fri, 12 Oct 2012 18:58:30 +0000]
ARM: tegra11x: Control power gating of each CPU

Currently, LP2 can be enabled or disabled for either CPU0 or CPUn,
this is good for T30, but for T114, CPU0 is no different from any
other CPUs in terms of hardware power management support. Add
finer control so that power gating can be enabled or disabled for
any individual CPU in fast cluster.

The control is done through sysfs interface. The node
"cpu_power_gating_in_idle" is a CPU mask. the 5 LSB represent 5
CPUs. bit 0 is for CPU0, bit 1 is for CPU1, bit 2 is for CPU2,
bit 3 is for CPU3. By default the mask is set for all CPUs. Writing
a '1' to bit n enables power gating of CPUn. any other bits are not
used. The special case is bit 4, which controls the single CPU in
slow cluster.

For example, to enable power gating for all CPUs in fast cluster,
just write a "15" to that sysfs node. To disable power gating for
all CPUs, write a "0". To enable LP2 for slow CPU, write 0x10 to
that node.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/144136
(cherry picked from commit bbfd7d15eba22492d56831e4db1181128ffa56ae)

Change-Id: I12299718d286f51d8340c0258cbd1265f3212655
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146485
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra11x: CPU start up fix
Bo Yan [Tue, 9 Oct 2012 02:52:49 +0000]
ARM: tegra11x: CPU start up fix

The first time when a CPU powers up in kernel, it has to be
done by directly toggling PMC register.

Subsequent CPU power up sequence is controlled by flow controller.

This is done after LP0 exit as well.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/143296

Change-Id: If32712706d827e4d0337d75163449cfa0a3a50f8
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146484
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra11x: Create cpuidle driver for t11x
Bo Yan [Wed, 3 Oct 2012 20:32:53 +0000]
ARM: tegra11x: Create cpuidle driver for t11x

The initial version is copied from cpuidle-t3.c, then conditional
compilation macros are cleaned up, unused functions are removed. t11x
code then is removed from cpuidle-t3.c

"slow_cluster_power_gating_noncpu" is added to sysfs to let user
control how to power gate slow cluster. It's disabled by default,
which means we power gate CPU partition only when running in slow
cluster.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/141422
(cherry picked from commit 2f7860a3cd004d803df2550499a26c6675617b01)

Change-Id: I7a00f7a77fa8a6612bdc9dd4f9c2a2656b2d84c5
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146483
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra: Fix typo
Bo Yan [Tue, 2 Oct 2012 16:58:43 +0000]
ARM: tegra: Fix typo

cpuidle, not cpudile

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/140950
(cherry picked from commit fcc9bc3771f79f602025cfeebd1bed785590394d)

Change-Id: I0a674c7e5facd06b8fd599c58d90e094a21fde1e
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146482
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra11x: Support per-core CPU power gating
Bo Yan [Mon, 1 Oct 2012 22:36:30 +0000]
ARM: tegra11x: Support per-core CPU power gating

Currently, CPU0 power gating can only be started once all 3 slave
CPUs have been taken offline. This change enables CPU0 power gating
while other CPUs are still online.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/140764
(cherry picked from commit 0b4c70f128a6b4b335dd2f91464a3f88e4ffe331)

Change-Id: I40357887334554148a97e3874cfdf26d20adb0a2
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146481
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra: More accurate name for LP2 functions
Bo Yan [Mon, 1 Oct 2012 18:59:50 +0000]
ARM: tegra: More accurate name for LP2 functions

Starting from tegra3, the LP2 is no longer an appropriate name
for a particular CPU power state. LP2 on CPU0 means rail-gating,
LP2 on slave CPUs means power-gating. Starting from tegra11x,
even CPU0 can do power gating.

This changes function names to reflect the fact that the rail-gating
is a cluster-wide power state, and power gating is a per-CPU core
power state.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/140704
(cherry picked from commit 885c9b26a07b2b8f5b05be3cf3e9dcda60a92157)

Change-Id: Icd1bd75494c17d18aecaea2a5177ca0a12df0ca1
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146480
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra11x: Fix TimerValue data type
Bo Yan [Fri, 28 Sep 2012 01:20:06 +0000]
ARM: tegra11x: Fix TimerValue data type

The TimerValue register in generic timer does not stop after
counting to 0, it will keep counting down. The value is the
time elapsed after event trigger.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/139535
(cherry picked from commit f84b23ed0c37297bf8142b69702cf8f2a1c24058)

Change-Id: I009585819b801b2eb157f9a70a3e9bf75a41ff77
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146479
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra: Optimize osc detection
Bo Yan [Fri, 28 Sep 2012 03:42:32 +0000]
ARM: tegra: Optimize osc detection

This needs to be done only once after boot. Actually, doing it
repeatedly on multiple CPUs without synchronization is bad.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/139557
(cherry picked from commit fee6c6af34763eb93641a52e7ba571819f79beb6)

Change-Id: Ie73a16dfc8496d5a3ff8091c5ef5768719475def
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146478
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: architected timer: Add C3STOP feature
Bo Yan [Sat, 22 Sep 2012 17:03:57 +0000]
ARM: architected timer: Add C3STOP feature

With architected timer, the clock source is always available,
which comes from time stamp counter. However, in time of rail
gating, timer itself will be lost, so we have to switch to
broadcast timer as a backup, therefore, CLOCK_EVT_FEAT_C3STOP
has to be added, otherwise clockevents framework will not allow
the switch to broadcast timer.

Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/134602
(cherry picked from commit 5ba404fa596e09b195a482547a8d052492187a01)

Change-Id: I319a7a117d6ad5d6397667a29bc9f071d8f8ab6d
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146477
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit

6 years agoARM: tegra: Remove host1x devs from pg blacklist
Terje Bergstrom [Thu, 18 Oct 2012 11:10:29 +0000]
ARM: tegra: Remove host1x devs from pg blacklist

Remove host1x engines from power gating blacklist.

Change-Id: If9beb7502aead6ca4582223c8b07d6382cbe37ba
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/146192
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoARM: tegra: Use 3D power gating sequence for MSENC
Terje Bergstrom [Fri, 28 Sep 2012 07:51:57 +0000]
ARM: tegra: Use 3D power gating sequence for MSENC

Use the 3D power gating sequence for MSENC. Hardware documentation
indicates that they have the same sequence.

Bug 1056631

Change-Id: If9de3dbddc3e0cb8e0fe99facec2a4deaf7e6b9b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/139599
(cherry picked from commit 44b3740357473312f5176b00d82688f5e0ebd5d9)
Reviewed-on: http://git-master/r/146191
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoarm: tegra: remove IMX091 support from Cardhu
Wei Chen [Fri, 19 Oct 2012 19:39:29 +0000]
arm: tegra: remove IMX091 support from Cardhu

IMX091 is not supported on Cardhu platform. Remove
it from the sensor board file.

Bug 1162221

Change-Id: I76de62984b34109ac9ae318cba8689d6162bcc60
Signed-off-by: Wei Chen <wechen@nvidia.com>
Reviewed-on: http://git-master/r/146035
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Gary Zhang <garyz@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agomedia: video: tegra: max77665-flash: trigger mode update
Charlie Huang [Fri, 5 Oct 2012 00:21:47 +0000]
media: video: tegra: max77665-flash: trigger mode update

plus some minor fixes.

Change-Id: I3aaa757068de1047bdd03fcd75b8d53765aea005
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit b1b6b6c3031f45bf55d04e1b1cf6cbb50a150289)
Reviewed on: http://git-master/r/#change,141774
Reviewed-on: http://git-master/r/146032
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agomedia: video: tegra: max77665 flash updates
Charlie Huang [Sun, 30 Sep 2012 01:46:06 +0000]
media: video: tegra: max77665 flash updates

fix trigger mode settings, and some code optimizations.

bug 1035551

Change-Id: I92cc0e0e7e9bac9b8cf26b5bba5d10c8dfad49ee
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit 0bafa31093f1ca948c43601a9bffd7dcbe00b136)
Reviewed on: http://git-master/r/#change,139959
Reviewed-on: http://git-master/r/146031
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoPM / Runtime: let rpm_resume() succeed if RPM_ACTIVE, even when disabled, v2
Kevin Hilman [Fri, 21 Sep 2012 22:47:34 +0000]
PM / Runtime: let rpm_resume() succeed if RPM_ACTIVE, even when disabled, v2

There are several drivers where the return value of
pm_runtime_get_sync() is used to decide whether or not it is safe to
access hardware and that don't provide .suspend() callbacks for system
suspend (but may use late/noirq callbacks.)  If such a driver happens
to call pm_runtime_get_sync() during system suspend, after the core
has disabled runtime PM, it will get the error code and will decide
that the hardware should not be accessed, although this may be a wrong
conclusion, depending on the state of the device when runtime PM was
disabled.

Drivers might work around this problem by using a test like:

   ret = pm_runtime_get_sync(dev);
   if (!ret || (ret == -EACCES && driver_private_data(dev)->suspended)) {
      /* access hardware */
   }

where driver_private_data(dev)->suspended is a flag set by the
driver's .suspend() method (that would have to be added for this
purpose).  However, that potentially would need to be done by multiple
drivers which means quite a lot of duplicated code and bloat.

To avoid that we can use the observation that the core sets
dev->power.is_suspended before disabling runtime PM and use that
instead of the driver's private flag.  Still, potentially many drivers
would need to repeat that same check in quite a few places, so it's
better to let the core do it.

Then we can be a bit smarter and check whether or not runtime PM was
disabled by the core only (disable_depth == 1) or by someone else in
addition to the core (disable_depth > 1).  In the former case
rpm_resume() can return 1 if the runtime PM status is RPM_ACTIVE,
because it means the device was active when the core disabled runtime
PM.  In the latter case it should still return -EACCES, because it
isn't clear why runtime PM has been disabled.

Tested on AM3730/Beagle-xM where a wakeup IRQ firing during the late
suspend phase triggers runtime PM activity in the I2C driver since the
wakeup IRQ is on an I2C-connected PMIC.

[rjw: Modified whitespace to follow the file's convention.]

Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
(cherry picked from commit 6f3c77b040fc24708228607bba504878de5236d1)
Change-Id: Idc33d188f460f6703e2fba147602b7b0a65f27c7
Reviewed-on: http://git-master/r/145855
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoPM / Runtime: Check device PM QoS setting before "no callbacks" check
Rafael J. Wysocki [Wed, 15 Aug 2012 19:32:04 +0000]
PM / Runtime: Check device PM QoS setting before "no callbacks" check

If __dev_pm_qos_read_value(dev) returns a negative value,
rpm_suspend() should return -EPERM for dev even if its
power.no_callbacks flag is set.  For this to happen, the device's
power.no_callbacks flag has to be checked after the PM QoS check,
so move the PM QoS check to rpm_check_suspend_allowed() (this will
make it cover idle notifications as well as runtime suspend too).

Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Cc: stable@vger.kernel.org
(cherry picked from commit 55d7ec4520e86d735d178c15d7df33d507bd43c6)
Change-Id: I02bbf2b76fc2881fdc13b0d885143a88addfc619
Reviewed-on: http://git-master/r/145854
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoPM / Runtime: Clear power.deferred_resume on success in rpm_suspend()
Rafael J. Wysocki [Wed, 15 Aug 2012 19:31:55 +0000]
PM / Runtime: Clear power.deferred_resume on success in rpm_suspend()

The power.deferred_resume can only be set if the runtime PM status
of device is RPM_SUSPENDING and it should be cleared after its
status has been changed, regardless of whether or not the runtime
suspend has been successful.  However, it only is cleared on
suspend failure, while it may remain set on successful suspend and
is happily leaked to rpm_resume() executed in that case.

That shouldn't happen, so if power.deferred_resume is set in
rpm_suspend() after the status has been changed to RPM_SUSPENDED,
clear it before calling rpm_resume().  Then, it doesn't need to be
cleared before changing the status to RPM_SUSPENDING any more,
because it's always cleared after the status has been changed to
either RPM_SUSPENDED (on success) or RPM_ACTIVE (on failure).

Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Cc: stable@vger.kernel.org
(cherry picked from commit 58a34de7b1a920d287d17d2ca08bc9aaf7e6d35b)
Change-Id: I1e46e92379c1880ecc3dc5588c4f11ea6f0679c8
Reviewed-on: http://git-master/r/145853
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoPM / Runtime: Fix rpm_resume() return value for power.no_callbacks set
Rafael J. Wysocki [Wed, 15 Aug 2012 19:31:45 +0000]
PM / Runtime: Fix rpm_resume() return value for power.no_callbacks set

For devices whose power.no_callbacks flag is set, rpm_resume()
should return 1 if the device's parent is already active, so that
the callers of pm_runtime_get() don't think that they have to wait
for the device to resume (asynchronously) in that case (the core
won't queue up an asynchronous resume in that case, so there's
nothing to wait for anyway).

Modify the code accordingly (and make sure that an idle notification
will be queued up on success, even if 1 is to be returned).

Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Cc: stable@vger.kernel.org
(cherry picked from commit 7f321c26c04807834fef4c524d2b21573423fc74)
Change-Id: Iad6e733535469a54932ab89574c1da356ce749a5
Reviewed-on: http://git-master/r/145852
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: pluto/dalmore: set VGP4 pinmux
Charlie Huang [Fri, 5 Oct 2012 20:30:57 +0000]
ARM: tegra: pluto/dalmore: set VGP4 pinmux

set the default mux to VGP4 and remove the gpio override in
board-pluto-sensors.c

Change-Id: Id08d0d53b75a67bc48df50cfe3a4fef7f1697be1
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit 5abc81df675eae63f69780d230fb54b37775d904)
Reviewed on: http://git-master/r/#change,142064
Reviewed-on: http://git-master/r/145668
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Philip Breczinski <pbreczinski@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoARM: tegra: config: enable flash AS3648
Charlie Huang [Sat, 8 Sep 2012 01:16:55 +0000]
ARM: tegra: config: enable flash AS3648

Device is enabled in both tegra3 and tegra114 defconfig files.

bug 1048411

Change-Id: Ib66684870262b73cfc7c315d4571e2967b75a95c
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit 481e9d0dcdb141abe49f8a1c4285b5e5beee194e)
Reviewed on: http://git-master/r/#change,133127
Reviewed-on: http://git-master/r/145662
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sivasubramaniam Venkataraman <svenkatarama@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agomedia: tegra: as3648: initial driver bring up
Charlie Huang [Fri, 7 Sep 2012 20:43:16 +0000]
media: tegra: as3648: initial driver bring up

New flash controller with dual led outputs, as well as over-current
protection, low-voltage protection, flash timeout control, etc.

bug 1048411

Change-Id: I20a74229cc357a4b93ed3ed70e663ef0acc258d9
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
(cherry picked from commit f84be39819cd40e2bfbc839ca7dd74c1143893be)
Reviewed on: http://git-master/r/#change,133114
Reviewed-on: http://git-master/r/145660
Reviewed-by: Sivasubramaniam Venkataraman <svenkatarama@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>

6 years agoMerge "Merge commit 'maxtouch-v3.0-16-Oct-2012' into ToT_2012-10-16_10-30-AM" into...
Simone Willett [Tue, 23 Oct 2012 01:38:18 +0000]
Merge "Merge commit 'maxtouch-v3.0-16-Oct-2012' into ToT_2012-10-16_10-30-AM" into android-tegra-nv-3.4

6 years agoARM: tegra11: clock: keep pll_re_vco disabled by default
Amit Kamath [Tue, 16 Oct 2012 11:34:38 +0000]
ARM: tegra11: clock: keep pll_re_vco disabled by default

Increases power consumption on rail AVDD_PLLE_AP
Bug 1158466

Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/144870
(cherry picked from commit b95079cbffdbdde0ef707b3a5472ef69145b625d)

Change-Id: I5121b335bf995c90f84d879e65e06b9d89efcc26
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146355
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: Tegra: clock: Change default state of pll_p_out3
Prashant Gaikwad [Mon, 15 Oct 2012 13:40:37 +0000]
ARM: Tegra: clock: Change default state of pll_p_out3

pll_p_out3 was kept on since some peripherals had it as
fixed parent. Currently all drivers for those peripherals
implement enable/disable for clocks derived from it.
No need to keep it enabled all the time.

Bug 1155689

Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-on: http://git-master/r/144572
(cherry picked from commit aa8df6af70b835eff2e150bd1f11e71313f982fa)

Change-Id: I33b3268bcf1abcdf483b4166df993538324f2b26

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: I7ea5d46a219138b14cb540c60dbbdf80d341526b
Reviewed-on: http://git-master/r/146354
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: decrease sclk min limit
Amit Kamath [Wed, 3 Oct 2012 09:24:12 +0000]
ARM: tegra11: clock: decrease sclk min limit

Change-Id: Iacd2339ba423363c89e6d81109cb88bb965115d5
Signed-off-by: Amit Kamath <akamath@nvidia.com>
Reviewed-on: http://git-master/r/141213
(cherry picked from commit 7720d2de96f9d726de0ddafddccee25760b2687c)
Reviewed-on: http://git-master/r/145587
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: pluto: Trim EMC DFS table
Alex Frid [Fri, 12 Oct 2012 22:51:41 +0000]
ARM: tegra: pluto: Trim EMC DFS table

Removed experimental low frequency entries from EMC DFS table.
Updated 408MHz and 204MHz entries.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/144242
(cherry picked from commit 7f48e9d4e0f183dda38cac487e5a7cb7840b121c)

Change-Id: Ied785e86dd1d8ee7a3903000bb6a17c9c826c451

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: Iddea47f41ad3ba7eaf2be2b5c693d5b08cf909d4
Reviewed-on: http://git-master/r/146339
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: pluto: Change clock source pll_m to pll_p
Vijay Mali [Tue, 2 Oct 2012 21:09:10 +0000]
ARM: tegra: pluto: Change clock source pll_m to pll_p

Change clock source from pll_m to pll_p for lower emc frequencies

Signed-off-by: Vijay Mali <vmali@nvidia.com>
Reviewed-on: http://git-master/r/143406
(cherry picked from commit bdd5886c50ba44a3092b2dc39d5c341dedab3d76)

Change-Id: I869a274d0f895bdc3609f81304d3ea1a5e8f9dd6

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: I4d9fb86966fbef670506f30153524724fe75d2b0
Reviewed-on: http://git-master/r/146338
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Vijay Mali <vmali@nvidia.com>
Tested-by: Vijay Mali <vmali@nvidia.com>

6 years agoARM: tegra: pluto: Update EMC tables
Daniel Solomon [Sun, 30 Sep 2012 07:29:01 +0000]
ARM: tegra: pluto: Update EMC tables

Update EMC tables with preliminary values, power
features included.

Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/143298
(cherry picked from commit a0a5bb60ac100e239b9d1c21580efaad96e78caf)

Change-Id: I1d2178d3ac613f3c7c0591356a0270dd89f2e35c

Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Change-Id: If9a104c26be9c04389cb6f1f7d81312b6f4aed8f
Reviewed-on: http://git-master/r/146337
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: fix build errors with tegra3 boards
Bharat Nihalani [Mon, 22 Oct 2012 07:35:05 +0000]
ARM: tegra: fix build errors with tegra3 boards

Dalmore and Pluto boards still get built for tegra3. Fix build
errors for such combination. This needs to be cleaned up as we
no longer need this combination to be supported.

Also fix issues that complain for 'defined but un-used' errors.

Change-Id: Ie41021cdf15ea62d1e704ea6e6e22d9f2224220d
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146290
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: clock: Switch from DFLL to PLL at low rate
Alex Frid [Thu, 11 Oct 2012 01:21:10 +0000]
ARM: tegra11: clock: Switch from DFLL to PLL at low rate

Added an option to automatically switch CPU clock source from DFLL
to PLL when target CPU rate is below DFLL minimum rate (instead of
using skipper). This option is disabled by default, and it is
controlled by /sys/module/tegra11_clocks/parameters/use_pll_cpu_low
parameter.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145169
(cherry picked from commit 0996421f20bedc55d605c89451f4680b616ba093)

Change-Id: Ieef31928d3f76c82fc4ced018c87acebbf84a5ac
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146289
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dvfs: Force CPU rail update
Alex Frid [Wed, 17 Oct 2012 03:08:56 +0000]
ARM: tegra: dvfs: Force CPU rail update

To force CPU rail update on exit from DFLL mode:

- altered by 1mV recorded rail level in DFLL mode, so that it won't
match any target level after switch from DFLL to PLL (actual level
in DFLL mode is approximately close to the recorded, anyway)

- altered by 1mV maximum limit requested from regulator, so that
core regulator call is not resolved as NOP (tegra dvfs would not
call core API to set the same voltage, with the exception of special
cases like switch from DFLL - and in these cases we do not need core
second guess).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145168
(cherry picked from commit e18df75763f0d9f6980a2d77ed8e532afda4e96d)

Change-Id: I45271085bc1cdd9176a9a136b389292c6336ed35
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146288
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Fix G-to-G CPU switch
Alex Frid [Thu, 18 Oct 2012 01:47:49 +0000]
ARM: tegra11: clock: Fix G-to-G CPU switch

Made sure that forced G-to-G CPU cluster switch does not mess up
CPU clock sources (it was erroneously switching from DFLL to PLL).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145452
(cherry picked from commit 2ce09a9506200c96410842d1714ca294c7b81344)

Change-Id: If4e5d783c92e7d970b79448cf2368168034edb87
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146287
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Use cvb model for pll clock source
Alex Frid [Tue, 16 Oct 2012 23:54:58 +0000]
ARM: tegra11: dvfs: Use cvb model for pll clock source

Added separate cvb coefficients for calculating CPU dvfs table with
pll clock source (instead of just adding margin on top of dfll source
voltage). This data is preliminary, pll source is disabled by default.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/145167
(cherry picked from commit 02fb97ea8f2c47716760e64405ab19af9d8bbd0c)

Change-Id: I6adbcfa04ac7982a2f1bb27eb6e0b07f68b05304
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146286
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Don't apply dfll min voltage in pll mode
Alex Frid [Thu, 4 Oct 2012 05:17:13 +0000]
ARM: tegra11: dvfs: Don't apply dfll min voltage in pll mode

- do not apply minimum dfll voltage limit in pll mode, and allow
voltage to go as low as cvb dvfs table output suggest.
- do not strip dvfs frequencies with predicted cvb voltage below
minimum dfll voltage, since they can be reached in pll mode

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141748
(cherry picked from commit 008ede787fbe6c10773e2b872a589f2870b033d4)

Change-Id: I0d5d5f756f76913a021b86c562daa13090938e81
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146285
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Move min millivolts to dfll_data
Alex Frid [Thu, 4 Oct 2012 03:19:20 +0000]
ARM: tegra11: dvfs: Move min millivolts to dfll_data

Moved minimum millivolts entry from upper level cpu dvfs data to
dfll specific data, since it should be applied in dfll mode only
(for now, it is still applied in both pll and dfll modes).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141747
(cherry picked from commit d0b1b98c07bcce2e321d0db6e10ffcdb0425f43e)

Change-Id: I4ecc0505316a137151112b00a41d93a2142a7ba2
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146284
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dalmore: Add EMC DFS table for E1611 board
Alex Frid [Sat, 6 Oct 2012 03:31:30 +0000]
ARM: tegra: dalmore: Add EMC DFS table for E1611 board

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/144371
(cherry picked from commit 1766f2e6193282d7b2d4e8d471017631acab2e8f)

Change-Id: I3db76ce78c3370e2d06e98e943b91032c5172a18
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146283
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update DFLL switch error handling
Alex Frid [Thu, 11 Oct 2012 02:35:44 +0000]
ARM: tegra11: clock: Update DFLL switch error handling

The changes below provide WAR for possible I2C deadlock if CL-DVFS
output is disabled while the I2C request is pending.

- Switch to Open Loop mode at the beginning of unlocking API (this
guarantees at most 2 outstanding transaction), drain pending (if any)
transactions, and then disable output.

- Separated cl_dvfs output_enable() and output_disable() operations.
Swap the order of waiting for output interface quiet and disabling
the output: first wait for quiet interface, and then disable output.
Re-enable interface if pending request is set again and continue
waiting until quiet state is confirmed or timeout is expired. Passed
timeout error to the caller of unlocking API.

- When switching CPU clock source from DFLL to PLL, restore DFLL
clock source and DFLL rail control in case of switch error,
including unlock timeout error.

- When switching from CPU G mode to CPU LP mode, re-lock DFLL in
case of switch error, including unlock timeout error.

- When switching CPU clock source from PLL to DFLL, move control
of VDD_CPU rail to DFLL even if it failed to lock (lock failure
should never happen here, and WARN() will be replaced with BUG()).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/144305
(cherry picked from commit 6c2782755b082b005fc7ce8e82e9f051e64bfbf1)

Change-Id: I4b4229f2737eed9bdffca2efbd08fc9a5ac058e3
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146282
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Remove pll table restriction
Alex Frid [Sat, 13 Oct 2012 05:28:59 +0000]
ARM: tegra11: clock: Remove pll table restriction

Removed requirement for dynamic ramp PLLs tabulated configuration to
always use post-divider 1 for rate above VCO minimum. Too restrictive,
and not necessary.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/144306
(cherry picked from commit 3ae859c123866d5270234af745790b4bb8fa36b9)

Change-Id: If1ffc488d1b826ae3e648a9354db0c63f31e7271
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146280
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Add PLLC rate initialization
Alex Frid [Thu, 11 Oct 2012 19:43:54 +0000]
ARM: tegra11: clock: Add PLLC rate initialization

Added explicit PLLC rate configuration to clock table in case of
dual cbus (for a single cbus it is configured implicitly as part
of cbus initialization).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/143818
(cherry picked from commit 00018f0040b4628bd8424da64d89cc4fd2e2ee32)

Change-Id: I9ebf3b2aa2f69df2c5b265238a9bd9aa4c532657
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146279
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Initialize pll_re_vco to 312 MHz
Alex Frid [Sat, 6 Oct 2012 00:21:28 +0000]
ARM: tegra11: clock: Initialize pll_re_vco to 312 MHz

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142128
(cherry picked from commit 218e7e5f5fc097198d56980818b0c510b588be3b)

Change-Id: Ia152b61a9f3df7662a9be67bc13afe0b1d7f978e
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146278
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Dynamically allocate cl dvfs object
Alex Frid [Tue, 9 Oct 2012 07:44:14 +0000]
ARM: tegra11: dvfs: Dynamically allocate cl dvfs object

Dynamically allocated cl dvfs object by the cl-dvfs driver, and
hide cl_dvfs structure definition from clock framework.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142851
(cherry picked from commit a2adb1710edc52c61b1fa336e5253aa5735ec717)

Change-Id: I6dd1af043d15aba143bdf02bb53dd1e796784626
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146277
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Acquire CL-DVFS clocks in probe
Alex Frid [Tue, 9 Oct 2012 06:00:48 +0000]
ARM: tegra11: dvfs: Acquire CL-DVFS clocks in probe

Acquired CL-DVFS clocks in driver probe function (instead of
pre-populating during dfll initialization).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142850
(cherry picked from commit 66dc99a9ce766bb464a1ddfab49cf89776fc006b)

Change-Id: I9b94f9c61f7b0a76ae3433fe752b0ed5e1941cb6
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146276

6 years agoARM: tegra: pluto: Add EMC DFS table
Alex Frid [Fri, 28 Sep 2012 21:39:55 +0000]
ARM: tegra: pluto: Add EMC DFS table

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139824
(cherry picked from commit f751de8bd24dcdd3387b3ecc9c8fb59d01890cdf)

Change-Id: I222518dae63800f7800bc893e1d30ad92ece466b
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146275
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Enable PLLE VREG
Alex Frid [Wed, 10 Oct 2012 02:00:28 +0000]
ARM: tegra11: clock: Enable PLLE VREG

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142829
(cherry picked from commit 099ccea9a52f351826a1200759e67718213ac1a1)

Change-Id: I95aa4bc199633693810fda505156444137da120e
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146274
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Put PLLU under h/w control
Alex Frid [Mon, 8 Oct 2012 23:14:26 +0000]
ARM: tegra11: clock: Put PLLU under h/w control

Put PLLU under h/w control, let s/w enable bits for secondary PLLU
dividers to be cleared.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142507
(cherry picked from commit 971e348d8317416b4f51d32c3515087c7c6dc18a)

Change-Id: I0b3692f1ba653eaea31c4cdd329ee5e5ed01f0d7
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146273
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dalmore: Add E1611 EMC DFS table template
Alex Frid [Fri, 5 Oct 2012 21:45:26 +0000]
ARM: tegra: dalmore: Add E1611 EMC DFS table template

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142127
(cherry picked from commit df6a6a5a2685655d1fa940485632264e5e1d0abd)

Change-Id: Ifdbe8190e08a27d9123e1bb12006430282a0a162
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146272
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update PLLC2/C3 configuration
Alex Frid [Tue, 25 Sep 2012 21:50:06 +0000]
ARM: tegra11: clock: Update PLLC2/C3 configuration

- Lower vco min to 600MHz
- Do not allow multiples of 3 as post divider values
- Extend unlock frame number

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/138754
(cherry picked from commit 8dea2e5438e76717931b34f5ee3d1f9a88703f0b)

Change-Id: I9fb441f5cadc23ab78f836438ee8aefade6b310d
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146271
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Add CL-DVFS platform device
Alex Frid [Sun, 7 Oct 2012 05:10:00 +0000]
ARM: tegra11: dvfs: Add CL-DVFS platform device

Added CL-DVFS platform device. Converted CL-DVFS module to platform
device driver, used driver registration to get CL_DVFS platform data
instead of calling board level API.

Change-Id: I5283e80c5d43f0259743b55bd3ad6783c639b090
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/142169
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146270
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra11: dvfs: Update CL-DVFS max voltage dynamically
Alex Frid [Wed, 3 Oct 2012 23:02:17 +0000]
ARM: tegra11: dvfs: Update CL-DVFS max voltage dynamically

Dynamically update CL-DVFS maximum voltage when target frequency
is changed (instead of keeping it at chip reliability limit always).
New maximum level is matching safe dvfs table entry for the requested
frequency.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141746
(cherry picked from commit e37e77eba2307e34489f9ac012d7fb7b5c405a29)

Change-Id: I01f6c8b3204e272441ddeafa1e2dc4bb5c3e252c
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146269
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Return CL-DVFS monitored rate
Alex Frid [Tue, 2 Oct 2012 20:33:57 +0000]
ARM: tegra11: dvfs: Return CL-DVFS monitored rate

When reading CL-DVFS monitor, convert readout into Hz.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141138
(cherry picked from commit 4fd847d5c6fa487b7ca4d1824af7afa55f5964d6)

Change-Id: Ib424c2aa27fc95664748ed8ddc47157710663ae7
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146268
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Select TEGRA_USE_DFLL config option
Alex Frid [Tue, 25 Sep 2012 04:45:26 +0000]
ARM: tegra11: dvfs: Select TEGRA_USE_DFLL config option

Change-Id: Ibd45d2de42fbbb9ecd87f7cdec53df73bd7b7ecb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/135001
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146267
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Remove CL-DVFS I2C fast clock
Alex Frid [Tue, 2 Oct 2012 20:08:40 +0000]
ARM: tegra11: dvfs: Remove CL-DVFS I2C fast clock

Since CL-DVFS I2c controller does not have i2c_fast clock, removed
the latter from CL-DVFS list of clocks.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/141137
(cherry picked from commit 4478aca99834686e338636798f2c9e6841ddda9b)

Change-Id: Iac84c6968502a6b7023025a92e900900ded1a5d1
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146266
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Add DFLL resume operation
Alex Frid [Sun, 30 Sep 2012 02:58:53 +0000]
ARM: tegra11: clock: Add DFLL resume operation

- Implemented DFLL resume including CL-DVFS state restoration.
- Moved G-CPU clock resume after DFLL.
- Made sure that LP-CPU clock is enabled before cluster switch on
entry to LP0 (it can be disabled on tegra11 if G-CPU is on DFLL).

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/140004
(cherry picked from commit 09f59e09eab56e855ab36c43244f0e04a3246216)

Change-Id: I90cf3f5c8c54bb99303851b30b42da49b47e208f
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146265
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update cpufreq table construction
Alex Frid [Mon, 1 Oct 2012 20:31:28 +0000]
ARM: tegra11: clock: Update cpufreq table construction

Use G CPU dvfs table step (102 MHz) to fill in the gap between
maximum LP CPU and minimum G CPU rates for construction of cpufreq
table

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/140757
(cherry picked from commit 826d7351d94518a19df5d7a9739d76e35a60e1f8)

Change-Id: I24cfecc466254ef0085112253f17980c41f0d8a4
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146264
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Fix CL-DVFS output mapping
Alex Frid [Mon, 1 Oct 2012 20:11:21 +0000]
ARM: tegra11: dvfs: Fix CL-DVFS output mapping

Since commit 4adbd45cddd9efdbc12e0e668cf562aca3bed38d allows two
top entries in dvfs frequency list with the same (maximum) safe
voltage, updated CL-DVFS output mapping procedure, to continue
mapping when maximum voltage is reached.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/140756
(cherry picked from commit ef925a158c7a52b9761f653787f57faac21f106e)

Change-Id: I5134ccea757e380660b484bdaa20020b1bad9440
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146263
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Increase maximum EMC rate at nominal voltage
Alex Frid [Mon, 1 Oct 2012 07:11:44 +0000]
ARM: tegra11: dvfs: Increase maximum EMC rate at nominal voltage

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/140554
(cherry picked from commit 181455d601f3c1e6a25d32b9a0bd23d37e20362f)

Change-Id: I7b1a8796d313c00c8b9414e3851873a8b615074f
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146262

6 years agoARM: tegra: power: Suspend/resume cpu dfll mode
Alex Frid [Sat, 29 Sep 2012 02:57:41 +0000]
ARM: tegra: power: Suspend/resume cpu dfll mode

If DFLL is used as CPU clock source switch to open loop mode before
cpu rail is turned off when rail-gating during idle (LP2 last), or
suspending the system (entering LP1 or LP0 states). Consolidated this
controls in pm.c file.

Change-Id: I8ed7f29a733225533dd94cce0b14f66dad258310
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139930
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146261
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Add dummy EMC ccfifo write
Alex Frid [Sun, 30 Sep 2012 03:32:18 +0000]
ARM: tegra11: clock: Add dummy EMC ccfifo write

Added dummy EMC ccfifo write to read-only register to make sure that
at least one ccfifo write is pushed after stall-after-change marker.
Without this dummy write EMC ccfifo (and the entire system) will hang
after clock change that does not update other registers via ccfifo.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139974
(cherry picked from commit 2c57e98d8b4e2781666412773f10794e707d2e7f)

Change-Id: I9784986c129fd60dcdf17af2fd7eb0088fbaf43e
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146260
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Round up CPU dvfs frequency list
Alex Frid [Sat, 29 Sep 2012 04:52:11 +0000]
ARM: tegra11: dvfs: Round up CPU dvfs frequency list

When predicted cpu voltage in dfll mode crosses maximum limit, keep
the respective frequency in the dvfs table ("round the list up"). The
voltage limit will be enforced anyway, and when the top frequency is
requested dfll will settle at whatever high rate it can reach on the
particular chip.

This change is relevant only until cvb coefficients characterization
is completed. With production coefficients predicted voltage will
never exceed maximum limit.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139929
(cherry picked from commit 4adbd45cddd9efdbc12e0e668cf562aca3bed38d)

Change-Id: I7bb034d193385b726742d7ee1ff83a5ade8f63cf
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146259
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Update CPU rate and voltage range
Alex Frid [Fri, 28 Sep 2012 20:11:16 +0000]
ARM: tegra11: dvfs: Update CPU rate and voltage range

- Set CPU voltage range 1.0V ... 1.230V
- Extended CPU frequency range up 1836 MHz

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139799
(cherry picked from commit df0d52bd4b2f8f90b756674c4e6d23bc7fd20345)

Change-Id: Ia8e7dac2d543d5de46d3396f9fbd9b2b02e9fe30
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146258
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: pluto: Add EMC DFS template
Alex Frid [Fri, 28 Sep 2012 03:09:50 +0000]
ARM: tegra: pluto: Add EMC DFS template

Created EMC DFS template and registered EMC device (with empty
table, for now).

Change-Id: I83e4ad4660855f3a50fc644b358641b5c10e493d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139558
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146257
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dalmore: Add EMC DFS template
Alex Frid [Thu, 20 Sep 2012 23:46:12 +0000]
ARM: tegra: dalmore: Add EMC DFS template

Created EMC DFS template and registered EMC device (with empty
table, for now).

Change-Id: Icf1e8d6decb9de36f884ada44536b02f8f7064ca
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/139289
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146256
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: pluto: Add CL-DVFS platform data
Alex Frid [Sun, 23 Sep 2012 06:42:01 +0000]
ARM: tegra: pluto: Add CL-DVFS platform data

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134650
(cherry picked from commit bd48d0c476a63dde113449796517650dd30d04fc)

Change-Id: I33beb954484d0f4a817b29c4c2a7f5a14bb95a1d
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146255
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoARM: tegra: dvfs: Add TEGRA_USE_DFLL config option
Alex Frid [Tue, 25 Sep 2012 04:27:41 +0000]
ARM: tegra: dvfs: Add TEGRA_USE_DFLL config option

Change-Id: Ie8766c6860dbc87f3b36618cafb9f6792b3fef02
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/135000
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146254
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Increase PLLX vco max limit
Alex Frid [Tue, 25 Sep 2012 07:11:18 +0000]
ARM: tegra11: clock: Increase PLLX vco max limit

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/135025
(cherry picked from commit d6ebf5cecb2a6ca27b5921d7a990266bcdf05f6c)

Change-Id: Icaf66d47df756992ac92f758693caddb980ea16a
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146253
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Keep PLLE under s/w control
Alex Frid [Tue, 25 Sep 2012 07:07:31 +0000]
ARM: tegra11: clock: Keep PLLE under s/w control

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/135024
(cherry picked from commit 1709a98df3d07ff549b20eb5a11d93fdde2da4d3)

Change-Id: I38f73ca41d46782db8f1468b6aca750cbb5874bd
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146252
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: fuse: Read speedo values from chip fuses
Alex Frid [Tue, 25 Sep 2012 04:15:27 +0000]
ARM: tegra11: fuse: Read speedo values from chip fuses

Based on original work by Matthew Longnecker <mlongnecker@nvidia.com>

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134999
(cherry picked from commit d7b619c8ea77cf52c90a27448d1183b3e0899218)

Change-Id: I327d0d39efccfd7e189c02370c9c7f95252172fc
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146251
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: dvfs: Increased CPU min voltage limit
Alex Frid [Mon, 24 Sep 2012 21:22:12 +0000]
ARM: tegra11: dvfs: Increased CPU min voltage limit

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134921
(cherry picked from commit d938033c90cf017bf75f2360da1dc98a8eebadec)

Change-Id: I64b4df3a28d4ce9ae98487c7524d8951ae71735f
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146250
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update PLLC2/C3 settings
Alex Frid [Sun, 23 Sep 2012 05:14:39 +0000]
ARM: tegra11: clock: Update PLLC2/C3 settings

Bug 1053337

Change-Id: I2dd8e376d198e442b1a0b7a4de76785c263bc76d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134649
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146249
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update EMC DFS table format
Alex Frid [Thu, 20 Sep 2012 22:03:20 +0000]
ARM: tegra11: clock: Update EMC DFS table format

Moved trimmers registers from common burst array to per-channel
trimmers arrays. Change array order in table structure. Fixed
start timing rate calculation.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134259
(cherry picked from commit 0505cfc8f5b9c6e11adf60d68788ef3c0f385222)

Change-Id: I33fc718e234234efbda0e34acc657cdaaecd1455
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146248
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Modify dqs preset operation
Alex Frid [Sun, 16 Sep 2012 06:44:30 +0000]
ARM: tegra11: clock: Modify dqs preset operation

Modified dqs preset operation during EMC clock change to work on
separate settings for EMC channel 0 and 1.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/133065
(cherry picked from commit b487cbda920e8eaf783d3b8ea0fb7a9dba0a5f4f)

Change-Id: Ia802a3194495df784a198859f33ee6ea004af6bd
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146247

6 years agoARM: tegra11: clock: Add use dfll parameter callback
Alex Frid [Thu, 20 Sep 2012 07:01:42 +0000]
ARM: tegra11: clock: Add use dfll parameter callback

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/134268
(cherry picked from commit 1766f138bd046c83b1f5b684f0d15a9106961e83)

Change-Id: If1a7fa26785819f649e4351965968b4130aad15c
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146246
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra11: clock: Update switch to/from dfll clock source
Alex Frid [Wed, 19 Sep 2012 23:28:05 +0000]
ARM: tegra11: clock: Update switch to/from dfll clock source

- Updated dvfs state variables and stats when switching to/from dfll
clock source.
- Made sure nominal voltage level is restored when switching from dfll
with disabled rail scaling.
- Round down target rate when switching from dfll to pll if it exceeds
pll mode maximum limit
- Implement 1-step dfll to pll switch directly to the new rate (instead
of 2-step switch from dfll to pll at the old rate, and then to the new
rate already on pll).

Change-Id: I13cfb89b47905cbc7c8b27a30cbc6472d4f651f3
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/133969
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146245

6 years agoARM: tegra11: power: Read LPDDR2/3 temperature
Alex Frid [Thu, 30 Aug 2012 06:39:48 +0000]
ARM: tegra11: power: Read LPDDR2/3 temperature

Change-Id: I52ab569c3568f7e47c5d4a5ce6f151fa51bbad08
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/132380
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146244
Reviewed-by: Automatic_Commit_Validation_User

6 years agoARM: tegra: dalmore/pluto: fix palmas init
Pradeep Goudagunta [Fri, 12 Oct 2012 08:46:19 +0000]
ARM: tegra: dalmore/pluto: fix palmas init

Fix palmas platform data initialization.

Reviewed-on: http://git-master/r/144026
(cherry picked from commit df44ead1c39ca281f87f4242d10512cb39e14203)

Conflicts:

arch/arm/mach-tegra/board-dalmore-power.c

Change-Id: I9fecaab84dac6e90e3a159f5eca0b7dc5c13b6f8
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/145891
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agomfd: palmas: Change regulator defns to better suite DT
Graeme Gregory [Tue, 28 Aug 2012 11:47:39 +0000]
mfd: palmas: Change regulator defns to better suite DT

In order to better fit DT parsing in of regulator definitions re-arrange
the platform data struct slightly which requires the definitions of
the regulator IDs earlier in the include file.

Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
(cherry picked from commit 7cc4c92fbc1b539597c00656b3236a57d76022f4)

Conflicts:

include/linux/mfd/palmas.h

Reviewed-on: http://git-master/r/144024
(cherry picked from commit bb762eccf74e729a907f22ee570d2743fada10f2)

Change-Id: Ic429548c054f2c8448c7a7aeb1d574d0631db62c
Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/145889
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: pluto: pinmux: fix UARTA
Pradeep Goudagunta [Fri, 21 Sep 2012 22:58:35 +0000]
ARM: tegra: pluto: pinmux: fix UARTA

KB pins are configured to UARTA in BL so make them
RSVD1 to deselect/clear UARTA selection.

Bug 1047414

Signed-off-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-on: http://git-master/r/134261
(cherry picked from commit 8f05f246dbc87001363132b6af95d14be3a94dd1)
Change-Id: I0bc7b62e8eb353e19506b80165b85c38582dfe57
Reviewed-on: http://git-master/r/145885
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agoARM: tegra: dalmore/pluto: increase framebuffer size
Jon Mayo [Thu, 18 Oct 2012 18:47:33 +0000]
ARM: tegra: dalmore/pluto: increase framebuffer size

Increase reserved framebuffer size to be twice the maximum resolution.
This is required for android recovery to do double buffering on /dev/fb0.

Change a spammy print from info to debug.

Bug 1054266
Bug 1159399

Change-Id: Icdcdec23133190e19de8d26c98f8b2f6ec8d9c24
Signed-off-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-on: http://git-master/r/145673
Reviewed-by: Automatic_Commit_Validation_User

6 years agomedia: tegra: imx091: fix pinkish preview issue
Frank Chen [Thu, 11 Oct 2012 18:04:13 +0000]
media: tegra: imx091: fix pinkish preview issue

Do software reset instead of standby before
programming the new sensor mode.

Bug 1156556

Change-Id: Icba79ff790905c810ed88533b74287b458d98423
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/143791
(cherry picked from commit 816c361834aa5a8c7a490a79088ae52047fe38f7)
Reviewed-on: http://git-master/r/145641
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Patrick Shehane <pshehane@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agoChromeOs: enable config TEGRA_PREPOWER_WIFI
Wei Ni [Mon, 8 Oct 2012 08:42:03 +0000]
ChromeOs: enable config TEGRA_PREPOWER_WIFI

Use brcmfmac for both bcm4329 and bcm4330.
Enable TEGRA_PREPOWER_WIFI:
enable it, so that the sdhci driver can scan the wlan.
Disable BCMDHD
disable bcmdhd driver,which is for bcm4330.

Change-Id: I4c08638a7038349019ce515abe477f8faa2b5726
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: http://git-master/r/143991
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: e1853: add WXGA touch panel support
Dongfang Shi [Tue, 4 Sep 2012 23:49:20 +0000]
arm: tegra: e1853: add WXGA touch panel support

Support WXGA display and touch input for e1853.

bug 1036173

Change-Id: Ia66119c1f05dd61a46346a1b7e5dc5bbbeb43495
Signed-off-by: Dongfang Shi <dshi@nvidia.com>
Reviewed-on: http://git-master/r/129521
(cherry picked from commit a766194a31b6fe7e9834959a19c88d375c15d6de)
Reviewed-on: http://git-master/r/143774
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: e1853: Config LVDS for display 1.
Dongfang Shi [Wed, 29 Aug 2012 21:36:48 +0000]
arm: tegra: e1853: Config LVDS for display 1.

Program FPDLink Serializer for display 1.

bug 966833

Change-Id: I6eba4655eae4418480f16089abd3a406e2111721
Signed-off-by: Dongfang Shi <dshi@nvidia.com>
Reviewed-on: http://git-master/r/128283
(cherry picked from commit 2920d48bb5a8c00d1d731199ab4cfd01e5b30c98)
Reviewed-on: http://git-master/r/139034
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Jon Mayo <jmayo@nvidia.com>

6 years agoRevert "ARM: config: tegra3: Enable PLATFORM_ENABLE_IOMMU"
Mrutyunjay Sawant [Mon, 22 Oct 2012 12:52:50 +0000]
Revert "ARM: config: tegra3: Enable PLATFORM_ENABLE_IOMMU"

This reverts commit cde08d2ba6697f307e95493f24ba91d06242951c.

Change-Id: Iea2328e5e8168f7f01a82538626bd9e7bb209aca
Reviewed-on: http://git-master/r/146398
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agomedia: video: tegra: tegra_camera: remove reset
Jihoon Bang [Mon, 8 Oct 2012 18:30:01 +0000]
media: video: tegra: tegra_camera: remove reset

Resetting VI, ISP and CSI is taken care of by
tegra_powergate_partition and tegra_unpowergate_partition api.
tegra_camera doesn't have to reset them again.

Bug 1059495

Reviewed-on: http://git-master/r/142451
(cherry picked from commit 3c08187fe1d5c8f44de6e40c96de1ce6e71f34eb)

Change-Id: Ia98e1ccfc5ea9c5080b99c3c74b929c771232e31
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/145665
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>

6 years agoRevert "arm: tegra: optimize L2 enable/disable paths for secureos"
Deepak Nibade [Wed, 17 Oct 2012 15:19:20 +0000]
Revert "arm: tegra: optimize L2 enable/disable paths for secureos"

With this revert, Dalmore enters LP0 state in Main
Otherwise NULL exception is encountered (variable l2x0_base)
Revert is required till we get proper secureos code and we
ensure that T114 does not enter l2x0 code

This reverts commit 7274dfdea8e1512b863438d4f34074a67b5b4a97.

Change-Id: Ib3ff4f1664fdc1693c2768eb3ecc0205a456c982
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/145288
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

6 years agopm: EDP: enable updates via sysfs
Sivaram Nair [Wed, 17 Oct 2012 12:37:03 +0000]
pm: EDP: enable updates via sysfs

This patch allows the user space to issue E-state and threshold change
requests. E-state updates are allowed only if the change is guaranteed
to be approved.

Change-Id: Id31f06ebb95f0b1fdfce205cb17038cb7a9eb30e
Signed-off-by: Sivaram Nair <sivaramn@nvidia.com>
Reviewed-on: http://git-master/r/145256
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>

6 years agoarm: tegra: raydium: fix coverity issue
Sri Krishna chowdary [Tue, 16 Oct 2012 13:12:01 +0000]
arm: tegra: raydium: fix coverity issue

Check return values of gpio_request
and gpio_direction_input/output for touch.

Bug 1046331

Change-Id: I804d74657d1769c40727b3d8ae318f12f1d83098
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/144901
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agoarm: tegra: pluto: fix coverity issue
Sri Krishna chowdary [Tue, 16 Oct 2012 12:54:57 +0000]
arm: tegra: pluto: fix coverity issue

Check return value.

Bug 1046331

Change-Id: I313d5868e1a47110f30345d6b19b188fd025c09c
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/144893
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agoarm: tegra: enterprise: fix coverity issue
Sri Krishna chowdary [Tue, 16 Oct 2012 09:10:30 +0000]
arm: tegra: enterprise: fix coverity issue

Check return values for gpio_return and
gpio_direction_input/output for panel and
touch.

Bug 1046331

Change-Id: Ib7ab615a699e4d506d13540b3def98c46820bd11
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/144811
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agomfd: Added rtc resources & fixed interrupt init
Sumit Sharma [Tue, 16 Oct 2012 05:37:39 +0000]
mfd: Added rtc resources & fixed interrupt init

Added rtc resources for tps65910-rtc
Fixed interrupt initialiazation for tps65910

Bug 1055083

Change-Id: Idbb5098830075fe459020d5bdf264d9414b7cb8d
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/144779
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agogpio: tps65910: Added gpio to irq support
Sumit Sharma [Tue, 16 Oct 2012 03:35:14 +0000]
gpio: tps65910: Added gpio to irq support

Added gpio to irq mapping support for tps65910

Bug 1055083

Change-Id: I6cf48361a0d54c588698438bc1f57a19b2b94bd8
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/144736
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>

6 years agoarm: tegra: Add MAX1749 platform device
Sumit Sharma [Wed, 17 Oct 2012 03:49:43 +0000]
arm: tegra: Add MAX1749 platform device

Added MAX1749 vibrator platform device in cardhu board file

Bug 1154522

Change-Id: I6464c0cf9739bae91d9c4d8b86b86be5a57a5b57
Signed-off-by: Sumit Sharma <sumsharma@nvidia.com>
Reviewed-on: http://git-master/r/144518
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agousb: gadget: tegra: fix coverity issue
Sri Krishna chowdary [Sun, 14 Oct 2012 07:00:36 +0000]
usb: gadget: tegra: fix coverity issue

name cant be NULL, it is static array.
Add check if name is empty string.

Bug 1046331

Change-Id: I2615ae0d24e44025b7528e10d0dafb124d355b4f
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/144374
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoasoc: tegra: wm8903: Fix the bug that wm8903 device is init twice
Shaoming Feng [Fri, 12 Oct 2012 22:35:17 +0000]
asoc: tegra: wm8903: Fix the bug that wm8903 device is init twice

Bug: 1056985

Change-Id: Id57093ccfbcb0673b660cd8cb0157d48078173c4
Signed-off-by: Shaoming Feng <shaomingf@nvidia.com>
Reviewed-on: http://git-master/r/144190
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

6 years agoarm: tegra: power: fix coverity issue
Sri Krishna chowdary [Sat, 6 Oct 2012 09:58:27 +0000]
arm: tegra: power: fix coverity issue

Fix Unsigned can't be less than zero issue.
tegra_dvfs_predict_millivolts returns int, so
voltage_mV can't be unsigned int.

Bug 1046331

Change-Id: I7973c3a434beef1cc54c4d61024b0b381c4fc66f
Signed-off-by: Sri Krishna chowdary <schowdary@nvidia.com>
Reviewed-on: http://git-master/r/142152
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

6 years agoARM: config: tegra3: Enable PLATFORM_ENABLE_IOMMU
Hiroshi Doyu [Mon, 16 Jul 2012 07:48:13 +0000]
ARM: config: tegra3: Enable PLATFORM_ENABLE_IOMMU

Make all platform device IOMMU'able. Those device drivers are expected
to use DMA API correctly.

Bug 956490

Change-Id: I0ff010cbf4d8a5b88bd07c9c56644dbb07469667
Signed-off-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-on: http://git-master/r/139662
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>