Alex Frid [Sat, 19 Mar 2011 01:08:54 +0000 (18:08 -0700)]
ARM: tegra: clock: Changed PLLE settings
Bug 792743
Original-Change-Id: I9ea94faefa01406ff16d2b78eab251b3b35cae9a
Reviewed-on: http://git-master/r/23733 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I4d0f4de7e5d32050010e368aef05f8b6bc20f6e1
Alex Frid [Mon, 21 Mar 2011 02:16:32 +0000 (19:16 -0700)]
ARM: tegra: clock: Update twd clock settings
On Tegra3 twd peripheral clock is divided by 2 from CPU clock
(while on Tegra2 divide by 4 was used).
Original-Change-Id: I15ee928049d21bda1a39b43ff88edc5f9d6675f6
Reviewed-on: http://git-master/r/23732 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I82772100308231bd43a005724c91f9455e575cf4
Alex Frid [Fri, 18 Mar 2011 23:40:15 +0000 (16:40 -0700)]
ARM: tegra: power: Don't enable stats interrupt on Tegra3
Tegra3 does not use stats monitor - do not blindly enable it on exit
from LP2
Original-Change-Id: I9fbcfcefc67510f6145a78edfc35362f9c059cf9
Reviewed-on: http://git-master/r/23731 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ib4797f3ab7ec047975edbaeac7c813e48b93ec0a
Scott Williams [Mon, 14 Mar 2011 22:28:33 +0000 (15:28 -0700)]
arm: tegra: Add support for T30.A02
Bug 784484
Original-Change-Id: I8aec236c62f01c3f319b1d96c8c13464cb564904
Reviewed-on: http://git-master/r/22886 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8f857fe8422c60b2ec3ccc0961bbd426e3c69c29
Jin Qian [Sat, 12 Mar 2011 04:37:35 +0000 (20:37 -0800)]
arm: tegra: fix ventana build break
Fix build break on ventana due to improper use
of kernel config paramters.
Original-Change-Id: I7ec13091cf67fa5cb25b39c92eb33756263506c4
Reviewed-on: http://git-master/r/22705 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id942dc5dc79e0edf5dc27d418083f340ae40edb8
Bo Yan [Wed, 2 Mar 2011 19:56:27 +0000 (11:56 -0800)]
arm: tegra: update clock settings for some modules
Original-Change-Id: If2d5e59817fa97e07209b800716f44827a33d87c
Reviewed-on: http://git-master/r/21417 Reviewed-by: Bo Yan <byan@nvidia.com> Tested-by: Bo Yan <byan@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Original-Change-Id: I1adf32978cc8cc3ee4ce08c3d408b2a21ee9e9d6
Alex Frid [Sun, 13 Feb 2011 01:20:43 +0000 (17:20 -0800)]
ARM: tegra: cpu: Update auto-hotplug policy
Do not switch to G cluster if cpufreq spikes above LP frequency limit
for a short time - currently set threshold to 100ms. Fixed timing
update for LP cluster statistic.
Alex Frid [Sat, 12 Feb 2011 02:17:28 +0000 (18:17 -0800)]
ARM: tegra: Update secondary CPU power up procedure
- Wait for power up status confirmation after secondary CPU was
un-gated by flow controller (instead of directly UN-gating CPU
again if the 1st status check failed).
- Enable CPU clock only after power up is confirmed.
- Insert propagation delays before and after removing clamps.
Scott Williams [Sat, 12 Feb 2011 01:21:05 +0000 (17:21 -0800)]
arm: tegra: Fix compiler errors for non-SMP configurations
Original-Change-Id: I7bbf5e25aa041900542e33cc5904ddcc3a945aab
Reviewed-on: http://git-master/r/19323 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ie18283ad5184b4c820c3a23b1ec8e970ad61467a
Scott Williams [Fri, 11 Feb 2011 22:37:19 +0000 (14:37 -0800)]
arm: tegra: Fix initial boot to LP cluster
Forbid cluster switch to G cluster if the G cluster doesn't exist.
Bug 791057
Original-Change-Id: I215de2581edf5fb3c1feaa00d1c6e0b52b15dc23
Reviewed-on: http://git-master/r/19302 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Id0a7e5ad62df4d1638518fe00715aac60e4efea9
Scott Williams [Thu, 10 Feb 2011 22:35:32 +0000 (14:35 -0800)]
arm: tegra: Reserve SMMU I/O window address space
Bug 790951
Bug 791114
Original-Change-Id: I50ac8b20c1a1cd2ed5c135f940ec1791fb3dc6c0
Reviewed-on: http://git-master/r/19145 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I3406c6cc5b0733b91965983028dc5935f2ad62f8
Alex Frid [Thu, 10 Feb 2011 02:40:23 +0000 (18:40 -0800)]
ARM: tegra: clock: Add Tegra3 PCIE clocks
Original-Change-Id: Ief1f80913e1d103aedfa600bc23d1050d09c228f
Reviewed-on: http://git-master/r/18991 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I4362da1226e2970d3598cb5149208fd8c415fe62
Scott Williams [Wed, 9 Feb 2011 22:05:31 +0000 (14:05 -0800)]
arm: tegra: Save CPU_SOFTRST_CTRL reg on suspend
Tegra3 CPU_SOFTRST_CTRL needs to be saved/restored on suspend/resume.
Original-Change-Id: I9aa5953174ed111d8b14c1a69b71eb2f20b873cf
Reviewed-on: http://git-master/r/18985 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: If8e12e99f6029b1fefd80bb61b183f196a244060
Alex Frid [Sat, 5 Feb 2011 09:11:13 +0000 (01:11 -0800)]
ARM: tegra: Add auto-hotplug support for Tegra3
Initial implementation of Tegra3 quad core CPU management. Add closed
control loop on top of cpufreq DFS. Target frequency range is bounded
by Fmax(Vnominal) for low power cluster - currently set to 456MHz, and
Fmax(Vminimum) for high power cluster - currently set to 356MHz.
When CPU frequency is scaled below the target range, slave high power
CPUs are gradually brought down and eventually CPU is switched to the
low power cluster.
When CPU frequency is scaled above the target range, CPU is switched
to the high power cluster and slave high power CPUs are gradually
brought up.
The auto hotplug support is disabled on boot. It can be explicitly
enabled via sysfs interface.
Original-Change-Id: Ie0e5cf1f334d9c53932db05950cfcf5addd271d7
Reviewed-on: http://git-master/r/18500 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I86152069aa2bed73e0148a4bcab897811e1a5827
Alex Frid [Sat, 5 Feb 2011 05:41:50 +0000 (21:41 -0800)]
ARM: tegra: Shorten cluster switch timing reports
Original-Change-Id: I9e0744eb937223062e0582900fd0fb33a3ae1707
Reviewed-on: http://git-master/r/18468 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I40995652cb88c643b2e8ce5e7af707bbe7d9bfed
Scott Williams [Tue, 1 Feb 2011 20:52:39 +0000 (12:52 -0800)]
arm: tegra: Add run-time cluster switch debug control
Allow run-time control of cluster switch debug messages
so they can be enabled for debuggability and disabled for
performance measurement.
Original-Change-Id: Id2bd85d6a9d3a57430a20d93b51ce5b59fe53c71
Reviewed-on: http://git-master/r/17927 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ia57424eee01276d82af7aab37d2f3d0525acc379
Alex Frid [Wed, 2 Feb 2011 04:46:21 +0000 (20:46 -0800)]
ARM: tegra: cpufreq: Add Tegra3 cpufreq table
Add Tegra3 cpufreq table and table selection interface. CPU scaling
is still disabled.
Original-Change-Id: I5a446cabe27dd89a67fdbeedf1118b71578088c3
Reviewed-on: http://git-master/r/17985 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I6d8856741c02d40ea8b0493545cbceffb63320b1
Scott Williams [Tue, 1 Feb 2011 03:56:16 +0000 (19:56 -0800)]
arm: tegra: Instrument cluster switch transitions
Original-Change-Id: I1526de69a1224f42ce3ff11ba1b6fa949c2f13a5
Reviewed-on: http://git-master/r/17787 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I43caec7348d970dc076f27cc2bb4b6ded234a38c
Alex Frid [Mon, 31 Jan 2011 18:07:57 +0000 (10:07 -0800)]
ARM: tegra: clock: Raise Tegra3 AVP frequency
Increased initialization frequency for AVP/SCLK clock to maximum for
Tegra3 platforms.
Original-Change-Id: I6cc8c47c0e830af740e1a9323004513729d4e7ab
Reviewed-on: http://git-master/r/17712 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ica65140e11770749cbce9a380feb0a46f192ed92
Alex Frid [Tue, 1 Feb 2011 04:52:05 +0000 (20:52 -0800)]
ARM: tegra: clock: Add DCCON support for Tegra3 PLLM
Original-Change-Id: Ic66ca456e1eef6b3775ca79c23220d1fc436cd76
Reviewed-on: http://git-master/r/17834 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ibd8b119d13d748f186f66947822f6f1b9898f351
Alex Frid [Tue, 1 Feb 2011 02:53:45 +0000 (18:53 -0800)]
ARM: tegra: clock: Add Tegra3 DSIB mux support
Original-Change-Id: Ifd463670e828adb8429b5408c9c0f0957706d717
Reviewed-on: http://git-master/r/17820 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I82837a72c05cfe70ead2f222933a0ed05defdbad
Laxman Dewangan [Mon, 31 Jan 2011 09:29:07 +0000 (14:59 +0530)]
arm: config: tegra: cardhu: config for Verbier E1187
Adding config variables for the Verbier E1187 configuration.
By default cardhu will be build for E1198.
The cardhu can be build for E1187 by saying config variable
CONFIG_TEGRA_VERBIER_E1187 to yes.
Alex Frid [Sun, 30 Jan 2011 10:12:39 +0000 (02:12 -0800)]
ARM: tegra: clock: Increased Tegar3 maximum limits
Increased Tegar3 maximum limits for AVP, MPE, NAND, NOR,
and SDMMC clocks.
Original-Change-Id: I40dc3bb7819103bca527b37b7bcb75656eb384dc
Reviewed-on: http://git-master/r/17617 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ifde905c87d3fd468f405f37ef9302a4872da7f6e
Original-Change-Id: I702957b20bd26e0bede675e119bedd3312d9eec6
Reviewed-on: http://git-master/r/13696 Tested-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Iff0642ac6bc02a3d4710ddf524c46781549a7839
Original-Change-Id: I2437268b2916d11b1ea9564a06333d8e037a5bc1
Reviewed-on: http://git-master/r/17610 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I49d5248d120233d175a090c27250a32c43ace140
Original-Change-Id: I6e6316b9817c5c9f53733745cf3e741ed24d04e8
Reviewed-on: http://git-master/r/17609 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Idbd91768c5d8ac24f0a5aabcdac1eecb635c2d7c
Alex Frid [Sun, 30 Jan 2011 02:01:55 +0000 (18:01 -0800)]
ARM: tegra: clock: Add Tegra3 main clock dividers
Original-Change-Id: I4d2b527bc5ef457f7c873aff4a974d248e1aa21e
Reviewed-on: http://git-master/r/17608 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Icc875c8e12e6ed654c8adb175cdf2b55bae7621e
Alex Frid [Sat, 29 Jan 2011 04:36:54 +0000 (20:36 -0800)]
ARM: tegra: clock: Re-factor peripheral mux support
Original-Change-Id: I8201a2439cdbddb78eee73f067cac1d23d3dc5b5
Reviewed-on: http://git-master/r/17607 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I00dc6ed228b8686da0a6015cea0f91b6e288c62f
Pavan Kunapuli [Sat, 29 Jan 2011 03:17:33 +0000 (19:17 -0800)]
sdhci-tegra:Enabling LVL2_CLK_OVR for sdmmc1
Enabling LVL2 CLK OVR bit for sdmmc1.
Disabling cd and wp gpios for sdmmc1.
Enabling vddio_sdmmc1 using regulator and
setting the voltage to 3.3V.
Using clk_m for sdmmc1.
Original-Change-Id: Id38e2357c5cafe103b7607ef5adb4e7e9bc228d4
Reviewed-on: http://git-master/r/17212 Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I89e4ab5b4cc501cf02eb800bc3acb49b0dba2519
Move audio sync clock sources to the root of clock tree. This removes
possible circular dependencies in the clock graph, and let the sync
clock owner to set input rate directly.
vdumpa [Wed, 17 Nov 2010 23:57:13 +0000 (15:57 -0800)]
tegra:arm: Set inner-WBWA/outer-WBNWA cacheability attributes
Change the cacheability attributes in the normal memory remap
register (NMRR) to inner write-back write-allocate/outer write-back
no-write-allocate to improve L2 cache performance.
Bug 728231
Bug 751146
Original-Change-Id: I992dd20b3cec3b0141ae114d5ae278122be0212d
Reviewed-on: http://git-master/r/11077 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Tested-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-on: http://git-master/r/17475 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0de3100975c592fe4a18780c2b0eb2c5d12258d7
Original-Change-Id: Ic930ffaf2d441466bc03be0b8f97582dc750f3d7
Reviewed-on: http://git-master/r/17372 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Andrew Howe <ahowe@nvidia.com> Tested-by: Andrew Howe <ahowe@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I9cebd7e83cdc28be5c4f7c458e71f5376b6eb84a
Pavan Kunapuli [Wed, 26 Jan 2011 19:14:53 +0000 (11:14 -0800)]
arm: tegra: sdhci: Do not disable sdmmc4 clock
Do not switch off sdmmc4 clock. Also, removed ddr
mode temporarily from linux mmc driver.
Programming tap_delays and internal clock.
Original-Change-Id: I830bf5e94ccd47e154c5ef9909e8bff1ff7754c0
Reviewed-on: http://git-master/r/17070 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ic1cff8dd85229fe903206f1dc9a967d600ba88c1
Scott Williams [Thu, 20 Jan 2011 23:17:19 +0000 (15:17 -0800)]
arm: tegra: Do not write read-only bits
AXI_FLUSH_DONE (bit 31) of CLK_RESET_CLK_MASK_ARM is a read-only
status bit. Do not write it.
Reviewed-on: http://git-master/r/16456 Reviewed-by: Jin Qian <jqian@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
(cherry picked from commit 34add7dc2e7398763fe36db7f4e79657cdd6e95e)
Original-Change-Id: Ia480e1b3113f7690ce6431f337b0c9354566d2ef
Reviewed-on: http://git-master/r/16936 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ic3ae3fa92e563f27a7b0bf5fe1d4c14a9d953ed6
Alex Frid [Tue, 25 Jan 2011 06:12:28 +0000 (22:12 -0800)]
ARM: tegra: clock: Prevent parent over-clocking
Pre-set clock rate when changing parent to avoid parent over-clocking
during clock initialization from common/board specific tables. Drivers
however, may still hit over-clocking error.
Original-Change-Id: Ib101d85e90ab4c1194ac98680c930eebd8c56b76
Reviewed-on: http://git-master/r/16877 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I307e7eb507d885c381087812d262d56338aab861
Alex Frid [Tue, 25 Jan 2011 04:33:16 +0000 (20:33 -0800)]
ARM: tegra: clock: Add check for parent over-clocking
Fail clk_set_parent() interface if switching the clock parent will set
the rate above maximum limit.
Original-Change-Id: I47c0798dafe5f8f497dcacfcd23f6957244cdb0a
Reviewed-on: http://git-master/r/16876 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ie5fef027411096a465ae5aa84fe84a08a769a613
Original-Change-Id: Iceb4c1188808ec6cd2f41b6d39dd18356f1ed24d
Reviewed-on: http://git-master/r/16806 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I80710f1d21d1b65f7837ec601d3b70962417b2a9
Alex Frid [Sun, 23 Jan 2011 02:40:45 +0000 (18:40 -0800)]
ARM: tegra: clock: Add Tegra3 PLLE support
Original-Change-Id: Iba29ff515fd850cd0f736d5ef693877e85fb0c5c
Reviewed-on: http://git-master/r/16660 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8d6efae37847fcbda12290b6cd5d61e6a61c2777
Alex Frid [Sun, 23 Jan 2011 04:07:49 +0000 (20:07 -0800)]
ARM: tegra: Add Tegra3 speedo stubs
Original-Change-Id: I05b9b8014062a28a69407c08fc630a280214315e
Reviewed-on: http://git-master/r/16661 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I190f04798473bf4452d00561cae96e45085c3dc0
Alex Frid [Sun, 23 Jan 2011 03:08:54 +0000 (19:08 -0800)]
ARM: tegra: clock: Propagate errors in debugfs
Original-Change-Id: I7d7f4f49cc1e41707032467197d53967d3ecaf06
Reviewed-on: http://git-master/r/16659 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I9e04b2833ef12466664cf6f6c2666d440600db08
Alex Frid [Sun, 23 Jan 2011 01:05:01 +0000 (17:05 -0800)]
ARM: tegra: clock: Add clock state debugfs control
Original-Change-Id: I2a16c36c8ee414a1f046eda2f3bdb9c1d71caf8b
Reviewed-on: http://git-master/r/16657 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Icc4b526f44697bd788d83434f6e9a62de005b09c
Hiro Sugawara [Wed, 19 Jan 2011 21:57:30 +0000 (13:57 -0800)]
[arm:tegra] Adding MC_DECERR interrupt handler
Adding MC_DECERR interrupt handler ported from Froyo.
This addition will not gracefully terminate a failing DMA transfer.
The handler does noting but simply reporting the error status with prink,
and the clinet software will likely hang forever waiting for a non-
completing DMA transfer. But it is still useful for debugging.
Original-Change-Id: I7b19c70d8cbb62be9ab3f955bf19c707c1e5045d
Reviewed-on: http://git-master/r/16590 Tested-by: Hiro Sugawara <hsugawara@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ibdcfe63d56d22e39d8c5398ff50eb663bd0d82f3
Yen Lin [Thu, 13 Jan 2011 20:37:10 +0000 (12:37 -0800)]
arm: tegra: Add SATA support
Original-Change-Id: I18c63f1c69e155ddc1cec1718af9684d861815b7
Reviewed-on: http://git-master/r/15863 Tested-by: Yen Lin <yelin@nvidia.com> Reviewed-by: Rhyland Klein <rklein@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/16485
Original-Change-Id: I6afa5a097b4fc7d6c45614107118458da0d9d888
Alex Frid [Wed, 19 Jan 2011 05:40:48 +0000 (21:40 -0800)]
ARM: tegra: clock: Fixed Tegra3 audio pll and board setting
Original-Change-Id: I3fd6622c4f4ff43b8ab03d552dd488a51d2cfdf4
Reviewed-on: http://git-master/r/16209 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I1279516ce261882d9e390cb6adbdb9bcffac0f94
Alex Frid [Wed, 19 Jan 2011 04:29:04 +0000 (20:29 -0800)]
ARM: tegra: Add Tegra3 kfuse clock
Original-Change-Id: I4969fe983dba767bfcff11d6dfc9187c3545568a
Reviewed-on: http://git-master/r/16207 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I79e6b93cb9c57e1aa5033ab1e4bc487f144bd982
Scott Williams [Sat, 15 Jan 2011 00:19:23 +0000 (16:19 -0800)]
arm: tegra: Enable Tegra3 APB DMA channels 16-31
Original-Change-Id: Ia098e22789f4817e14ac34de01f8d990b4b4d29b
Reviewed-on: http://git-master/r/15975 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: If9677ac2190d8d2266ee40d011f5841e97838522
Scott Williams [Fri, 7 Jan 2011 18:48:48 +0000 (10:48 -0800)]
arm: tegra: Enable Tegra3 cluster control
Original-Change-Id: I162c061f8a1851394d6390bc1234910cdf0972b3
Reviewed-on: http://git-master/r/15269 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I0dc20ab81db7456c0faf3a81984f2821e7d565ae
Scott Williams [Thu, 13 Jan 2011 22:30:20 +0000 (14:30 -0800)]
arm: tegra: Fix reserved memory area reporting
Also fixes:
- possible unitialized global variable usage.
- corruption of the LP0 code segment if there is no bootloader framebuffer.
Original-Change-Id: Ic163be339dad8b9bb3c3ffe509ccfd8ea33c8299
Reviewed-on: http://git-master/r/15875 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ibc6838c412caf0e2f452a4737ec36ad67434f636
Original-Change-Id: I5b39fd8ea2284828e9cb3b5ce4330728e20b1662
Reviewed-on: http://git-master/r/15736 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I71ecd7c4426e7e82500f12d57b85a6bcc417065c
Dara Ramesh [Wed, 12 Jan 2011 04:15:54 +0000 (09:45 +0530)]
[ARM/tegra] HDA Driver support
Adding HDA audio driver support for Tegra3
Original-Change-Id: I81a76a54f6ce5390051d96dbeadf447682f9ff0e
Reviewed-on: http://git-master/r/15405 Tested-by: Dara Ramesh <dramesh@nvidia.com> Reviewed-by: Dara Ramesh <dramesh@nvidia.com> Reviewed-by: Scott Peterson <speterson@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I8525ef7317606b895818e73ec92ca174dddf609e
[ARM] tegra: Fixing the details of config TEGRA_FPGA_PLATFORM
Adding the details like default value and help for the config
variable TEGRA_FPGA_PLATFORM in Kconfig file.
Making cardhu as depends on Tegra3 soc architecture.
Original-Change-Id: Ib395ffa09c44a8924fdc6bf514132d98acec7bc8
Reviewed-on: http://git-master/r/15408 Reviewed-by: Scott Williams <scwilliams@nvidia.com> Tested-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ic797d7f5fbcec7c7763f8fe4b694afb385e3ad4c
Scott Williams [Tue, 11 Jan 2011 18:50:52 +0000 (10:50 -0800)]
arm: tegra: Fix hardcoded frame buffer addresses
Dynamically obtain the carveout and framebuffer addresses.
Bug 769986
Original-Change-Id: I9b8eeb710e5198ab9ae4e7e6c7095cfd23209e66
Reviewed-on: http://git-master/r/15534 Tested-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ia6f68817b65281bd5da4f8774476a947fd970950
Alex Frid [Tue, 11 Jan 2011 07:26:40 +0000 (23:26 -0800)]
ARM: tegra: clock: Add clock change delay
Added 2us clock change delay to peripheral and pll divider clock
operations.
Original-Change-Id: Ib2f138d4be89542c46fd7ad24bd57ad75baf2548
Reviewed-on: http://git-master/r/15542 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Ieb7f88404ab3f42612502a58666f70c469e40056
Alex Frid [Tue, 11 Jan 2011 06:10:43 +0000 (22:10 -0800)]
ARM: tegra: clock: Fix set parent/rate corner cases
- Prevented division by 0 when 0 rate is requested
- Prevented attempt to set parent for clocks with no mux (otherwise
write to CAR register at offset 0 may affect WDT operations)
Original-Change-Id: I1beb8850cf96198422b1f07d807be18a1dce3aaf
Reviewed-on: http://git-master/r/15541 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: Icfda0e3919c238895e613f97c9e982fbbd4055b0
Alex Frid [Tue, 11 Jan 2011 05:13:47 +0000 (21:13 -0800)]
ARM: tegra: clock: Add missed tegra clocks to Tegra3
Added to Tegra3 kbc, bsev and duplicate vde clocks missed in merge.
Original-Change-Id: I30df934c933a88186f49c44d538ca35d1e1835b5
Reviewed-on: http://git-master/r/15540 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I362543a1c7215131836ca5b9f5fdb37549db376a
Alex Frid [Sun, 9 Jan 2011 05:00:54 +0000 (21:00 -0800)]
ARM: tegra: clock: Add Tegra3 EMC shared bus
Original-Change-Id: I0c8ed371abb9f2172d42504527d7585e6bef6c94
Reviewed-on: http://git-master/r/15349 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I78576a1ac1bfbb89a59ca428d94a7a99edde6777