ARM: Tegra: dvfs: Proc array indep of new T30 char SKUs
Diwakar Tundlam [Thu, 23 Jun 2011 04:17:19 +0000 (21:17 -0700)]
- Make process_ids array independent of SKU to avoid confusion when
  detecting SKU, speedo_id and parsing process_id.
- Added SKU definitions for characterization SKUs of AP30, T30, T30S

Bug 855816

Original-Change-Id: I925d54ab6d35e8af038cbfe84ef4b4c076cd596d
Reviewed-on: http://git-master/r/43096
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: R832f8fb1a34ab700af0c6389fbe5307f334cc54c

arch/arm/mach-tegra/fuse.c
arch/arm/mach-tegra/tegra3_speedo.c

index 292f561..d779f5c 100644 (file)
@@ -110,7 +110,8 @@ void tegra_init_fuse(void)
        writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
        tegra_init_speedo_data();
 
-       pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
+       pr_info("Tegra Revision: %s "
+               "SKU: 0x%x CPU Process: %d Core Process: %d\n",
                tegra_get_revision_name(), tegra_sku_id(),
                tegra_cpu_process_id(), tegra_core_process_id());
 }
index 3c4e70d..b34ded2 100644 (file)
 /* Maximum speedo levels for each core process corner */
 static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
 /* proc_id 0 */
-       {180}, /* soc_speedo_id 0 */
-       {183}, /* soc_speedo_id 1 */
-       {197}, /* soc_speedo_id 2 */
+       {180}, /* threshold_index 0: soc_speedo_id 0: any A01 */
+
+/* T30 family */
+       {183}, /* threshold_index 1: soc_speedo_id 1: AP30 */
+       {197}, /* threshold_index 2: soc_speedo_id 2: T30  */
+       {197}, /* threshold_index 3: soc_speedo_id 2: T30S */
+
+/* Characterization SKUs */
+       {170}, /* threshold_index 4: soc_speedo_id 1: AP30 char */
+       {190}, /* threshold_index 5: soc_speedo_id 2: T30  char */
+       {190}, /* threshold_index 6: soc_speedo_id 2: T30S char */
 };
 
 /* Maximum speedo levels for each CPU process corner */
 static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
 /* proc_id 0    1    2    3 */
-       {306, 338, 360, 376}, /* cpu_speedo_id 0 */
-       {306, 338, 360, 376}, /* cpu_speedo_id 1 */
-       {338, 338, 360, 376}, /* cpu_speedo_id 2 */
-       {338, 338, 360, 376}, /* cpu_speedo_id 3 */
+       {306, 338, 360, 376}, /* threshold_index 0: cpu_speedo_id 0: any A01 */
+
+/* T30 family */
+       {306, 338, 360, 376}, /* threshold_index 1: cpu_speedo_id 1: AP30 */
+       {338, 338, 360, 376}, /* threshold_index 2: cpu_speedo_id 2: T30  */
+       {338, 338, 360, 376}, /* threshold_index 3: cpu_speedo_id 3: T30S */
+
+/* Characterization SKUs */
+       {295, 326, 348, 364}, /* threshold_index 4: cpu_speedo_id 1: AP30char */
+       {326, 326, 348, 364}, /* threshold_index 5: cpu_speedo_id 2: T30char  */
+       {326, 326, 348, 364}, /* threshold_index 6: cpu_speedo_id 3: T30Schar */
 };
 
+/*
+ * Common speedo_value array threshold index for both core_process_speedos and
+ * cpu_process_speedos arrays. Make sure these two arrays are always in synch.
+ */
+static int threshold_index;
+
 static int cpu_process_id;
 static int core_process_id;
 static int cpu_speedo_id;
@@ -71,48 +92,86 @@ static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
 static void rev_sku_to_speedo_ids(int rev, int sku)
 {
        switch (rev) {
-       case TEGRA_REVISION_A01:
+       case TEGRA_REVISION_A01: /* any A01 */
                cpu_speedo_id = 0;
                soc_speedo_id = 0;
+               threshold_index = 0;
                break;
+
        case TEGRA_REVISION_A02:
        case TEGRA_REVISION_A03:
                switch (sku) {
                case 0x87: /* AP30 */
                        cpu_speedo_id = 1;
                        soc_speedo_id = 1;
+                       threshold_index = 1;
                        break;
+
                case 0x81: /* T30 */
+                       switch (package_id) {
+                       case 1: /* MID => T30 */
+                               cpu_speedo_id = 2;
+                               soc_speedo_id = 2;
+                               threshold_index = 2;
+                               break;
+                       default:
+                               pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n",
+                                      package_id);
+                               BUG();
+                               break;
+                       }
+                       break;
+
+               case 0x83: /* T30S */
+                       cpu_speedo_id = 3;
+                       soc_speedo_id = 2;
+                       threshold_index = 3;
+                       break;
+
+/* Characterization SKUs */
+               case 0x08: /* AP30 char */
+                       cpu_speedo_id = 1;
+                       soc_speedo_id = 1;
+                       threshold_index = 4;
+                       break;
+               case 0x02: /* T30 char */
                        cpu_speedo_id = 2;
                        soc_speedo_id = 2;
+                       threshold_index = 5;
                        break;
-               case 0x83: /* T30S */
+               case 0x04: /* T30S char */
                        cpu_speedo_id = 3;
                        soc_speedo_id = 2;
+                       threshold_index = 6;
                        break;
-               case 0:    /* ENG - check PKG_SKU */
-                       pr_info("Tegra3 ENG SKU: Checking pkg info\n");
+
+               case 0:    /* ENG - check package_id */
+                       pr_info("Tegra3 ENG SKU: Checking package_id\n");
                        switch (package_id) {
                        case 1: /* MID => assume T30 */
                                cpu_speedo_id = 2;
                                soc_speedo_id = 2;
+                               threshold_index = 2;
                                break;
                        case 2: /* DSC => assume T30S */
                                cpu_speedo_id = 3;
                                soc_speedo_id = 2;
+                               threshold_index = 3;
                                break;
                        default:
-                               pr_err("Tegra3 Rev-A02: Reserved pkg info %d\n",
+                               pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n",
                                       package_id);
                                BUG();
                                break;
                        }
                        break;
+
                default:
                        /* FIXME: replace with BUG() when all SKU's valid */
                        pr_err("Tegra3 Rev-A02: Unknown SKU %d\n", sku);
                        cpu_speedo_id = 0;
                        soc_speedo_id = 0;
+                       threshold_index = 0;
                        break;
                }
                break;
@@ -130,16 +189,20 @@ void tegra_init_speedo_data(void)
        /* Package info: 4 bits - 0,3:reserved 1:MID 2:DSC */
        package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
 
+       /* Arrays must be of equal size - each index corresponds to a SKU */
+       BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
+              ARRAY_SIZE(core_process_speedos));
+
        rev_sku_to_speedo_ids(tegra_get_revision(), tegra_sku_id());
-       BUG_ON(cpu_speedo_id >= ARRAY_SIZE(cpu_process_speedos));
-       BUG_ON(soc_speedo_id >= ARRAY_SIZE(core_process_speedos));
+       BUG_ON(threshold_index >= ARRAY_SIZE(cpu_process_speedos));
 
        fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
        pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
        pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
 
        for (iv = 0; iv < CPU_PROCESS_CORNERS_NUM; iv++) {
-               if (cpu_speedo_val < cpu_process_speedos[cpu_speedo_id][iv]) {
+               if (cpu_speedo_val <
+                   cpu_process_speedos[threshold_index][iv]) {
                        break;
                }
        }
@@ -158,7 +221,8 @@ void tegra_init_speedo_data(void)
        }
 
        for (iv = 0; iv < CORE_PROCESS_CORNERS_NUM; iv++) {
-               if (core_speedo_val < core_process_speedos[soc_speedo_id][iv]) {
+               if (core_speedo_val <
+                   core_process_speedos[threshold_index][iv]) {
                        break;
                }
        }