[ARM] 5460/1: Orion: reduce namespace pollution
Nicolas Pitre [Wed, 22 Apr 2009 19:08:17 +0000 (20:08 +0100)]
Symbols like SOFT_RESET are way too generic to be exported at large.
To avoid this, let's move the mbus bridge register defines into a
separate file and include it where needed.  This affects mach-kirkwood,
mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all
share code in plat-orion which relies on those defines.

Some other defines have been moved to narrower scopes, or simply deleted
when they had no user.

This fixes compilation problem with mpt2sas on the above listed
platforms.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

29 files changed:
arch/arm/mach-kirkwood/common.c
arch/arm/mach-kirkwood/include/mach/bridge-regs.h [new file with mode: 0644]
arch/arm/mach-kirkwood/include/mach/debug-macro.S
arch/arm/mach-kirkwood/include/mach/entry-macro.S
arch/arm/mach-kirkwood/include/mach/kirkwood.h
arch/arm/mach-kirkwood/include/mach/system.h
arch/arm/mach-kirkwood/irq.c
arch/arm/mach-loki/addr-map.c
arch/arm/mach-loki/include/mach/bridge-regs.h [new file with mode: 0644]
arch/arm/mach-loki/include/mach/entry-macro.S
arch/arm/mach-loki/include/mach/loki.h
arch/arm/mach-loki/include/mach/system.h
arch/arm/mach-loki/irq.c
arch/arm/mach-mv78xx0/common.c
arch/arm/mach-mv78xx0/include/mach/bridge-regs.h [new file with mode: 0644]
arch/arm/mach-mv78xx0/include/mach/entry-macro.S
arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
arch/arm/mach-mv78xx0/include/mach/system.h
arch/arm/mach-mv78xx0/irq.c
arch/arm/mach-orion5x/addr-map.c
arch/arm/mach-orion5x/include/mach/bridge-regs.h [new file with mode: 0644]
arch/arm/mach-orion5x/include/mach/entry-macro.S
arch/arm/mach-orion5x/include/mach/orion5x.h
arch/arm/mach-orion5x/include/mach/system.h
arch/arm/mach-orion5x/irq.c
arch/arm/mach-orion5x/mss2-setup.c
arch/arm/mach-orion5x/pci.c
arch/arm/plat-orion/time.c
drivers/watchdog/orion5x_wdt.c

index 16dc9ea..eeb0024 100644 (file)
@@ -23,6 +23,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
 #include <plat/ehci-orion.h>
 #include <plat/mvsdio.h>
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
new file mode 100644 (file)
index 0000000..4f7029f
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+ *
+ * Mbus-L to Mbus Bridge Registers
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+
+#include <mach/kirkwood.h>
+
+#define CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_RESET              0x00000002
+
+#define RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define SOFT_RESET_OUT_EN      0x00000004
+
+#define SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define SOFT_RESET             0x00000001
+
+#define BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define BRIDGE_INT_TIMER0      0x0002
+#define BRIDGE_INT_TIMER1      0x0004
+#define BRIDGE_INT_TIMER1_CLR  (~0x0004)
+
+#define IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_CAUSE_LOW_OFF      0x0000
+#define IRQ_MASK_LOW_OFF       0x0004
+#define IRQ_CAUSE_HIGH_OFF     0x0010
+#define IRQ_MASK_HIGH_OFF      0x0014
+
+#define TIMER_VIRT_BASE                (BRIDGE_VIRT_BASE | 0x0300)
+
+#define L2_CONFIG_REG          (BRIDGE_VIRT_BASE | 0x0128)
+#define L2_WRITETHROUGH                0x00000010
+
+#endif
index c0cc5b5..a4a55c1 100644 (file)
@@ -6,7 +6,7 @@
  * published by the Free Software Foundation.
 */
 
-#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
 
        .macro  addruart,rx
        mrc     p15, 0, \rx, c1, c0
index 83e0cba..8939d36 100644 (file)
@@ -8,7 +8,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
 
        .macro  disable_fiq
        .endm
index 38c9868..b3e1395 100644 (file)
 #define KIRKWOOD_PCIE_MEM_SIZE         SZ_128M
 
 /*
- * MBUS bridge registers.
- */
-#define BRIDGE_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
-#define  CPU_CONTROL           (BRIDGE_VIRT_BASE | 0x0104)
-#define   CPU_RESET            0x00000002
-#define  RSTOUTn_MASK          (BRIDGE_VIRT_BASE | 0x0108)
-#define   SOFT_RESET_OUT_EN    0x00000004
-#define  SYSTEM_SOFT_RESET     (BRIDGE_VIRT_BASE | 0x010c)
-#define   SOFT_RESET           0x00000001
-#define  BRIDGE_CAUSE          (BRIDGE_VIRT_BASE | 0x0110)
-#define  BRIDGE_MASK           (BRIDGE_VIRT_BASE | 0x0114)
-#define   BRIDGE_INT_TIMER0    0x0002
-#define   BRIDGE_INT_TIMER1    0x0004
-#define   BRIDGE_INT_TIMER1_CLR        (~0x0004)
-#define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
-#define   IRQ_CAUSE_LOW_OFF    0x0000
-#define   IRQ_MASK_LOW_OFF     0x0004
-#define   IRQ_CAUSE_HIGH_OFF   0x0010
-#define   IRQ_MASK_HIGH_OFF    0x0014
-#define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
-#define  L2_CONFIG_REG         (BRIDGE_VIRT_BASE | 0x0128)
-#define   L2_WRITETHROUGH      0x00000010
-
-/*
- * Supported devices and revisions.
- */
-#define MV88F6281_DEV_ID       0x6281
-#define MV88F6281_REV_Z0       0
-#define MV88F6281_REV_A0       2
-
-#define MV88F6192_DEV_ID       0x6192
-#define MV88F6192_REV_Z0       0
-#define MV88F6192_REV_A0       2
-
-#define MV88F6180_DEV_ID       0x6180
-#define MV88F6180_REV_A0       2
-
-/*
  * Register Map
  */
 #define DDR_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
@@ -99,6 +61,8 @@
 #define  UART1_PHYS_BASE       (DEV_BUS_PHYS_BASE | 0x2100)
 #define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2100)
 
+#define BRIDGE_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
+
 #define PCIE_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 
 #define USB_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
 #define SDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
 
+/*
+ * Supported devices and revisions.
+ */
+#define MV88F6281_DEV_ID       0x6281
+#define MV88F6281_REV_Z0       0
+#define MV88F6281_REV_A0       2
+
+#define MV88F6192_DEV_ID       0x6192
+#define MV88F6192_REV_Z0       0
+#define MV88F6192_REV_A0       2
+
+#define MV88F6180_DEV_ID       0x6180
+#define MV88F6180_REV_A0       2
 
 #endif
index 23a1914..7568e95 100644 (file)
@@ -9,8 +9,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <mach/hardware.h>
-#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
 
 static inline void arch_idle(void)
 {
index 06083b2..28020ab 100644 (file)
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <mach/bridge-regs.h>
 #include <plat/irq.h>
 #include <asm/gpio.h>
 #include "common.h"
index 0332d8f..b9537c9 100644 (file)
@@ -38,6 +38,7 @@
 /*
  * CPU Address Decode Windows registers
  */
+#define BRIDGE_REG(x)          (BRIDGE_VIRT_BASE | (x))
 #define CPU_WIN_CTRL(n)                BRIDGE_REG(0x000 | ((n) << 4))
 #define CPU_WIN_BASE(n)                BRIDGE_REG(0x004 | ((n) << 4))
 #define CPU_WIN_REMAP_LO(n)    BRIDGE_REG(0x008 | ((n) << 4))
diff --git a/arch/arm/mach-loki/include/mach/bridge-regs.h b/arch/arm/mach-loki/include/mach/bridge-regs.h
new file mode 100644 (file)
index 0000000..a3fabf7
--- /dev/null
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-loki/include/mach/bridge-regs.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+
+#include <mach/loki.h>
+
+#define RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define SOFT_RESET_OUT_EN      0x00000004
+
+#define SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define SOFT_RESET             0x00000001
+
+#define BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+
+#define BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define BRIDGE_INT_TIMER0      0x0002
+#define BRIDGE_INT_TIMER1      0x0004
+#define BRIDGE_INT_TIMER1_CLR  0x0004
+
+#define IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_CAUSE_OFF          0x0000
+#define IRQ_MASK_OFF           0x0004
+
+#define TIMER_VIRT_BASE                (BRIDGE_VIRT_BASE | 0x0300)
+
+#endif
index 332af38..bc917ed 100644 (file)
@@ -8,7 +8,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <mach/loki.h>
+#include <mach/bridge-regs.h>
 
        .macro  disable_fiq
        .endm
index c00af6b..bfca7c2 100644 (file)
 #define  UART1_VIRT_BASE       (DEV_BUS_VIRT_BASE | 0x2100)
 
 #define BRIDGE_VIRT_BASE       (LOKI_REGS_VIRT_BASE | 0x20000)
-#define  BRIDGE_REG(x)         (BRIDGE_VIRT_BASE | (x))
-#define  RSTOUTn_MASK          (BRIDGE_VIRT_BASE | 0x0108)
-#define   SOFT_RESET_OUT_EN    0x00000004
-#define  SYSTEM_SOFT_RESET     (BRIDGE_VIRT_BASE | 0x010c)
-#define   SOFT_RESET           0x00000001
-#define  BRIDGE_CAUSE          (BRIDGE_VIRT_BASE | 0x0110)
-#define  BRIDGE_MASK           (BRIDGE_VIRT_BASE | 0x0114)
-#define   BRIDGE_INT_TIMER0    0x0002
-#define   BRIDGE_INT_TIMER1    0x0004
-#define   BRIDGE_INT_TIMER1_CLR        0x0004
-#define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
-#define   IRQ_CAUSE_OFF                0x0000
-#define   IRQ_MASK_OFF         0x0004
-#define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
 
 #define PCIE0_VIRT_BASE                (LOKI_REGS_VIRT_BASE | 0x30000)
 
index c1de36f..7189519 100644 (file)
@@ -9,8 +9,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <mach/hardware.h>
-#include <mach/loki.h>
+#include <mach/bridge-regs.h>
 
 static inline void arch_idle(void)
 {
index e1f9733..76b211b 100644 (file)
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/io.h>
+#include <mach/bridge-regs.h>
 #include <plat/irq.h>
 #include "common.h"
 
index a575daa..9ba5950 100644 (file)
@@ -20,6 +20,7 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/mv78xx0.h>
+#include <mach/bridge-regs.h>
 #include <plat/cache-feroceon-l2.h>
 #include <plat/ehci-orion.h>
 #include <plat/orion_nand.h>
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
new file mode 100644 (file)
index 0000000..2d14c4f
--- /dev/null
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+
+#include <mach/mv78xx0.h>
+
+#define CPU_CONTROL            (BRIDGE_VIRT_BASE | 0x0104)
+#define L2_WRITETHROUGH                0x00020000
+
+#define RSTOUTn_MASK           (BRIDGE_VIRT_BASE | 0x0108)
+#define SOFT_RESET_OUT_EN      0x00000004
+
+#define SYSTEM_SOFT_RESET      (BRIDGE_VIRT_BASE | 0x010c)
+#define SOFT_RESET             0x00000001
+
+#define BRIDGE_CAUSE           (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_MASK            (BRIDGE_VIRT_BASE | 0x0114)
+#define BRIDGE_INT_TIMER0      0x0002
+#define BRIDGE_INT_TIMER1      0x0004
+#define BRIDGE_INT_TIMER1_CLR  (~0x0004)
+
+#define IRQ_VIRT_BASE          (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_CAUSE_ERR_OFF      0x0000
+#define IRQ_CAUSE_LOW_OFF      0x0004
+#define IRQ_CAUSE_HIGH_OFF     0x0008
+#define IRQ_MASK_ERR_OFF       0x000c
+#define IRQ_MASK_LOW_OFF       0x0010
+#define IRQ_MASK_HIGH_OFF      0x0014
+
+#define TIMER_VIRT_BASE                (BRIDGE_VIRT_BASE | 0x0300)
+
+#endif
index fbfb269..66ae2d2 100644 (file)
@@ -8,7 +8,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <mach/mv78xx0.h>
+#include <mach/bridge-regs.h>
 
        .macro  disable_fiq
        .endm
index 582cffc..d715b92 100644 (file)
  * Core-specific peripheral registers.
  */
 #define BRIDGE_VIRT_BASE       (MV78XX0_CORE_REGS_VIRT_BASE)
-#define  CPU_CONTROL           (BRIDGE_VIRT_BASE | 0x0104)
-#define   L2_WRITETHROUGH      0x00020000
-#define  RSTOUTn_MASK          (BRIDGE_VIRT_BASE | 0x0108)
-#define   SOFT_RESET_OUT_EN    0x00000004
-#define  SYSTEM_SOFT_RESET     (BRIDGE_VIRT_BASE | 0x010c)
-#define   SOFT_RESET           0x00000001
-#define  BRIDGE_CAUSE          (BRIDGE_VIRT_BASE | 0x0110)
-#define  BRIDGE_MASK           (BRIDGE_VIRT_BASE | 0x0114)
-#define   BRIDGE_INT_TIMER0    0x0002
-#define   BRIDGE_INT_TIMER1    0x0004
-#define   BRIDGE_INT_TIMER1_CLR        (~0x0004)
-#define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
-#define   IRQ_CAUSE_ERR_OFF    0x0000
-#define   IRQ_CAUSE_LOW_OFF    0x0004
-#define   IRQ_CAUSE_HIGH_OFF   0x0008
-#define   IRQ_MASK_ERR_OFF     0x000c
-#define   IRQ_MASK_LOW_OFF     0x0010
-#define   IRQ_MASK_HIGH_OFF    0x0014
-#define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
-
-/*
- * Supported devices and revisions.
- */
-#define MV78X00_Z0_DEV_ID      0x6381
-#define MV78X00_REV_Z0         1
-
-#define MV78100_DEV_ID         0x7810
-#define MV78100_REV_A0         1
-
-#define MV78200_DEV_ID         0x7820
-#define MV78200_REV_A0         1
 
 /*
  * Register Map
 
 #define SATA_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0xa0000)
 
+/*
+ * Supported devices and revisions.
+ */
+#define MV78X00_Z0_DEV_ID      0x6381
+#define MV78X00_REV_Z0         1
+
+#define MV78100_DEV_ID         0x7810
+#define MV78100_REV_A0         1
+
+#define MV78200_DEV_ID         0x7820
+#define MV78200_REV_A0         1
 
 #endif
index 1d6350b..66e7ce4 100644 (file)
@@ -9,8 +9,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <mach/hardware.h>
-#include <mach/mv78xx0.h>
+#include <mach/bridge-regs.h>
 
 static inline void arch_idle(void)
 {
index 30b7e4b..f289b0e 100644 (file)
@@ -13,7 +13,7 @@
 #include <linux/pci.h>
 #include <linux/irq.h>
 #include <asm/gpio.h>
-#include <mach/mv78xx0.h>
+#include <mach/bridge-regs.h>
 #include <plat/irq.h>
 #include "common.h"
 
index 719957e..c14d121 100644 (file)
 /*
  * Helpers to get DDR bank info
  */
+#define ORION5X_DDR_REG(x)     (ORION5X_DDR_VIRT_BASE | (x))
 #define DDR_BASE_CS(n)         ORION5X_DDR_REG(0x1500 + ((n) << 3))
 #define DDR_SIZE_CS(n)         ORION5X_DDR_REG(0x1504 + ((n) << 3))
 
 /*
  * CPU Address Decode Windows registers
  */
+#define ORION5X_BRIDGE_REG(x)  (ORION5X_BRIDGE_VIRT_BASE | (x))
 #define CPU_WIN_CTRL(n)                ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
 #define CPU_WIN_BASE(n)                ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
 #define CPU_WIN_REMAP_LO(n)    ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
new file mode 100644 (file)
index 0000000..be896e5
--- /dev/null
@@ -0,0 +1,41 @@
+/*
+ * arch/arm/mach-orion5x/include/mach/bridge-regs.h
+ *
+ * Orion CPU Bridge Registers
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_BRIDGE_REGS_H
+#define __ASM_ARCH_BRIDGE_REGS_H
+
+#include <mach/orion5x.h>
+
+#define CPU_CONF               (ORION5X_BRIDGE_VIRT_BASE | 0x100)
+
+#define CPU_CTRL               (ORION5X_BRIDGE_VIRT_BASE | 0x104)
+
+#define CPU_RESET_MASK         (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define WDT_RESET              0x0002
+
+#define CPU_SOFT_RESET         (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+
+#define POWER_MNG_CTRL_REG     (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
+
+#define BRIDGE_CAUSE           (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+#define WDT_INT_REQ            0x0008
+
+#define BRIDGE_MASK            (ORION5X_BRIDGE_VIRT_BASE | 0x114)
+#define BRIDGE_INT_TIMER0      0x0002
+#define BRIDGE_INT_TIMER1      0x0004
+#define BRIDGE_INT_TIMER1_CLR  (~0x0004)
+
+#define MAIN_IRQ_CAUSE         (ORION5X_BRIDGE_VIRT_BASE | 0x200)
+
+#define MAIN_IRQ_MASK          (ORION5X_BRIDGE_VIRT_BASE | 0x204)
+
+#define TIMER_VIRT_BASE                (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+
+#endif
index 4351937..d658992 100644 (file)
@@ -8,7 +8,7 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
 
        .macro  disable_fiq
        .endm
index 67bda31..377a773 100644 (file)
 #define ORION5X_PCI_MEM_SIZE           SZ_128M
 
 /*******************************************************************************
- * Supported Devices & Revisions
- ******************************************************************************/
-/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
-#define MV88F5181_DEV_ID       0x5181
-#define MV88F5181_REV_B1       3
-#define MV88F5181L_REV_A0      8
-#define MV88F5181L_REV_A1      9
-/* Orion-NAS (88F5182) */
-#define MV88F5182_DEV_ID       0x5182
-#define MV88F5182_REV_A2       2
-/* Orion-2 (88F5281) */
-#define MV88F5281_DEV_ID       0x5281
-#define MV88F5281_REV_D0       4
-#define MV88F5281_REV_D1       5
-#define MV88F5281_REV_D2       6
-/* Orion-1-90 (88F6183) */
-#define MV88F6183_DEV_ID       0x6183
-#define MV88F6183_REV_B0       3
-
-/*******************************************************************************
  * Orion Registers Map
  ******************************************************************************/
+
 #define ORION5X_DDR_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x00000)
-#define ORION5X_DDR_REG(x)             (ORION5X_DDR_VIRT_BASE | (x))
 
 #define ORION5X_DEV_BUS_PHYS_BASE      (ORION5X_REGS_PHYS_BASE | 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE      (ORION5X_REGS_VIRT_BASE | 0x10000)
 #define  UART1_VIRT_BASE               (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
 
 #define ORION5X_BRIDGE_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x20000)
-#define ORION5X_BRIDGE_REG(x)          (ORION5X_BRIDGE_VIRT_BASE | (x))
-#define  TIMER_VIRT_BASE               (ORION5X_BRIDGE_VIRT_BASE | 0x300)
 
 #define ORION5X_PCI_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x30000)
-#define ORION5X_PCI_REG(x)             (ORION5X_PCI_VIRT_BASE | (x))
 
 #define ORION5X_PCIE_VIRT_BASE         (ORION5X_REGS_VIRT_BASE | 0x40000)
-#define ORION5X_PCIE_REG(x)            (ORION5X_PCIE_VIRT_BASE | (x))
 
 #define ORION5X_USB0_PHYS_BASE         (ORION5X_REGS_PHYS_BASE | 0x50000)
 #define ORION5X_USB0_VIRT_BASE         (ORION5X_REGS_VIRT_BASE | 0x50000)
-#define ORION5X_USB0_REG(x)            (ORION5X_USB0_VIRT_BASE | (x))
 
 #define ORION5X_XOR_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x60900)
 #define ORION5X_XOR_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x60900)
-#define ORION5X_XOR_REG(x)             (ORION5X_XOR_VIRT_BASE | (x))
 
 #define ORION5X_ETH_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x70000)
 #define ORION5X_ETH_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x70000)
-#define ORION5X_ETH_REG(x)             (ORION5X_ETH_VIRT_BASE | (x))
 
 #define ORION5X_SATA_PHYS_BASE         (ORION5X_REGS_PHYS_BASE | 0x80000)
 #define ORION5X_SATA_VIRT_BASE         (ORION5X_REGS_VIRT_BASE | 0x80000)
-#define ORION5X_SATA_REG(x)            (ORION5X_SATA_VIRT_BASE | (x))
 
 #define ORION5X_USB1_PHYS_BASE         (ORION5X_REGS_PHYS_BASE | 0xa0000)
 #define ORION5X_USB1_VIRT_BASE         (ORION5X_REGS_VIRT_BASE | 0xa0000)
-#define ORION5X_USB1_REG(x)            (ORION5X_USB1_VIRT_BASE | (x))
 
 /*******************************************************************************
  * Device Bus Registers
 #define DEV_BUS_INT_CAUSE      ORION5X_DEV_BUS_REG(0x4d0)
 #define DEV_BUS_INT_MASK       ORION5X_DEV_BUS_REG(0x4d4)
 
-/***************************************************************************
- * Orion CPU Bridge Registers
- **************************************************************************/
-#define CPU_CONF               ORION5X_BRIDGE_REG(0x100)
-#define CPU_CTRL               ORION5X_BRIDGE_REG(0x104)
-#define CPU_RESET_MASK         ORION5X_BRIDGE_REG(0x108)
-#define  WDT_RESET             0x0002
-#define CPU_SOFT_RESET         ORION5X_BRIDGE_REG(0x10c)
-#define POWER_MNG_CTRL_REG     ORION5X_BRIDGE_REG(0x11C)
-#define BRIDGE_CAUSE           ORION5X_BRIDGE_REG(0x110)
-#define  WDT_INT_REQ           0x0008
-#define BRIDGE_MASK            ORION5X_BRIDGE_REG(0x114)
-#define  BRIDGE_INT_TIMER0     0x0002
-#define  BRIDGE_INT_TIMER1     0x0004
-#define  BRIDGE_INT_TIMER1_CLR (~0x0004)
-#define MAIN_IRQ_CAUSE         ORION5X_BRIDGE_REG(0x200)
-#define MAIN_IRQ_MASK          ORION5X_BRIDGE_REG(0x204)
-
+/*******************************************************************************
+ * Supported Devices & Revisions
+ ******************************************************************************/
+/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
+#define MV88F5181_DEV_ID       0x5181
+#define MV88F5181_REV_B1       3
+#define MV88F5181L_REV_A0      8
+#define MV88F5181L_REV_A1      9
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID       0x5182
+#define MV88F5182_REV_A2       2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID       0x5281
+#define MV88F5281_REV_D0       4
+#define MV88F5281_REV_D1       5
+#define MV88F5281_REV_D2       6
+/* Orion-1-90 (88F6183) */
+#define MV88F6183_DEV_ID       0x6183
+#define MV88F6183_REV_B0       3
 
 #endif
index 9b8db1d..e912490 100644 (file)
@@ -11,8 +11,7 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H
 
-#include <mach/hardware.h>
-#include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
 
 static inline void arch_idle(void)
 {
index e03f7b4..d7512b9 100644 (file)
@@ -15,7 +15,7 @@
 #include <linux/irq.h>
 #include <linux/io.h>
 #include <asm/gpio.h>
-#include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
 #include <plat/irq.h>
 #include "common.h"
 
index 68acca9..41e6d50 100644 (file)
@@ -26,6 +26,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/pci.h>
 #include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
 #include "common.h"
 #include "mpp.h"
 
index d0a785a..36dc541 100644 (file)
@@ -196,6 +196,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
 /*****************************************************************************
  * PCI controller
  ****************************************************************************/
+#define ORION5X_PCI_REG(x)     (ORION5X_PCI_VIRT_BASE | (x))
 #define PCI_MODE               ORION5X_PCI_REG(0xd00)
 #define PCI_CMD                        ORION5X_PCI_REG(0xc00)
 #define PCI_P2P_CONF           ORION5X_PCI_REG(0x1d14)
index 6fa2923..bdeb166 100644 (file)
@@ -16,7 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
-#include <mach/hardware.h>
+#include <mach/bridge-regs.h>
 
 /*
  * Number of timer ticks per jiffy.
index 7529616..2cde568 100644 (file)
@@ -22,6 +22,7 @@
 #include <linux/uaccess.h>
 #include <linux/io.h>
 #include <linux/spinlock.h>
+#include <mach/bridge-regs.h>
 #include <plat/orion5x_wdt.h>
 
 /*