ARM: tegra: xusb: set PD_CHRP and PD_DISC always zero
Ajay Gupta [Tue, 21 May 2013 15:54:04 +0000 (08:54 -0700)]
This is needed to save 4mW power.

Bug 1275290

Change-Id: Id96916c1a9d85f915284369942a59e454becc1d8
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: http://git-master/r/231016
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>

arch/arm/mach-tegra/board-dalmore.c
arch/arm/mach-tegra/board-pluto.c

index c90ff71..44b0350 100644 (file)
@@ -564,8 +564,8 @@ static struct tegra_xusb_pad_data xusb_padctl_data = {
        .ls_rslew = (0x3 << 14),
        .otg_pad0_ctl0 = (0x7 << 19),
        .otg_pad1_ctl0 = (0x0 << 19),
-       .otg_pad0_ctl1 = (0x4 << 0),
-       .otg_pad1_ctl1 = (0x3 << 0),
+       .otg_pad0_ctl1 = (0x0 << 0),
+       .otg_pad1_ctl1 = (0x0 << 0),
        .hs_disc_lvl = (0x5 << 2),
        .hsic_pad0_ctl0 = (0x00 << 8),
        .hsic_pad0_ctl1 = (0x00 << 8),
index 3e40015..3cc8821 100644 (file)
@@ -1144,8 +1144,8 @@ static struct tegra_xusb_pad_data xusb_padctl_data = {
        .ls_rslew = (0x3 << 14),
        .otg_pad0_ctl0 = (0x0 << 19),
        .otg_pad1_ctl0 = (0x7 << 19),
-       .otg_pad0_ctl1 = (0x3 << 0),
-       .otg_pad1_ctl1 = (0x4 << 0),
+       .otg_pad0_ctl1 = (0x0 << 0),
+       .otg_pad1_ctl1 = (0x0 << 0),
        .hs_disc_lvl = (0x5 << 2),
        .hsic_pad0_ctl0 = (0x00 << 8),
        .hsic_pad0_ctl1 = (0x00 << 8),