drm/radeon/kms: gfx init fixes for r6xx/r7xx
Alex Deucher [Fri, 5 Mar 2010 19:50:37 +0000 (14:50 -0500)]
This fixes some issues with the last gfx init patch.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/r600_cp.c
drivers/gpu/drm/radeon/rv770.c

index 5aee7fe..d568262 100644 (file)
@@ -1133,6 +1133,7 @@ void r600_gpu_init(struct radeon_device *rdev)
        /* Setup pipes */
        WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
        WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
+       WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 
        tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
        WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
index 40416c0..68e6f43 100644 (file)
@@ -1548,10 +1548,13 @@ static void r700_gfx_init(struct drm_device *dev,
 
        RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
        RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
+       RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 
        RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
        RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
        RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
+       RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
+       RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
 
        num_qd_pipes =
                R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8);
index 2f917db..86d39cb 100644 (file)
@@ -648,10 +648,13 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
        WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
        WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
+       WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
        WREG32(CC_SYS_RB_BACKEND_DISABLE,  cc_rb_backend_disable);
 
        WREG32(CGTS_SYS_TCC_DISABLE, 0);
        WREG32(CGTS_TCC_DISABLE, 0);
+       WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
+       WREG32(CGTS_USER_TCC_DISABLE, 0);
 
        num_qd_pipes =
                R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);