Merge branch 'drm-radeon-fusion' of ../drm-radeon-next into drm-core-next
Dave Airlie [Fri, 3 Dec 2010 04:01:08 +0000 (14:01 +1000)]
* 'drm-radeon-fusion' of ../drm-radeon-next:
  drm/radeon/kms: add Ontario APU ucode loading support
  drm/radeon/kms: add Ontario Fusion APU pci ids
  drm/radeon/kms: enable MSIs on fusion APUs
  drm/radeon/kms: add power table parsing support for Ontario fusion APUs
  drm/radeon/kms: refactor atombios power state fetching
  drm/radeon/kms: add bo blit support for Ontario fusion APUs
  drm/radeon/kms: add thermal sensor support for fusion APUs
  drm/radeon/kms: fill in GPU init for AMD Ontario Fusion APUs
  drm/radeon/kms: add radeon_asic struct for AMD Ontario fusion APUs
  drm/radeon/kms: evergreen.c updates for fusion
  drm/radeon/kms: MC setup changes for fusion APUs
  drm/radeon/kms: move r7xx/evergreen to its own vram_gtt setup function
  drm/radeon/kms: add support for ss overrides on Fusion APUs
  drm/radeon/kms: Add support for external encoders on fusion APUs
  drm/radeon/kms: atom changes for DCE4.1 devices
  drm/radeon/kms: add new family id for AMD Ontario APUs
  drm/radeon/kms: upstream power table updates
  drm/radeon/kms: upstream atombios.h updates
  drm/radeon/kms: upstream ObjectID.h updates
  drm/radeon/kms: setup mc chremap properly on r7xx/evergreen

1  2 
drivers/gpu/drm/radeon/evergreen.c
drivers/gpu/drm/radeon/r600.c
drivers/gpu/drm/radeon/radeon.h
drivers/gpu/drm/radeon/radeon_asic.c
drivers/gpu/drm/radeon/radeon_display.c
drivers/gpu/drm/radeon/radeon_irq_kms.c
drivers/gpu/drm/radeon/radeon_pm.c
drivers/gpu/drm/radeon/rv770.c
drivers/gpu/drm/radeon/rv770d.h

@@@ -2205,18 -2254,13 +2316,20 @@@ int evergreen_irq_set(struct radeon_dev
  
        WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
        WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
-       WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
-       WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
-       WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
-       WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
+       if (!(rdev->flags & RADEON_IS_IGP)) {
+               WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
+               WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
+               WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
+               WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
+       }
  
 +      WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
 +      WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
 +      WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
 +      WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
 +      WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
 +      WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
 +
        WREG32(DC_HPD1_INT_CONTROL, hpd1);
        WREG32(DC_HPD2_INT_CONTROL, hpd2);
        WREG32(DC_HPD3_INT_CONTROL, hpd3);
Simple merge
Simple merge
@@@ -788,11 -749,51 +788,54 @@@ static struct radeon_asic evergreen_asi
        .pm_finish = &evergreen_pm_finish,
        .pm_init_profile = &r600_pm_init_profile,
        .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
 +      .pre_page_flip = &evergreen_pre_page_flip,
 +      .page_flip = &evergreen_page_flip,
 +      .post_page_flip = &evergreen_post_page_flip,
  };
  
+ static struct radeon_asic sumo_asic = {
+       .init = &evergreen_init,
+       .fini = &evergreen_fini,
+       .suspend = &evergreen_suspend,
+       .resume = &evergreen_resume,
+       .cp_commit = &r600_cp_commit,
+       .gpu_is_lockup = &evergreen_gpu_is_lockup,
+       .asic_reset = &evergreen_asic_reset,
+       .vga_set_state = &r600_vga_set_state,
+       .gart_tlb_flush = &evergreen_pcie_gart_tlb_flush,
+       .gart_set_page = &rs600_gart_set_page,
+       .ring_test = &r600_ring_test,
+       .ring_ib_execute = &r600_ring_ib_execute,
+       .irq_set = &evergreen_irq_set,
+       .irq_process = &evergreen_irq_process,
+       .get_vblank_counter = &evergreen_get_vblank_counter,
+       .fence_ring_emit = &r600_fence_ring_emit,
+       .cs_parse = &evergreen_cs_parse,
+       .copy_blit = &evergreen_copy_blit,
+       .copy_dma = &evergreen_copy_blit,
+       .copy = &evergreen_copy_blit,
+       .get_engine_clock = &radeon_atom_get_engine_clock,
+       .set_engine_clock = &radeon_atom_set_engine_clock,
+       .get_memory_clock = NULL,
+       .set_memory_clock = NULL,
+       .get_pcie_lanes = NULL,
+       .set_pcie_lanes = NULL,
+       .set_clock_gating = NULL,
+       .set_surface_reg = r600_set_surface_reg,
+       .clear_surface_reg = r600_clear_surface_reg,
+       .bandwidth_update = &evergreen_bandwidth_update,
+       .hpd_init = &evergreen_hpd_init,
+       .hpd_fini = &evergreen_hpd_fini,
+       .hpd_sense = &evergreen_hpd_sense,
+       .hpd_set_polarity = &evergreen_hpd_set_polarity,
+       .gui_idle = &r600_gui_idle,
+       .pm_misc = &evergreen_pm_misc,
+       .pm_prepare = &evergreen_pm_prepare,
+       .pm_finish = &evergreen_pm_finish,
+       .pm_init_profile = &rs780_pm_init_profile,
+       .pm_get_dynpm_state = &r600_pm_get_dynpm_state,
+ };
  int radeon_asic_init(struct radeon_device *rdev)
  {
        radeon_register_accessor_init(rdev);
Simple merge
Simple merge
Simple merge